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Revision 451

Added by markw over 9 years ago

Added testbenches. Do not respond to bus cycles that do not target the cart

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ultimate_cart/veronica/sram.vhd
-- ======================================================================================
-- A generic VHDL entity for a typical SRAM with complete timing parameters
--
-- Static memory, version 1.3 9. August 1996
--
-- ======================================================================================
--
-- (C) Andre' Klindworth, Dept. of Computer Science
-- University of Hamburg
-- Vogt-Koelln-Str. 30
-- 22527 Hamburg
-- klindwor@informatik.uni-hamburg.de
--
-- This VHDL code may be freely copied as long as the copyright note isn't removed from
-- its header. Full affiliation of anybody modifying this file shall be added to the
-- header prior to further distribution.
-- The download procedure originates from DLX memory-behaviour.vhdl:
-- Copyright (C) 1993, Peter J. Ashenden
-- Mail: Dept. Computer Science
-- University of Adelaide, SA 5005, Australia
-- e-mail: petera@cs.adelaide.edu.au
--
--
--
-- Features:
--
-- o generic memory size, width and timing parameters
--
-- o 18 typical SRAM timing parameters supported
--
-- o clear-on-power-up and/or download-on-power-up if requested by generic
--
-- o RAM dump into or download from an ASCII-file at any time possible
-- (requested by signal)
--
-- o pair of active-low and active-high Chip-Enable signals
--
-- o nWE-only memory access control
--
-- o many (but not all) timing and access control violations reported by assertions
--
--
--
-- RAM data file format:
--
-- The format of the ASCII-files for RAM download or dump is very simple:
-- Each line of the file consists of the memory address (given as a decimal number).
-- and the corresponding RAM data at this address (given as a binary number).
-- Any text in a line following the width-th digit of the binary number is ignored.
-- Please notice that address and data have to be seperated by a SINGLE blank,
-- that the binary number must have as many digits as specified by the generic width,
-- and that no additional blanks or blank lines are tolerated. Example:
--
-- 0 0111011010111101 This text is interpreted as a comment
-- 1 1011101010110010
-- 17 0010001001000100
--
--
-- Hints & traps:
--
-- If you have problems using this model, please feel free to to send me an e-mail.
-- Here are some potential problems which have been reported to me:
--
-- o There's a potential problem with passing the filenames for RAM download or
-- dump via port signals of type string. E.g. for Synopsys VSS, the string
-- assigned to a filename-port should have the same length as its default value.
-- If you are sure that you need a download or dump only once during a single
-- simulation run, you may remove the filename-ports from the interface list
-- and replace the constant string in the corresponding file declarations.
--
-- o Some simulators do not implement all of the standard TEXTIO-functions as
-- specified by the IEEE Std 1076-87 and IEEE Std 1076-93. Check it out.
-- If any of the (multiple overloaded) writeline, write, readline or
-- read functions that are used in this model is missing, you have to
-- write your own version and you should complain at your simulator tool
-- vendor for this deviation from the standard.
--
-- o If you are about to simulate a large RAM e.g. 4M * 32 Bit, representing
-- the RAM with a static array variable of 4 * 32 std_logic values uses a large
-- amount of memory and may result in an out-of-memory error. A potential remedy
-- for this is to use a dynamic data type, allocating memory for small blocks of
-- RAM data (e.g. a single word) only if they are actually referenced during a
-- simulation run. A version of the SRAM model with dynamic memory allocation
-- shall be available at the same WWW-site were you obtained this file or at:
-- http://tech-www.informatik.uni-hamburg.de/vhdl/models/sram/sram.html
--
--
-- Bugs:
--
-- No severe bugs have been found so far. Please report any bugs:
-- e-mail: klindwor@informatik.uni-hamburg.de
--
USE std.textio.all;
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_unsigned.all;
USE IEEE.std_logic_textio.all;
ENTITY sram IS
GENERIC (
clear_on_power_up: boolean := FALSE; -- if TRUE, RAM is initialized with zeroes at start of simulation
-- Clearing of RAM is carried out before download takes place
download_on_power_up: boolean := TRUE; -- if TRUE, RAM is downloaded at start of simulation
trace_ram_load: boolean := TRUE; -- Echoes the data downloaded to the RAM on the screen
-- (included for debugging purposes)
enable_nWE_only_control: boolean := TRUE; -- Read-/write access controlled by nWE only
-- nOE may be kept active all the time
-- Configuring RAM size
size: INTEGER := 8; -- number of memory words
adr_width: INTEGER := 3; -- number of address bits
width: INTEGER := 8; -- number of bits per memory word
-- READ-cycle timing parameters
tAA_max: TIME := 20 NS; -- Address Access Time
tOHA_min: TIME := 3 NS; -- Output Hold Time
tACE_max: TIME := 20 NS; -- nCE/CE2 Access Time
tDOE_max: TIME := 8 NS; -- nOE Access Time
tLZOE_min: TIME := 0 NS; -- nOE to Low-Z Output
tHZOE_max: TIME := 8 NS; -- OE to High-Z Output
tLZCE_min: TIME := 3 NS; -- nCE/CE2 to Low-Z Output
tHZCE_max: TIME := 10 NS; -- CE/nCE2 to High Z Output
-- WRITE-cycle timing parameters
tWC_min: TIME := 20 NS; -- Write Cycle Time
tSCE_min: TIME := 18 NS; -- nCE/CE2 to Write End
tAW_min: TIME := 15 NS; -- tAW Address Set-up Time to Write End
tHA_min: TIME := 0 NS; -- tHA Address Hold from Write End
tSA_min: TIME := 0 NS; -- Address Set-up Time
tPWE_min: TIME := 13 NS; -- nWE Pulse Width
tSD_min: TIME := 10 NS; -- Data Set-up to Write End
tHD_min: TIME := 0 NS; -- Data Hold from Write End
tHZWE_max: TIME := 10 NS; -- nWE Low to High-Z Output
tLZWE_min: TIME := 0 NS -- nWE High to Low-Z Output
);
PORT (
nCE: IN std_logic := '1'; -- low-active Chip-Enable of the SRAM device; defaults to '1' (inactive)
nOE: IN std_logic := '1'; -- low-active Output-Enable of the SRAM device; defaults to '1' (inactive)
nWE: IN std_logic := '1'; -- low-active Write-Enable of the SRAM device; defaults to '1' (inactive)
A: IN std_logic_vector(adr_width-1 downto 0); -- address bus of the SRAM device
D: INOUT std_logic_vector(width-1 downto 0); -- bidirectional data bus to/from the SRAM device
CE2: IN std_logic := '1'; -- high-active Chip-Enable of the SRAM device; defaults to '1' (active)
download: IN boolean := FALSE; -- A FALSE-to-TRUE transition on this signal downloads the data
-- in file specified by download_filename to the RAM
download_filename: IN string := "sram_load.dat"; -- name of the download source file
-- Passing the filename via a port of type
-- ********** string may cause a problem with some
-- WATCH OUT! simulators. The string signal assigned
-- ********** to the port at least should have the
-- same length as the default value.
dump: IN boolean := FALSE; -- A FALSE-to-TRUE transition on this signal dumps
-- the current content of the memory to the file
-- specified by dump_filename.
dump_start: IN natural := 0; -- Written to the dump-file are the memory words from memory address
dump_end: IN natural := size-1; -- dump_start to address dump_end (default: all addresses)
dump_filename: IN string := "sram_dump.dat" -- name of the dump destination file
-- (See note at port download_filename)
);
END sram;
ARCHITECTURE behavior OF sram IS
FUNCTION Check_For_Valid_Data (a: std_logic_vector) RETURN BOOLEAN IS
VARIABLE result: BOOLEAN;
BEGIN
result := TRUE;
FOR i IN a'RANGE LOOP
result := (a(i) = '0') OR (a(i) = '1');
IF NOT result THEN EXIT;
END IF;
END LOOP;
RETURN result;
END Check_For_Valid_Data;
FUNCTION Check_For_Tristate (a: std_logic_vector) RETURN BOOLEAN IS
VARIABLE result: BOOLEAN;
BEGIN
result := TRUE;
FOR i IN a'RANGE LOOP
result := (a(i) = 'Z');
IF NOT result THEN EXIT;
END IF;
END LOOP;
RETURN result;
END Check_For_Tristate;
SIGNAL tristate_vec: std_logic_vector(D'RANGE); -- constant all-Z vector for data bus D
SIGNAL undef_vec: std_logic_vector(D'RANGE); -- constant all-X vector for data bus D
SIGNAL undef_adr_vec: std_logic_vector(A'RANGE); -- constant all-X vector for address bus
SIGNAL read_active: BOOLEAN := FALSE; -- Indicates whether the SRAM is sending on the D bus
SIGNAL read_valid: BOOLEAN := FALSE; -- If TRUE, the data output by the RAM is valid
SIGNAL read_data: std_logic_vector(D'RANGE); -- content of the memory location addressed by A
SIGNAL do_write: std_logic := '0'; -- A '0'->'1' transition on this signal marks
-- the moment when the data on D is stored in the
-- addressed memory location
SIGNAL adr_setup: std_logic_vector(A'RANGE); -- delayed value of A to model the Address Setup Time
SIGNAL adr_hold: std_logic_vector(A'RANGE); -- delayed value of A to model the Address Hold Time
SIGNAL valid_adr: std_logic_vector(A'RANGE); -- valid memory address derived from A after
-- considering Address Setup and Hold Times
BEGIN
PROCESS BEGIN -- static assignments to the variable length busses'
-- all-X and all-Z signal vectors
FOR i IN D'RANGE LOOP
tristate_vec(i) <= 'Z';
undef_vec(i) <= 'X';
END LOOP;
FOR i IN A'RANGE LOOP
undef_adr_vec(i) <= 'X';
END LOOP;
WAIT;
END PROCESS;
memory: PROCESS
CONSTANT low_address: natural := 0;
CONSTANT high_address: natural := size -1;
TYPE memory_array IS
ARRAY (natural RANGE low_address TO high_address) OF std_logic_vector(width-1 DOWNTO 0);
VARIABLE mem: memory_array;
VARIABLE address : natural;
VARIABLE write_data: std_logic_vector(width-1 DOWNTO 0);
PROCEDURE power_up (mem: inout memory_array; clear: boolean) IS
VARIABLE init_value: std_logic;
BEGIN
IF clear THEN
init_value := '0';
write(output, string'("Initializing SRAM with zero ...") );
ELSE
init_value := 'X';
END IF;
FOR add IN low_address TO high_address LOOP
FOR j IN (width-1) DOWNTO 0 LOOP
mem(add)(j) := init_value;
END LOOP;
END LOOP;
END power_up;
PROCEDURE load (mem: INOUT memory_array; download_filename: IN string) IS
FILE source : text IS IN download_filename;
VARIABLE inline, outline : line;
VARIABLE add: natural;
VARIABLE c : character;
VARIABLE source_line_nr: integer := 1;
VARIABLE init_value: std_logic := 'U';
BEGIN
write(output, string'("Loading SRAM from file ") & download_filename & string'(" ... ") );
WHILE NOT endfile(source) LOOP
readline(source, inline);
read(inline, add);
read(inline, c);
IF (c /= ' ') THEN
write(outline, string'("Syntax error in file '"));
write(outline, download_filename);
write(outline, string'("', line "));
write(outline, source_line_nr);
writeline(output, outline);
ASSERT FALSE
REPORT "RAM loader aborted."
SEVERITY FAILURE;
END IF;
FOR i IN (width -1) DOWNTO 0 LOOP
read(inline, c);
IF (c = '1') THEN
mem(add)(i) := '1';
ELSE
IF (c /= '0') THEN
write(outline, string'("-W- Invalid character '"));
write(outline, c);
write(outline, string'("' in Bitstring in '"));
write(outline, download_filename);
write(outline, '(');
write(outline, source_line_nr);
write(outline, string'(") is set to '0'"));
writeline(output, outline);
END IF;
mem(add)(i) := '0';
END IF;
END LOOP;
IF (trace_ram_load) THEN
write(outline, string'("RAM["));
write(outline, add);
write(outline, string'("] := "));
write(outline, mem(add));
writeline(output, outline );
END IF;
source_line_nr := source_line_nr +1;
END LOOP; -- WHILE
END load; -- PROCEDURE
PROCEDURE do_dump (mem: INOUT memory_array;
dump_start, dump_end: IN natural;
dump_filename: IN string) IS
FILE dest : text IS OUT dump_filename;
VARIABLE l : line;
VARIABLE c : character;
BEGIN
IF (dump_start > dump_end) OR (dump_end >= size) THEN
ASSERT FALSE
REPORT "Invalid addresses for memory dump. Cancelled."
SEVERITY ERROR;
ELSE
FOR add IN dump_start TO dump_end LOOP
write(l, add);
write(l, ' ');
FOR i IN (width-1) downto 0 LOOP
write(l, mem(add)(i));
END LOOP;
writeline(dest, l);
END LOOP;
END IF;
END do_dump; -- PROCEDURE
BEGIN
power_up(mem, clear_on_power_up);
IF download_on_power_up THEN
load(mem, download_filename);
END IF;
LOOP
IF do_write'EVENT and (do_write = '1') then
IF NOT Check_For_Valid_Data(D) THEN
IF D'EVENT AND Check_For_Valid_Data(D'DELAYED) THEN
write(output, "-W- Data changes exactly at end-of-write to SRAM.");
write_data := D'delayed;
ELSE
write(output, "-E- Data not valid at end-of-write to SRAM.");
write_data := undef_vec;
END IF;
ELSIF NOT D'DELAYED(tHD_min)'STABLE(tSD_min) THEN
write(output, "-E- tSD violation: Data input changes within setup-time at end-of-write to SRAM.");
write_data := undef_vec;
ELSIF NOT D'STABLE(tHD_min) THEN
write(output, "-E- tHD violation: Data input changes within hold-time at end-of-write to SRAM.");
write_data := undef_vec;
ELSIF nWE'DELAYED(tHD_min)'STABLE(tPWE_min) THEN
write(output, "-E- tPWE violation: Pulse width of nWE too short at SRAM.");
write_data := undef_vec;
ELSE write_data := D;
END IF;
mem(CONV_INTEGER(valid_adr)) := write_data;
END IF;
IF Check_For_Valid_Data(valid_adr) THEN
read_data <= mem(CONV_INTEGER(valid_adr));
ELSE
read_data <= undef_vec;
END IF;
IF dump AND dump'EVENT THEN do_dump(mem, dump_start, dump_end, dump_filename);
END IF;
IF download AND download'EVENT THEN load(mem, download_filename);
END IF;
WAIT ON do_write, valid_adr, dump, download;
END LOOP;
END PROCESS memory;
adr_setup <= TRANSPORT A AFTER tAA_max;
adr_hold <= TRANSPORT A AFTER tOHA_min;
valid_adr <= adr_setup WHEN Check_For_Valid_Data(adr_setup)
AND (adr_setup = adr_hold)
AND adr_hold'STABLE(tAA_max - tOHA_min) ELSE
undef_adr_vec;
read_active <= ( (nOE = '0') AND (nOE'DELAYED(tLZOE_min) = '0') AND nOE'STABLE(tLZOE_min)
AND ((nWE = '1') OR (nWE'DELAYED(tHZWE_max) = '0'))
AND (nCE = '0') AND (CE2 = '1') AND nCE'STABLE(tLZCE_min) AND CE2'STABLE(tLZCE_min))
OR (read_active AND (nOE'DELAYED(tHZOE_max) = '0')
AND (nWE'DELAYED(tHZWE_max) = '1')
AND (nCE'DELAYED(tHZCE_max) = '0') AND (CE2'DELAYED(tHZCE_max) = '1'));
read_valid <= ( (nOE = '0') AND nOE'STABLE(tDOE_max)
AND (nWE = '1') AND (nWE'DELAYED(tHZWE_max) = '1')
AND (nCE = '0') AND (CE2 = '1') AND nCE'STABLE(tACE_max) AND CE2'STABLE(tACE_max))
OR (read_valid AND read_active);
D <= read_data WHEN read_valid and read_active ELSE
undef_vec WHEN not read_valid and read_active ELSE
tristate_vec;
PROCESS (nWE, nCE, CE2)
BEGIN
IF ((nCE = '1') OR (nWE = '1') OR (CE2 = '0'))
AND (nCE'DELAYED = '0') AND (CE2'DELAYED = '1') AND (nWE'DELAYED = '0') -- End of Write
THEN
do_write <= '1' AFTER tHD_min;
ELSE
IF (Now > 10 NS) AND (nCE = '0') AND (CE2 = '1') AND (nWE = '0') -- Start of Write
THEN
ASSERT Check_For_Valid_Data(A)
REPORT "Address not valid at start-of-write to RAM."
SEVERITY FAILURE;
ASSERT A'STABLE(tSA_min)
REPORT "tSA violation: Address changed within setup-time at start-of-write to SRAM."
SEVERITY ERROR;
ASSERT enable_nWE_only_control OR ((nOE = '1') AND nOE'STABLE(tSA_min))
REPORT "tSA violation: nOE not inactive at start-of-write to RAM."
SEVERITY ERROR;
END IF;
do_write <= '0';
END IF;
END PROCESS;
-- The following processes check for validity of the control signals at the
-- SRAM interface. Removing them to speed up simulation will not affect the
-- functionality of the SRAM model.
PROCESS (A) -- Checks that an address change is allowed
BEGIN
IF (Now > 0 NS) THEN -- suppress obsolete error message at time 0
ASSERT (nCE = '1') OR (CE2 = '0') OR (nWE = '1')
REPORT "Address not stable while write-to-SRAM active"
SEVERITY FAILURE;
ASSERT (nCE = '1') OR (CE2 = '0') OR (nWE = '1')
OR (nCE'DELAYED(tHA_min) = '1') OR (CE2'DELAYED(tHA_min) = '0')
OR (nWE'DELAYED(tHA_min) = '1')
REPORT "tHA violation: Address changed within hold-time at end-of-write to SRAM."
SEVERITY FAILURE;
END IF;
END PROCESS;
PROCESS (nOE, nWE, nCE, CE2) -- Checks that control signals at RAM are valid all the time
BEGIN
IF (Now > 0 NS) AND (nCE /= '1') AND (CE2 /= '0') THEN
IF (nCE = '0') AND (CE2 = '1') THEN
ASSERT (nWE = '0') OR (nWE = '1')
REPORT "Invalid nWE-signal at SRAM while nCE is active"
SEVERITY WARNING;
ELSE
IF (nCE /= '0') THEN
ASSERT (nOE = '1')
REPORT "Invalid nCE-signal at SRAM while nOE not inactive"
SEVERITY WARNING;
ASSERT (nWE = '1')
REPORT "Invalid nCE-signal at SRAM while nWE not inactive"
SEVERITY ERROR;
END IF;
IF (CE2 /= '1') THEN
ASSERT (nOE = '1')
REPORT "Invalid CE2-signal at SRAM while nOE not inactive"
SEVERITY WARNING;
ASSERT (nWE = '1')
REPORT "Invalid CE2-signal at SRAM while nWE not inactive"
SEVERITY ERROR;
END IF;
END IF;
END IF;
END PROCESS;
END behavior;
ultimate_cart/veronica/README
This is not a 'real' veronica
Its a clone to try out Rob Finch's 65816 core - it will run on the ultimate cart (when finished, not ready yet)
If you like it consider buying the original real cartridge with a real 65816
ultimate_cart/veronica/cpu65816.wcfg
<?xml version="1.0" encoding="UTF-8"?>
<wave_config>
<wave_state>
</wave_state>
<db_ref_list>
<db_ref path="veronica.wdb" id="1" type="auto">
<top_modules>
<top_module name="attributes" />
<top_module name="numeric_std" />
<top_module name="std_logic_1164" />
<top_module name="std_logic_arith" />
<top_module name="std_logic_misc" />
<top_module name="std_logic_textio" />
<top_module name="std_logic_unsigned" />
<top_module name="textio" />
<top_module name="veronica_tb" />
<top_module name="vl_types" />
</top_modules>
</db_ref>
</db_ref_list>
<WVObjectSize size="40" />
<wvobject fp_name="/veronica_tb/thebigone/cpu_65816_rob/rst" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">rst</obj_property>
<obj_property name="ObjectShortName">rst</obj_property>
</wvobject>
<wvobject fp_name="/veronica_tb/thebigone/cpu_65816_rob/clk" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">clk</obj_property>
<obj_property name="ObjectShortName">clk</obj_property>
</wvobject>
<wvobject fp_name="divider60" type="divider">
<obj_property name="label">Input</obj_property>
<obj_property name="DisplayName">label</obj_property>
<obj_property name="BkColor">128 128 255</obj_property>
<obj_property name="TextColor">230 230 230</obj_property>
</wvobject>
<wvobject fp_name="/veronica_tb/thebigone/cpu_65816_rob/nmi" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">nmi</obj_property>
<obj_property name="ObjectShortName">nmi</obj_property>
</wvobject>
<wvobject fp_name="/veronica_tb/thebigone/cpu_65816_rob/irq" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">irq</obj_property>
<obj_property name="ObjectShortName">irq</obj_property>
</wvobject>
<wvobject fp_name="/veronica_tb/thebigone/cpu_65816_rob/abort" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">abort</obj_property>
<obj_property name="ObjectShortName">abort</obj_property>
</wvobject>
<wvobject fp_name="/veronica_tb/thebigone/cpu_65816_rob/rdy" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">rdy</obj_property>
<obj_property name="ObjectShortName">rdy</obj_property>
</wvobject>
<wvobject fp_name="/veronica_tb/thebigone/cpu_65816_rob/be" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">be</obj_property>
<obj_property name="ObjectShortName">be</obj_property>
</wvobject>
<wvobject fp_name="/veronica_tb/thebigone/cpu_65816_rob/db" type="array" db_ref_id="1">
<obj_property name="ElementShortName">db[7:0]</obj_property>
<obj_property name="ObjectShortName">db[7:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/veronica_tb/thebigone/cpu_65816_rob/err_i" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">err_i</obj_property>
<obj_property name="ObjectShortName">err_i</obj_property>
</wvobject>
<wvobject fp_name="/veronica_tb/thebigone/cpu_65816_rob/rty_i" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">rty_i</obj_property>
<obj_property name="ObjectShortName">rty_i</obj_property>
</wvobject>
<wvobject fp_name="divider71" type="divider">
<obj_property name="label">Output</obj_property>
<obj_property name="DisplayName">label</obj_property>
<obj_property name="BkColor">128 128 255</obj_property>
<obj_property name="TextColor">230 230 230</obj_property>
</wvobject>
<wvobject fp_name="/veronica_tb/thebigone/cpu_65816_rob/clko" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">clko</obj_property>
<obj_property name="ObjectShortName">clko</obj_property>
</wvobject>
<wvobject fp_name="/veronica_tb/thebigone/cpu_65816_rob/phi11" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">phi11</obj_property>
<obj_property name="ObjectShortName">phi11</obj_property>
</wvobject>
<wvobject fp_name="/veronica_tb/thebigone/cpu_65816_rob/phi12" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">phi12</obj_property>
<obj_property name="ObjectShortName">phi12</obj_property>
</wvobject>
<wvobject fp_name="/veronica_tb/thebigone/cpu_65816_rob/phi81" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">phi81</obj_property>
<obj_property name="ObjectShortName">phi81</obj_property>
</wvobject>
<wvobject fp_name="/veronica_tb/thebigone/cpu_65816_rob/phi82" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">phi82</obj_property>
<obj_property name="ObjectShortName">phi82</obj_property>
</wvobject>
<wvobject fp_name="/veronica_tb/thebigone/cpu_65816_rob/e" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">e</obj_property>
<obj_property name="ObjectShortName">e</obj_property>
</wvobject>
<wvobject fp_name="/veronica_tb/thebigone/cpu_65816_rob/mx" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">mx</obj_property>
<obj_property name="ObjectShortName">mx</obj_property>
</wvobject>
<wvobject fp_name="/veronica_tb/thebigone/cpu_65816_rob/rw" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">rw</obj_property>
<obj_property name="ObjectShortName">rw</obj_property>
</wvobject>
<wvobject fp_name="/veronica_tb/thebigone/cpu_65816_rob/ad" type="array" db_ref_id="1">
<obj_property name="ElementShortName">ad[23:0]</obj_property>
<obj_property name="ObjectShortName">ad[23:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/veronica_tb/thebigone/cpu_65816_rob/dw" type="array" db_ref_id="1">
<obj_property name="ElementShortName">dw[7:0]</obj_property>
<obj_property name="ObjectShortName">dw[7:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/veronica_tb/thebigone/cpu_65816_rob/cyc" type="array" db_ref_id="1">
<obj_property name="ElementShortName">cyc[4:0]</obj_property>
<obj_property name="ObjectShortName">cyc[4:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/veronica_tb/thebigone/cpu_65816_rob/vpa" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">vpa</obj_property>
<obj_property name="ObjectShortName">vpa</obj_property>
</wvobject>
<wvobject fp_name="/veronica_tb/thebigone/cpu_65816_rob/vda" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">vda</obj_property>
<obj_property name="ObjectShortName">vda</obj_property>
</wvobject>
<wvobject fp_name="/veronica_tb/thebigone/cpu_65816_rob/mlb" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">mlb</obj_property>
<obj_property name="ObjectShortName">mlb</obj_property>
</wvobject>
<wvobject fp_name="/veronica_tb/thebigone/cpu_65816_rob/vpb" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">vpb</obj_property>
<obj_property name="ObjectShortName">vpb</obj_property>
</wvobject>
<wvobject fp_name="divider95" type="divider">
<obj_property name="label">decode</obj_property>
<obj_property name="DisplayName">label</obj_property>
<obj_property name="BkColor">128 128 255</obj_property>
<obj_property name="TextColor">230 230 230</obj_property>
</wvobject>
<wvobject fp_name="/veronica_tb/thebigone/glue5/addr_in" type="array" db_ref_id="1">
<obj_property name="ElementShortName">addr_in[15:0]</obj_property>
<obj_property name="ObjectShortName">addr_in[15:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/veronica_tb/thebigone/glue5/window_address" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">window_address</obj_property>
<obj_property name="ObjectShortName">window_address</obj_property>
</wvobject>
<wvobject fp_name="/veronica_tb/thebigone/glue5/bank_half_select" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">bank_half_select</obj_property>
<obj_property name="ObjectShortName">bank_half_select</obj_property>
</wvobject>
<wvobject fp_name="/veronica_tb/thebigone/glue5/bank_select" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">bank_select</obj_property>
<obj_property name="ObjectShortName">bank_select</obj_property>
</wvobject>
<wvobject fp_name="/veronica_tb/thebigone/glue5/config_select" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">config_select</obj_property>
<obj_property name="ObjectShortName">config_select</obj_property>
</wvobject>
<wvobject fp_name="/veronica_tb/thebigone/glue5/sram_select" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">sram_select</obj_property>
<obj_property name="ObjectShortName">sram_select</obj_property>
</wvobject>
<wvobject fp_name="/veronica_tb/thebigone/glue5/sram_address" type="array" db_ref_id="1">
<obj_property name="ElementShortName">sram_address[16:0]</obj_property>
<obj_property name="ObjectShortName">sram_address[16:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="divider101" type="divider">
<obj_property name="label">sram</obj_property>
<obj_property name="DisplayName">label</obj_property>
<obj_property name="BkColor">128 128 255</obj_property>
<obj_property name="TextColor">230 230 230</obj_property>
</wvobject>
<wvobject fp_name="/veronica_tb/thebigone/glue6/sram_addr" type="array" db_ref_id="1">
<obj_property name="ElementShortName">sram_addr[19:0]</obj_property>
<obj_property name="ObjectShortName">sram_addr[19:0]</obj_property>
</wvobject>
<wvobject fp_name="/veronica_tb/thebigone/glue6/sram_data_out" type="array" db_ref_id="1">
<obj_property name="ElementShortName">sram_data_out[7:0]</obj_property>
<obj_property name="ObjectShortName">sram_data_out[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/veronica_tb/thebigone/glue6/sram_drive_data" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">sram_drive_data</obj_property>
<obj_property name="ObjectShortName">sram_drive_data</obj_property>
</wvobject>
<wvobject fp_name="/veronica_tb/thebigone/glue6/sram_we_n" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">sram_we_n</obj_property>
<obj_property name="ObjectShortName">sram_we_n</obj_property>
</wvobject>
</wave_config>
ultimate_cart/veronica/simulate_slave.sh
#!/bin/bash
echo "---------------------------------------------------------"
echo "Use 'simulate -run' to skip compilation stage."
echo "Use 'simulate -view' to show previous simulation results."
echo "---------------------------------------------------------"
name=slave
. /home/markw/fpga/xilinx/14.7/ISE_DS/settings32.sh
mkdir -p sim
pushd sim
# if we have a WDB file, we can view it if requested (otherwise we remove it)
if [ ! -e $name.wdb -o "$1" != "-view" ]; then
rm -f $name.wdb
# if we have a EXE, we can run it if requested (otherwise we remove it)
if [ ! -e $name.exe -o "$1" != "-run" ]; then
rm -f $name.exe
# copy testbench files
cp -p ../tb_slave/* .
# copy source files
cp ../slave_timing_6502.vhd .
cp ../memory_timing*.vhd .
cp ../synchronizer*.vhdl .
# cp `find ../a8core/ -iname "*.vhd"` .
# cp `find ../a8core/ -iname "*.vhdl"` .
# cp `find ../components/ -iname "*.vhd"` .
# cp `find ../components/ -iname "*.vhdl"` .
#
# set up project definition file
ls *.vhd* | perl -e 'while (<>){s/(.*)/vhdl work $1/;print $_;}' | cat > $name.prj
echo NumericStdNoWarnings = 1 >> xilinxsim.ini
# verbose & no multthreading - fallback in case of problems
# fuse -v 1 -mt off -incremental -prj %name%.prj -o %name%.exe -t %name%
fuse -timeprecision_vhdl 1fs -incremental -prj $name.prj -o $name.exe -t ${name}_tb || exit 1
# fuse --mt off -prj %name%.prj -o %name%.exe -t %name%_tb
# Check for the EXE again, independent of the errorlevel of fuse...
[ -e $name.exe ] || echo "No simulation executable created"
fi
# Open the iSIM GUI and run the simulation
./$name.exe -gui -f ../$name.cmd -wdb $name.wdb -log $name.log -view ../$name.wcfg || exit 1
#strace ./$name.exe -gui -f ../$name.cmd -wdb $name.wdb -log $name.log -view ../$name.wcfg >& out
#./$name.exe -h -log $name.log
else
# Only start the viewer on an existing wave configuration (from an old simulation)
isimgui -view ../$name.wcfg || exit 1
fi
popd
ultimate_cart/veronica/simulate_veronica.sh
#!/bin/bash
echo "---------------------------------------------------------"
echo "Use 'simulate -run' to skip compilation stage."
echo "Use 'simulate -view' to show previous simulation results."
echo "---------------------------------------------------------"
name=veronica
. /home/markw/fpga/xilinx/14.7/ISE_DS/settings32.sh
mkdir -p sim
pushd sim
# if we have a WDB file, we can view it if requested (otherwise we remove it)
if [ ! -e $name.wdb -o "$1" != "-view" ]; then
rm -f $name.wdb
# if we have a EXE, we can run it if requested (otherwise we remove it)
if [ ! -e $name.exe -o "$1" != "-run" ]; then
rm -f $name.exe
# copy source files
cp ../*.v* .
# copy testbench files
cp -p ../tb_veronica/* .
# cp `find ../a8core/ -iname "*.vhd"` .
# cp `find ../a8core/ -iname "*.vhdl"` .
# cp `find ../components/ -iname "*.vhd"` .
# cp `find ../components/ -iname "*.vhdl"` .
#
# set up project definition file
ls BCDMath.v | perl -e 'while (<>){s/(.*)/verilog work $1/;print $_;}' | cat > $name.prj
ls FT816.v | perl -e 'while (<>){s/(.*)/verilog work $1/;print $_;}' | cat >> $name.prj
ls *.vhd* | perl -e 'while (<>){s/(.*)/vhdl work $1/;print $_;}' | cat >> $name.prj
echo NumericStdNoWarnings = 1 >> xilinxsim.ini
# verbose & no multthreading - fallback in case of problems
# fuse -v 1 -mt off -incremental -prj %name%.prj -o %name%.exe -t %name%
fuse -timeprecision_vhdl 1fs -incremental -prj $name.prj -o $name.exe -t ${name}_tb || exit 1
# fuse --mt off -prj %name%.prj -o %name%.exe -t %name%_tb
# Check for the EXE again, independent of the errorlevel of fuse...
[ -e $name.exe ] || echo "No simulation executable created"
fi
# Open the iSIM GUI and run the simulation
./$name.exe -gui -f ../$name.cmd -wdb $name.wdb -log $name.log -view ../$name.wcfg || exit 1
#strace ./$name.exe -gui -f ../$name.cmd -wdb $name.wdb -log $name.log -view ../$name.wcfg >& out
#./$name.exe -h -log $name.log
else
# Only start the viewer on an existing wave configuration (from an old simulation)
isimgui -view ../$name.wcfg || exit 1
fi
popd
ultimate_cart/veronica/slave.wcfg
<?xml version="1.0" encoding="UTF-8"?>
<wave_config>
<wave_state>
</wave_state>
<db_ref_list>
<db_ref path="slave.wdb" id="1" type="auto">
<top_modules>
<top_module name="attributes" />
<top_module name="numeric_std" />
<top_module name="slave_tb" />
<top_module name="std_logic_1164" />
<top_module name="std_logic_arith" />
<top_module name="std_logic_misc" />
<top_module name="std_logic_textio" />
<top_module name="std_logic_unsigned" />
<top_module name="textio" />
</top_modules>
</db_ref>
</db_ref_list>
<WVObjectSize size="36" />
<wvobject fp_name="/slave_tb/bus_adaptor/bus_data_out" type="array" db_ref_id="1">
<obj_property name="ElementShortName">bus_data_out[7:0]</obj_property>
<obj_property name="ObjectShortName">bus_data_out[7:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/slave_tb/bus_adaptor/bus_data_oe" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">bus_data_oe</obj_property>
<obj_property name="ObjectShortName">bus_data_oe</obj_property>
</wvobject>
<wvobject fp_name="/slave_tb/cart_addr" type="array" db_ref_id="1">
<obj_property name="ElementShortName">cart_addr[12:0]</obj_property>
<obj_property name="ObjectShortName">cart_addr[12:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/slave_tb/cart_data" type="array" db_ref_id="1">
<obj_property name="ElementShortName">cart_data[7:0]</obj_property>
<obj_property name="ObjectShortName">cart_data[7:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/slave_tb/cart_rd5" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">cart_rd5</obj_property>
<obj_property name="ObjectShortName">cart_rd5</obj_property>
</wvobject>
<wvobject fp_name="/slave_tb/cart_rd4" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">cart_rd4</obj_property>
<obj_property name="ObjectShortName">cart_rd4</obj_property>
</wvobject>
<wvobject fp_name="/slave_tb/cart_s5" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">cart_s5</obj_property>
<obj_property name="ObjectShortName">cart_s5</obj_property>
</wvobject>
<wvobject fp_name="/slave_tb/cart_s4" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">cart_s4</obj_property>
<obj_property name="ObjectShortName">cart_s4</obj_property>
</wvobject>
<wvobject fp_name="/slave_tb/cart_phi2" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">cart_phi2</obj_property>
<obj_property name="ObjectShortName">cart_phi2</obj_property>
</wvobject>
<wvobject fp_name="/slave_tb/cart_ctl" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">cart_ctl</obj_property>
<obj_property name="ObjectShortName">cart_ctl</obj_property>
</wvobject>
<wvobject fp_name="/slave_tb/cart_rw" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">cart_rw</obj_property>
<obj_property name="ObjectShortName">cart_rw</obj_property>
</wvobject>
<wvobject fp_name="/slave_tb/bus_adaptor/enable_179_early" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">enable_179_early</obj_property>
<obj_property name="ObjectShortName">enable_179_early</obj_property>
</wvobject>
<wvobject fp_name="/slave_tb/bus_adaptor/request" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">request</obj_property>
<obj_property name="ObjectShortName">request</obj_property>
</wvobject>
<wvobject fp_name="/slave_tb/glue3/phi2" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">phi2</obj_property>
<obj_property name="ObjectShortName">phi2</obj_property>
</wvobject>
<wvobject fp_name="/slave_tb/glue3/phi_edge_prev_reg" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">phi_edge_prev_reg</obj_property>
<obj_property name="ObjectShortName">phi_edge_prev_reg</obj_property>
</wvobject>
<wvobject fp_name="/slave_tb/glue3/phi2_sync" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">phi2_sync</obj_property>
<obj_property name="ObjectShortName">phi2_sync</obj_property>
</wvobject>
<wvobject fp_name="/slave_tb/glue3/addr_in" type="array" db_ref_id="1">
<obj_property name="ElementShortName">addr_in[12:0]</obj_property>
<obj_property name="ObjectShortName">addr_in[12:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/slave_tb/glue3/data_in" type="array" db_ref_id="1">
<obj_property name="ElementShortName">data_in[7:0]</obj_property>
<obj_property name="ObjectShortName">data_in[7:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/slave_tb/glue3/data_out" type="array" db_ref_id="1">
<obj_property name="ElementShortName">data_out[7:0]</obj_property>
<obj_property name="ObjectShortName">data_out[7:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/slave_tb/glue3/state_reg" type="array" db_ref_id="1">
<obj_property name="ElementShortName">state_reg[2:0]</obj_property>
<obj_property name="ObjectShortName">state_reg[2:0]</obj_property>
</wvobject>
<wvobject fp_name="/slave_tb/glue3/delay_reg" type="array" db_ref_id="1">
<obj_property name="ElementShortName">delay_reg[60:0]</obj_property>
<obj_property name="ObjectShortName">delay_reg[60:0]</obj_property>
</wvobject>
<wvobject fp_name="/slave_tb/glue3/bus_data_out" type="array" db_ref_id="1">
<obj_property name="ElementShortName">bus_data_out[7:0]</obj_property>
<obj_property name="ObjectShortName">bus_data_out[7:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/slave_tb/glue3/bus_drive" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">bus_drive</obj_property>
<obj_property name="ObjectShortName">bus_drive</obj_property>
</wvobject>
<wvobject fp_name="/slave_tb/clk7x" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">clk7x</obj_property>
<obj_property name="ObjectShortName">clk7x</obj_property>
</wvobject>
<wvobject fp_name="/slave_tb/glue3/state_reg" type="array" db_ref_id="1">
<obj_property name="ElementShortName">state_reg[2:0]</obj_property>
<obj_property name="ObjectShortName">state_reg[2:0]</obj_property>
</wvobject>
<wvobject fp_name="/slave_tb/glue3/internal_memory_request" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">internal_memory_request</obj_property>
<obj_property name="ObjectShortName">internal_memory_request</obj_property>
</wvobject>
<wvobject fp_name="divider27" type="divider">
<obj_property name="label">Outputs</obj_property>
<obj_property name="DisplayName">label</obj_property>
<obj_property name="BkColor">128 128 255</obj_property>
<obj_property name="TextColor">230 230 230</obj_property>
</wvobject>
<wvobject fp_name="/slave_tb/glue3/bus_data_out" type="array" db_ref_id="1">
<obj_property name="ElementShortName">bus_data_out[7:0]</obj_property>
<obj_property name="ObjectShortName">bus_data_out[7:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/slave_tb/glue3/bus_drive" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">bus_drive</obj_property>
<obj_property name="ObjectShortName">bus_drive</obj_property>
</wvobject>
<wvobject fp_name="/slave_tb/glue3/bus_request" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">bus_request</obj_property>
<obj_property name="ObjectShortName">bus_request</obj_property>
</wvobject>
<wvobject fp_name="/slave_tb/glue3/addr_in" type="array" db_ref_id="1">
<obj_property name="ElementShortName">addr_in[12:0]</obj_property>
<obj_property name="ObjectShortName">addr_in[12:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/slave_tb/glue3/data_in" type="array" db_ref_id="1">
<obj_property name="ElementShortName">data_in[7:0]</obj_property>
<obj_property name="ObjectShortName">data_in[7:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/slave_tb/glue3/rw_n" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">rw_n</obj_property>
<obj_property name="ObjectShortName">rw_n</obj_property>
</wvobject>
<wvobject fp_name="/slave_tb/glue3/s4_n" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">s4_n</obj_property>
<obj_property name="ObjectShortName">s4_n</obj_property>
</wvobject>
<wvobject fp_name="/slave_tb/glue3/s5_n" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">s5_n</obj_property>
<obj_property name="ObjectShortName">s5_n</obj_property>
</wvobject>
<wvobject fp_name="/slave_tb/glue3/ctl_n" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">ctl_n</obj_property>
<obj_property name="ObjectShortName">ctl_n</obj_property>
</wvobject>
</wave_config>
ultimate_cart/veronica/slave_timing_6502.vhd
state_next <= state_reg;
case (state_reg) is
when state_wait_addrctl =>
if (delay_reg(17)='1') then -- n+4 cycles
if ((not(bus_s4_n and bus_s5_n and bus_ctl_n) and delay_reg(17))='1') then -- n+4 cycles
-- snap control signals, should be stable by now
bus_addr_in_next <= bus_addr;
bus_rw_n_next <= bus_rw_n;
ultimate_cart/veronica/sram.wcfg
<?xml version="1.0" encoding="UTF-8"?>
<wave_config>
<wave_state>
</wave_state>
<db_ref_list>
<db_ref path="sram.wdb" id="1" type="auto">
<top_modules>
<top_module name="numeric_std" />
<top_module name="sram_tb" />
<top_module name="std_logic_1164" />
<top_module name="std_logic_arith" />
<top_module name="std_logic_textio" />
<top_module name="std_logic_unsigned" />
<top_module name="textio" />
</top_modules>
</db_ref>
</db_ref_list>
<WVObjectSize size="12" />
<wvobject fp_name="/sram_tb/clk" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">clk</obj_property>
<obj_property name="ObjectShortName">clk</obj_property>
</wvobject>
<wvobject fp_name="/sram_tb/clk_fast" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">clk_fast</obj_property>
<obj_property name="ObjectShortName">clk_fast</obj_property>
</wvobject>
<wvobject fp_name="/sram_tb/glue6/tick_reg" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">tick_reg</obj_property>
<obj_property name="ObjectShortName">tick_reg</obj_property>
</wvobject>
<wvobject fp_name="/sram_tb/glue6/tick_fast_reg" type="array" db_ref_id="1">
<obj_property name="ElementShortName">tick_fast_reg[6:0]</obj_property>
<obj_property name="ObjectShortName">tick_fast_reg[6:0]</obj_property>
</wvobject>
<wvobject fp_name="/sram_tb/glue6/tick_last_fast_reg" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">tick_last_fast_reg</obj_property>
<obj_property name="ObjectShortName">tick_last_fast_reg</obj_property>
</wvobject>
<wvobject fp_name="/sram_tb/glue6/atari_bus_request" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">atari_bus_request</obj_property>
<obj_property name="ObjectShortName">atari_bus_request</obj_property>
</wvobject>
<wvobject fp_name="/sram_tb/sram_drive_data" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">sram_drive_data</obj_property>
<obj_property name="ObjectShortName">sram_drive_data</obj_property>
</wvobject>
<wvobject fp_name="/sram_tb/ext_sram_addr" type="array" db_ref_id="1">
<obj_property name="ElementShortName">ext_sram_addr[19:0]</obj_property>
<obj_property name="ObjectShortName">ext_sram_addr[19:0]</obj_property>
</wvobject>
<wvobject fp_name="/sram_tb/ext_sram_data" type="array" db_ref_id="1">
<obj_property name="ElementShortName">ext_sram_data[7:0]</obj_property>
<obj_property name="ObjectShortName">ext_sram_data[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/sram_tb/ext_sram_oe" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">ext_sram_oe</obj_property>
<obj_property name="ObjectShortName">ext_sram_oe</obj_property>
</wvobject>
<wvobject fp_name="/sram_tb/ext_sram_we" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">ext_sram_we</obj_property>
<obj_property name="ObjectShortName">ext_sram_we</obj_property>
</wvobject>
<wvobject fp_name="/sram_tb/glue6/sram_we_n" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">sram_we_n</obj_property>
<obj_property name="ObjectShortName">sram_we_n</obj_property>
</wvobject>
</wave_config>
ultimate_cart/veronica/tb_slave/slave_tb.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
library std_developerskit ; -- used for to_string
-- use std_developerskit.std_iopak.all;
entity slave_tb is
end;
architecture rtl of slave_tb is
constant CLK_FAST_PERIOD : time := 1 us / (14*7);
constant CLK_PERIOD : time := 1 us / (14);
constant CLK_CART_PERIOD : time := 1 us / (1.79*32);
signal reset_n : std_logic;
signal clk7x : std_logic;
signal clk : std_logic;
signal clk_cart : std_logic;
signal EXT_SRAM_ADDR: std_logic_vector(19 downto 0);
signal EXT_SRAM_DATA: std_logic_vector(7 downto 0);
signal EXT_SRAM_CE: std_logic;
signal EXT_SRAM_OE: std_logic;
signal EXT_SRAM_WE: std_logic;
signal CART_ADDR: std_logic_vector(12 downto 0);
signal CART_DATA: std_logic_vector(7 downto 0);
signal CART_RD5: std_logic;
signal CART_RD4: std_logic;
signal CART_S5: std_logic;
signal CART_S4: std_logic;
signal CART_PHI2: std_logic;
signal CART_CTL: std_logic;
signal CART_RW: std_logic;
-- 65816 bus
signal veronica_address : std_logic_vector(23 downto 0);
signal veronica_read_data : std_logic_vector(7 downto 0);
signal veronica_write_data : std_logic_vector(7 downto 0);
signal veronica_w_n : std_logic;
signal veronica_config_w_n : std_logic;
-- 6502 bus
signal atari_bus_request : std_logic;
signal atari_address : std_logic_vector(12 downto 0);
signal atari_data_bus : std_logic_vector(7 downto 0);
signal atari_read_data : std_logic_vector(7 downto 0);
signal atari_write_data : std_logic_vector(7 downto 0);
signal atari_w_n : std_logic;
signal atari_config_w_n : std_logic;
signal atari_s4 : std_logic;
signal atari_s5 : std_logic;
signal atari_ctl : std_logic;
-- address decode
signal veronica_config_select : std_logic;
signal veronica_sram_select : std_logic;
signal veronica_sram_address: std_logic_vector(16 downto 0);
signal atari_config_select : std_logic;
signal atari_sram_select : std_logic;
signal atari_sram_address: std_logic_vector(16 downto 0);
-- veronica config
signal veronica_window_address : std_logic;
signal veronica_bank_half_select : std_logic;
signal veronica_config_data : std_logic_vector(7 downto 0);
-- atari config
signal atari_banka_enable : std_logic;
signal atari_bank8_enable : std_logic;
signal atari_bank_half_select : std_logic;
signal atari_config_data : std_logic_vector(7 downto 0);
-- common config
signal common_sem : std_logic;
signal common_bank_select : std_logic;
-- cart driving
signal cart_bus_data_out : std_logic_vector(7 downto 0);
signal cart_bus_drive : std_logic;
-- sram driving
signal sram_write_data : std_logic_vector(7 downto 0);
signal sram_drive_data : std_logic;
signal sram_read_data : std_logic_vector(7 downto 0);
-- 6502 bus other side
signal enable_179_early : std_logic;
signal cart_request : std_logic;
signal pbi_addr_out : std_logic_vector(15 downto 0);
signal cart_data_write : std_logic_vector(7 downto 0);
signal pbi_write_enable : std_logic;
signal s4_n : std_logic;
signal s5_n : std_logic;
signal cctl_n : std_logic;
signal cart_data_read : std_logic_vector(7 downto 0);
signal cart_complete : std_logic;
signal bus_data_in : std_logic_vector(7 downto 0);
signal bus_data_out : std_logic_vector(7 downto 0);
signal bus_data_oe : std_logic;
signal bus_addr_out : std_logic_vector(15 downto 0);
signal bus_addr_oe : std_logic;
signal bus_write_n : std_logic;
signal bus_s4_n : std_logic;
signal bus_s5_n : std_logic;
signal bus_cctl_n : std_logic;
signal bus_control_oe : std_logic;
begin
p_clk_gen_a : process
begin
clk <= '1';
wait for CLK_PERIOD/2;
clk <= '0';
wait for CLK_PERIOD - (CLK_PERIOD/2 );
end process;
p_clk_gen_b : process
begin
clk_cart <= '1';
wait for CLK_CART_PERIOD/2;
clk_cart <= '0';
wait for CLK_CART_PERIOD - (CLK_CART_PERIOD/2 );
end process;
p_clk_gen_c : process
begin
clk7x <= '1';
wait for CLK_FAST_PERIOD/2;
clk7x <= '0';
wait for CLK_FAST_PERIOD - (CLK_FAST_PERIOD/2 );
end process;
reset_n <= '0', '1' after 1000ns;
process_enable : process
begin
wait until clk_cart'event and clk_cart = '1';
enable_179_early <= '1'; -- HERE!
wait until clk_cart'event and clk_cart = '1';
enable_179_early <= '0';
wait until clk_cart'event and clk_cart = '1';
enable_179_early <= '0';
wait until clk_cart'event and clk_cart = '1';
enable_179_early <= '0';
wait until clk_cart'event and clk_cart = '1';
enable_179_early <= '0';
wait until clk_cart'event and clk_cart = '1';
enable_179_early <= '0';
wait until clk_cart'event and clk_cart = '1';
enable_179_early <= '0';
wait until clk_cart'event and clk_cart = '1';
enable_179_early <= '0';
wait until clk_cart'event and clk_cart = '1';
enable_179_early <= '0';
wait until clk_cart'event and clk_cart = '1';
enable_179_early <= '0';
wait until clk_cart'event and clk_cart = '1';
enable_179_early <= '0';
wait until clk_cart'event and clk_cart = '1';
enable_179_early <= '0';
wait until clk_cart'event and clk_cart = '1';
enable_179_early <= '0';
wait until clk_cart'event and clk_cart = '1';
enable_179_early <= '0';
wait until clk_cart'event and clk_cart = '1';
enable_179_early <= '0';
wait until clk_cart'event and clk_cart = '1';
enable_179_early <= '0';
wait until clk_cart'event and clk_cart = '1';
enable_179_early <= '0';
wait until clk_cart'event and clk_cart = '1';
enable_179_early <= '0';
wait until clk_cart'event and clk_cart = '1';
enable_179_early <= '0';
wait until clk_cart'event and clk_cart = '1';
enable_179_early <= '0';
wait until clk_cart'event and clk_cart = '1';
enable_179_early <= '0';
wait until clk_cart'event and clk_cart = '1';
enable_179_early <= '0';
wait until clk_cart'event and clk_cart = '1';
enable_179_early <= '0';
wait until clk_cart'event and clk_cart = '1';
enable_179_early <= '0';
wait until clk_cart'event and clk_cart = '1';
enable_179_early <= '0';
wait until clk_cart'event and clk_cart = '1';
enable_179_early <= '0';
wait until clk_cart'event and clk_cart = '1';
enable_179_early <= '0';
wait until clk_cart'event and clk_cart = '1';
enable_179_early <= '0';
wait until clk_cart'event and clk_cart = '1';
enable_179_early <= '0';
wait until clk_cart'event and clk_cart = '1';
enable_179_early <= '0';
wait until clk_cart'event and clk_cart = '1';
enable_179_early <= '0';
wait until clk_cart'event and clk_cart = '1';
enable_179_early <= '0';
end process;
process_setup_sram : process
begin
cart_request <= '0';
pbi_addr_out <= (others=>'0');
cart_data_write <= (others=>'0');
pbi_write_enable <= '0';
s4_n <= '1';
s5_n <= '1';
cctl_n <= '1';
wait for 3000ns;
wait until enable_179_early'event and enable_179_early = '1';
cart_request <= '1';
pbi_addr_out <= x"D402";
cart_data_write <= x"65";
pbi_write_enable <= '1';
s4_n <= '0';
wait until enable_179_early'event and enable_179_early = '1';
cart_request <= '1';
pbi_addr_out <= x"D513";
cart_data_write <= x"56";
pbi_write_enable <= '1';
s5_n <= '0';
s4_n <= '1';
wait until enable_179_early'event and enable_179_early = '1';
cart_request <= '1';
pbi_addr_out <= x"D402";
cart_data_write <= x"65";
pbi_write_enable <= '1';
wait until enable_179_early'event and enable_179_early = '1';
cart_request <= '0';
wait for 100000000us;
end process;
glue3: entity work.slave_timing_6502
port map
(
clk => clk,
clk7x => clk7x,
reset_n => reset_n,
phi2 => CART_PHI2,
bus_addr => CART_ADDR,
bus_data => CART_DATA,
bus_ctl_n => CART_CTL,
bus_rw_n => CART_RW,
bus_s4_n => CART_S4,
bus_s5_n => CART_S5,
bus_data_out => cart_bus_data_out,
bus_drive => cart_bus_drive,
s4_n => atari_s4,
s5_n => atari_s5,
ctl_n => atari_ctl,
addr_in => atari_address,
data_in => atari_write_data,
data_out => atari_read_data,
rw_n => atari_w_n,
bus_request => atari_bus_request
);
CART_DATA <= cart_bus_data_out when cart_bus_drive='1' else (others=>'Z');
atari_read_data <= x"12" when atari_bus_request='1' else (others=>'U');
bus_adaptor : ENTITY work.timing6502
GENERIC MAP
(
CYCLE_LENGTH => 32,
CONTROl_BITS => 3
)
PORT MAP
(
CLK => clk_cart,
RESET_N => reset_n,
-- FPGA side
ENABLE_179_EARLY =>enable_179_early,
REQUEST => cart_request,
ADDR_IN => pbi_addr_out,
DATA_IN => cart_data_write,
WRITE_IN => pbi_write_enable,
CONTROL_N_IN => s4_n&s5_n&cctl_n,
DATA_OUT => cart_data_read,
COMPLETE => cart_complete,
-- 6502 side
BUS_DATA_IN => CART_DATA,
BUS_PHI1 => open,
BUS_PHI2 => CART_PHI2,
BUS_SUBCYCLE => open,
BUS_ADDR_OUT => bus_addr_out,
BUS_ADDR_OE => bus_addr_oe,
BUS_DATA_OUT => bus_data_out,
BUS_DATA_OE => bus_data_oe,
BUS_WRITE_N => CART_RW,
BUS_CONTROL_N(2) => bus_s4_n,
BUS_CONTROL_N(1) => bus_s5_n,
BUS_CONTROL_N(0) => bus_cctl_n,
BUS_CONTROL_OE => bus_control_oe
);
CART_ADDR <= bus_addr_out when bus_addr_oe='1' else (others=>'Z');
CART_DATA <= bus_data_out when bus_data_oe='1' else (others=>'Z');
CART_S4 <= bus_s4_n when bus_control_oe='1' else 'Z';
CART_S5 <= bus_s5_n when bus_control_oe='1' else 'Z';
... This diff was truncated because it exceeds the maximum size that can be displayed.

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