EclaireXL

sram model for tb

Moved memory timing bridge inside slave_timing, its an internal detail really

Adjusted delays and verified in sim

Trivial but important fixes, thanks to quartus warnings

70ns accuracy is not enough for reliable Atari bus sampling, use faster clock we are already using for sram

Register bus_data before we write it

Fixed c0 decode and made more explicit

Simulated and repaired 6502 bus and sram bus

constraint all cart input/outputs - 1.79MHz so not a problem. Improve sram constraints - including adding a bit of hold time.

register output data