Revision 45
Added by markw over 11 years ago
| mcc216/atari800core.qsf | ||
|---|---|---|
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set_global_assignment -name QIP_FILE pll_downstream_ntsc.qip
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set_global_assignment -name SDC_FILE atari800core.sdc
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set_global_assignment -name VERILOG_FILE sdram_ctrl_3_ports.v
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set_global_assignment -name VHDL_FILE zpu_rom.vhdl
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set_global_assignment -name VHDL_FILE atari800core_mcc.vhd
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set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
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| mcc216/atari800core_mcc.vhd | ||
|---|---|---|
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SIGNAL CONSOL_SELECT : std_logic;
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SIGNAL CONSOL_OPTION : std_logic;
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-- 6502 throttling
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SIGNAL THROTTLE_COUNT_6502 : std_logic_vector(5 downto 0);
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-- scandoubler
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signal scandouble_clk : std_logic;
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| ... | ... | |
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signal svideo_y : std_logic_vector(7 downto 0);
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signal svideo_c : std_logic_vector(5 downto 0);
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-- dma/virtual drive
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signal DMA_ADDR_FETCH : std_logic_vector(23 downto 0);
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signal DMA_WRITE_DATA : std_logic_vector(31 downto 0);
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signal DMA_FETCH : std_logic;
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signal DMA_32BIT_WRITE_ENABLE : std_logic;
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signal DMA_16BIT_WRITE_ENABLE : std_logic;
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signal DMA_8BIT_WRITE_ENABLE : std_logic;
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signal DMA_READ_ENABLE : std_logic;
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signal DMA_MEMORY_READY : std_logic;
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signal DMA_MEMORY_DATA : std_logic_vector(31 downto 0);
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signal ZPU_ADDR_ROM : std_logic_vector(15 downto 0);
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signal ZPU_ROM_DATA : std_logic_vector(31 downto 0);
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signal ZPU_OUT1 : std_logic_vector(31 downto 0);
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signal ZPU_OUT2 : std_logic_vector(31 downto 0);
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signal ZPU_OUT3 : std_logic_vector(31 downto 0);
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signal ZPU_OUT4 : std_logic_vector(31 downto 0);
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signal zpu_pokey_enable : std_logic;
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signal zpu_sio_txd : std_logic;
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signal zpu_sio_rxd : std_logic;
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signal zpu_sio_command : std_logic;
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-- system control from zpu
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signal ram_select : std_logic_vector(2 downto 0);
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signal rom_select : std_logic_vector(5 downto 0);
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signal reset_atari : std_logic;
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signal pause_atari : std_logic;
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SIGNAL speed_6502 : std_logic_vector(5 downto 0);
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BEGIN
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dac_left : hq_dac
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| ... | ... | |
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JOY1_IN_N <= JOY1_n(4)&JOY1_n(0)&JOY1_n(1)&JOY1_n(2)&JOY1_n(3);
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JOY2_IN_N <= JOY2_n(4)&JOY2_n(0)&JOY2_n(1)&JOY2_n(2)&JOY2_n(3);
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-- THROTTLE
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THROTTLE_COUNT_6502 <= std_logic_vector(to_unsigned(1,6));
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--atari800xl : entity work.atari800core_helloworld
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-- GENERIC MAP
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| ... | ... | |
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KEYBOARD_RESPONSE => KEYBOARD_RESPONSE,
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KEYBOARD_SCAN => KEYBOARD_SCAN,
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SIO_COMMAND => open,
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SIO_RXD => '1',
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SIO_TXD => open,
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SIO_COMMAND => zpu_sio_command,
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SIO_RXD => zpu_sio_txd,
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SIO_TXD => zpu_sio_rxd,
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CONSOL_OPTION => CONSOL_OPTION,
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CONSOL_SELECT => CONSOL_SELECT,
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| ... | ... | |
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SDRAM_8BIT_WRITE_ENABLE => SDRAM_WIDTH_8bit_ACCESS,
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SDRAM_REFRESH => SDRAM_REFRESH,
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DMA_FETCH => '0',
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DMA_READ_ENABLE => '0',
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DMA_32BIT_WRITE_ENABLE => '0',
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DMA_16BIT_WRITE_ENABLE => '0',
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DMA_8BIT_WRITE_ENABLE => '0',
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DMA_ADDR => (others=>'1'),
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DMA_WRITE_DATA => (others=>'1'),
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MEMORY_READY_DMA => open,
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DMA_FETCH => dma_fetch,
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DMA_READ_ENABLE => dma_read_enable,
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DMA_32BIT_WRITE_ENABLE => dma_32bit_write_enable,
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DMA_16BIT_WRITE_ENABLE => dma_16bit_write_enable,
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DMA_8BIT_WRITE_ENABLE => dma_8bit_write_enable,
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DMA_ADDR => dma_addr_fetch,
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DMA_WRITE_DATA => dma_write_data,
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MEMORY_READY_DMA => dma_memory_ready,
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DMA_MEMORY_DATA => dma_memory_data,
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RAM_SELECT => (others=>'0'),
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RAM_SELECT => ram_select,
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ROM_SELECT => "000001",
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PAL => PAL,
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HALT => '0',
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THROTTLE_COUNT_6502 => THROTTLE_COUNT_6502
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HALT => pause_atari,
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THROTTLE_COUNT_6502 => speed_6502
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);
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process(clk_sdram,sdram_reset_ctrl_n_reg)
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| ... | ... | |
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end if;
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end process;
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process(seq_reg, seq_next, sdram_rdy, sdram_reset_n_reg)
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process(seq_reg, seq_next, sdram_rdy, sdram_reset_n_reg, reset_atari)
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begin
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sdram_reset_n_next <= sdram_reset_n_reg;
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if (sdram_rdy = '1' and seq_next(8)='1' and seq_reg(8)='0') then
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sdram_reset_n_next <= '1';
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end if;
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if (reset_atari = '1') then
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sdram_reset_n_next <= '0';
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end if;
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end process;
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-- Adapt SDRAM
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| ... | ... | |
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if (SDRAM_WIDTH_8BIT_ACCESS = '1') then
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ram_di_next <= (others=>'0');
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else
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ram_di_next <= SDRAM_DI(15 downto 0);
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ram_di_next <= SDRAM_DI(31 downto 16);
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ram_bena_next <= "11";
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end if;
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end if;
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| ... | ... | |
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end generate;
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gen_scandouble_on: if scandouble=1 generate
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process(scandouble_clk,reset_n)
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process(scandouble_clk,sdram_reset_n_reg)
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begin
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if (reset_n='0') then
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if (sdram_reset_n_reg='0') then
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half_scandouble_enable_reg <= '0';
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elsif (scandouble_clk'event and scandouble_clk='1') then
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half_scandouble_enable_reg <= half_scandouble_enable_next;
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| ... | ... | |
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PORT MAP
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(
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CLK => SCANDOUBLE_CLK,
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RESET_N => RESET_N and sdram_rdy,
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RESET_N => sdram_reset_n_reg,
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VGA => '1',
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COMPOSITE_ON_HSYNC => '0', -- TODO
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| ... | ... | |
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end generate;
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zpu: entity work.zpucore
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GENERIC MAP
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(
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platform => 1 -- TODO
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)
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PORT MAP
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(
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-- standard...
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CLK => CLK,
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RESET_N => RESET_N and sdram_rdy,
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-- dma bus master (with many waitstates...)
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ZPU_ADDR_FETCH => dma_addr_fetch,
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ZPU_DATA_OUT => dma_write_data,
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ZPU_FETCH => dma_fetch,
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ZPU_32BIT_WRITE_ENABLE => dma_32bit_write_enable,
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ZPU_16BIT_WRITE_ENABLE => dma_16bit_write_enable,
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ZPU_8BIT_WRITE_ENABLE => dma_8bit_write_enable,
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ZPU_READ_ENABLE => dma_read_enable,
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ZPU_MEMORY_READY => dma_memory_ready,
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ZPU_MEMORY_DATA => dma_memory_data,
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-- rom bus master
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-- data on next cycle after addr
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ZPU_ADDR_ROM => zpu_addr_rom,
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ZPU_ROM_DATA => zpu_rom_data,
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-- spi master
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-- Too painful to bit bang spi from zpu, so we have a hardware master in here
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ZPU_SD_DAT0 => sd_dat0,
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ZPU_SD_CLK => sd_clk,
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ZPU_SD_CMD => sd_cmd,
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ZPU_SD_DAT3 => sd_dat3,
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-- SIO
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-- Ditto for speaking to Atari, we have a built in Pokey
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ZPU_POKEY_ENABLE => zpu_pokey_enable,
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ZPU_SIO_TXD => zpu_sio_txd,
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ZPU_SIO_RXD => zpu_sio_rxd,
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ZPU_SIO_COMMAND => zpu_sio_command,
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-- external control
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-- switches etc. sector DMA blah blah.
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ZPU_IN1 => X"00000000",
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ZPU_IN2 => X"00000000",
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ZPU_IN3 => X"00000000",
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ZPU_IN4 => X"00000000",
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-- ouputs - e.g. Atari system control, halt, throttle, rom select
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ZPU_OUT1 => zpu_out1,
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ZPU_OUT2 => zpu_out2,
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ZPU_OUT3 => zpu_out3,
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ZPU_OUT4 => zpu_out4
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);
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pause_atari <= zpu_out1(0);
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reset_atari <= zpu_out1(1);
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speed_6502 <= zpu_out1(7 downto 2);
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ram_select <= zpu_out1(10 downto 8);
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rom_select <= zpu_out1(16 downto 11);
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zpu_rom1: entity work.zpu_rom
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port map(
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clock => clk,
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address => zpu_addr_rom(13 downto 2),
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q => zpu_rom_data
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);
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enable_179_clock_div_zpu_pokey : entity work.enable_divider
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generic map (COUNT=>16) -- cycle_length
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port map(clk=>clk,reset_n=>reset_n,enable_in=>'1',enable_out=>zpu_pokey_enable);
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END vhdl;
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| mcc216/build.sh | ||
|---|---|---|
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`cp atari800core_mcc.vhd $dir`;
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`cp *pll*.* $dir`;
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`cp sdram_ctrl_3_ports.v $dir`;
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`cp zpu_rom.vhdl $dir`;
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`cp atari800core.sdc $dir`;
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chdir $dir;
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`../makeqsf ../atari800core.qsf ../svideo ../../common/a8core ../../common/components`;
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`../makeqsf ../atari800core.qsf ../svideo ../../common/a8core ../../common/components ../../common/zpu`;
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foreach my $key (sort keys %{$variants{$variant}})
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{
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| mcc216/simulate_full.sh | ||
|---|---|---|
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cp `find ../../common/a8core/ -iname "*.vhdl"` .
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cp `find ../../common/components/ -iname "*.vhd"` .
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cp `find ../../common/components/ -iname "*.vhdl"` .
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cp `find ../../common/zpu/ -iname "*.vhd"` .
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cp `find ../../common/zpu/ -iname "*.vhdl"` .
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cp ../atari800core_mcc.vhd .
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cp ../zpu_rom.vhdl .
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cp ../sdram_ctrl_3_ports.v .
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cp ../*pll*.vhd* .
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cp ../svideo/* .
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| mcc216/zpu_rom.vhdl | ||
|---|---|---|
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--
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--ROMsUsingBlockRAMResources.
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--VHDLcodeforaROMwithregisteredoutput(template2)
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--
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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entity zpu_rom is
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port(
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clock:in std_logic;
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address:in std_logic_vector(11 downto 0);
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q:out std_logic_vector(31 downto 0)
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);
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end zpu_rom;
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architecture syn of zpu_rom is
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type rom_type is array(0 to 4095) of std_logic_vector(31 downto 0);
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signal ROM:rom_type:=
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(
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X"0b0b0b89",
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X"ad040b0b",
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X"0b0b0b0b",
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X"0b0b0b0b",
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X"0b0b0b0b",
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X"0b0b0b0b",
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X"0b0b0b0b",
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X"0b0b0b0b",
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X"0b0b0b0b",
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X"00000000",
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X"00000000",
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X"00000000",
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X"00000000",
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X"00000000",
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X"00000000",
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X"00000000",
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X"71fd0608",
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X"72830609",
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X"81058205",
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X"832b2a83",
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X"ffff0652",
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X"04000000",
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X"00000000",
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X"00000000",
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X"71fd0608",
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X"83ffff73",
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X"83060981",
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X"05820583",
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X"2b2b0906",
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X"7383ffff",
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X"0b0b0b0b",
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X"83a70400",
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X"72098105",
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X"72057373",
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X"09060906",
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X"73097306",
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X"070a8106",
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X"53510400",
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X"00000000",
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X"00000000",
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X"72722473",
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X"732e0753",
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X"51040000",
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X"00000000",
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X"00000000",
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X"00000000",
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X"00000000",
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X"00000000",
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X"71737109",
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X"71068106",
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X"30720a10",
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X"0a720a10",
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||
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X"0a31050a",
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||
|
X"81065151",
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||
|
X"53510400",
|
||
|
X"00000000",
|
||
|
X"72722673",
|
||
|
X"732e0753",
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||
|
X"51040000",
|
||
|
X"00000000",
|
||
|
X"00000000",
|
||
|
X"00000000",
|
||
|
X"00000000",
|
||
|
X"00000000",
|
||
|
X"00000000",
|
||
|
X"00000000",
|
||
|
X"00000000",
|
||
|
X"00000000",
|
||
|
X"00000000",
|
||
|
X"00000000",
|
||
|
X"00000000",
|
||
|
X"00000000",
|
||
|
X"0b0b0b88",
|
||
|
X"bc040000",
|
||
|
X"00000000",
|
||
|
X"00000000",
|
||
|
X"00000000",
|
||
|
X"00000000",
|
||
|
X"00000000",
|
||
|
X"00000000",
|
||
|
X"720a722b",
|
||
|
X"0a535104",
|
||
|
X"00000000",
|
||
|
X"00000000",
|
||
|
X"00000000",
|
||
|
X"00000000",
|
||
|
X"00000000",
|
||
|
X"00000000",
|
||
|
X"72729f06",
|
||
|
X"0981050b",
|
||
|
X"0b0b889f",
|
||
|
X"05040000",
|
||
|
X"00000000",
|
||
|
X"00000000",
|
||
|
X"00000000",
|
||
|
X"00000000",
|
||
|
X"72722aff",
|
||
|
X"739f062a",
|
||
|
X"0974090a",
|
||
|
X"8106ff05",
|
||
|
X"06075351",
|
||
|
X"04000000",
|
||
|
X"00000000",
|
||
|
X"00000000",
|
||
|
X"71715351",
|
||
|
X"020d0406",
|
||
|
X"73830609",
|
||
|
X"81058205",
|
||
|
X"832b0b2b",
|
||
|
X"0772fc06",
|
||
|
X"0c515104",
|
||
|
X"00000000",
|
||
|
X"72098105",
|
||
|
X"72050970",
|
||
|
X"81050906",
|
||
|
X"0a810653",
|
||
|
X"51040000",
|
||
|
X"00000000",
|
||
|
X"00000000",
|
||
|
X"00000000",
|
||
|
X"72098105",
|
||
|
X"72050970",
|
||
|
X"81050906",
|
||
|
X"0a098106",
|
||
|
X"53510400",
|
||
|
X"00000000",
|
||
|
X"00000000",
|
||
|
X"00000000",
|
||
|
X"71098105",
|
||
|
X"52040000",
|
||
|
X"00000000",
|
||
|
X"00000000",
|
||
|
X"00000000",
|
||
|
X"00000000",
|
||
|
X"00000000",
|
||
|
X"00000000",
|
||
|
X"72720981",
|
||
|
X"05055351",
|
||
|
X"04000000",
|
||
|
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Also available in: Unified diff
Added zpu. Fix sdram 32-bit mode.