Revision 448
Added by markw over 9 years ago
| ultimate_cart/veronica/slave_timing_6502.vhd | ||
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signal phi_edge_prev_next : std_logic;
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signal phi_edge_prev_reg: std_logic;
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signal delay_next : std_logic_vector(30 downto 0);
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signal delay_reg : std_logic_vector(30 downto 0);
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signal delay_next : std_logic_vector(60 downto 0);
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signal delay_reg : std_logic_vector(60 downto 0);
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signal bus_data_out_next : std_logic_vector(7 downto 0);
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signal bus_data_out_reg : std_logic_vector(7 downto 0);
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| ... | ... | |
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signal state_reg : std_logic_vector(2 downto 0);
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signal state_next : std_logic_vector(2 downto 0);
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constant state_phi : std_logic_vector(2 downto 0) := "000";
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constant state_write_request : std_logic_vector(2 downto 0) := "001";
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constant state_read_request : std_logic_vector(2 downto 0) := "010";
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constant state_wait_addrctl : std_logic_vector(2 downto 0) := "001";
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constant state_write_request : std_logic_vector(2 downto 0) := "010";
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constant state_read_output_start : std_logic_vector(2 downto 0) := "011";
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constant state_read_output_end : std_logic_vector(2 downto 0) := "100";
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| ... | ... | |
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bus_s5_n_reg <= '1';
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bus_ctl_n_reg <= '1';
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state_reg <= state_phi;
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state_reg <= state_wait_addrctl;
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elsif (clk7x'event and clk7x='1') then
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phi_edge_prev_reg <= phi_edge_prev_next;
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delay_reg <= delay_next;
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| ... | ... | |
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bus_ctl_n_next <= bus_ctl_n_reg;
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internal_memory_request <= '0';
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delay_next <= delay_reg(29 downto 0)&'0';
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delay_next <= delay_reg(59 downto 0)&(not(phi2_sync) and phi_edge_prev_reg);
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bus_data_out_next <= bus_data_out_reg;
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bus_drive_next <= bus_drive_reg;
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| ... | ... | |
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-- XXXXXXXXXXDDDD
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state_next <= state_reg;
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case (state_reg) is
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when state_phi =>
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if (phi2_sync = '1' and phi_edge_prev_reg='0') then -- falling edge (3 cycles delayed)
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delay_next(0) <= '1';
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when state_wait_addrctl =>
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if (delay_reg(17)='1') then -- n+4 cycles
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-- snap control signals, should be stable by now
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bus_addr_in_next <= bus_addr;
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bus_rw_n_next <= bus_rw_n;
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| ... | ... | |
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bus_ctl_n_next <= bus_ctl_n;
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if (bus_rw_n='1') then -- read
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state_next <= state_read_request;
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state_next <= state_read_output_start;
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internal_memory_request <= '1';
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else
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state_next <= state_write_request;
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end if;
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end if;
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when state_write_request =>
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if (delay_reg(19)='1') then -- n+4 cycles
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if (delay_reg(45)='1') then -- n+4 cycles
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bus_data_in_next <= bus_data;
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end if;
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if (delay_reg(20)='1') then -- n+4 cycles
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if (delay_reg(46)='1') then -- n+4 cycles
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internal_memory_request <= '1';
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state_next <= state_phi;
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state_next <= state_wait_addrctl;
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end if;
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when state_read_request =>
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if (delay_reg(0)='1') then -- n+4 cycles
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state_next <= state_read_output_start;
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internal_memory_request <= '1';
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end if;
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when state_read_output_start =>
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if (delay_reg(16)='1') then -- n+4 cycles
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if (delay_reg(38)='1') then -- n+4 cycles
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bus_data_out_next <= data_out;
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bus_drive_next <= '1';
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state_next <= state_read_output_start;
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state_next <= state_read_output_end;
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end if;
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when state_read_output_end =>
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if (delay_reg(30)='1') then -- n+4 cycles
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if (delay_reg(56)='1') then -- n+4 cycles
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bus_drive_next <= '0';
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state_next <= state_phi;
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state_next <= state_wait_addrctl;
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end if;
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when others =>
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end case;
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Also available in: Unified diff
Adjusted delays and verified in sim