Revision 447
Added by markw over 9 years ago
| ultimate_cart/veronica/memory_timing_bridge.vhd | ||
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signal make_request_reg : std_logic;
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begin
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-- register
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process(clk)
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process(clk,reset_n)
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begin
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if (reset_n='0') then
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memory_reg <= (others=>'0');
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| ... | ... | |
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end if;
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end process;
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process(clk7x)
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process(clk7x,reset_n)
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begin
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if (reset_n='0') then
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fast_request_toggle_reg <= '0';
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elsif (clk'event and clk='1') then
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elsif (clk7x'event and clk7x='1') then
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fast_request_toggle_reg <= fast_request_toggle_next;
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end if;
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end process;
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fast_request_toggle_next <= fast_request_toggle_reg xor fast_memory_request;
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slow_request_toggle_next <= fast_request_toggle_reg;
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process(memory_reg,read_data,make_request_reg)
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begin
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| ultimate_cart/veronica/slave_timing_6502.vhd | ||
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s5_n <= bus_s5_n_reg;
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ctl_n <= bus_ctl_n_reg;
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process(data_out, phi2_sync, phi_edge_prev_reg, delay_reg, bus_data_out_reg,
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process(data_out, phi2_sync, phi_edge_prev_reg, delay_reg,
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bus_drive_reg,bus_data_out_reg,
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bus_rw_n_reg,bus_addr_in_reg,bus_data_in_reg,
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bus_s4_n_reg,bus_s5_n_reg,bus_ctl_n_reg,
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bus_rw_n,
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bus_s4_n,bus_s5_n,bus_ctl_n,
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bus_data,bus_addr,
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state_reg)
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begin
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Also available in: Unified diff
Trivial but important fixes, thanks to quartus warnings