repo2/eclaireXL/pll.cmp @ 447
| 382 | markw | component pll is
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port (
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refclk : in std_logic := 'X'; -- clk
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rst : in std_logic := 'X'; -- reset
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outclk_0 : out std_logic; -- clk
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outclk_1 : out std_logic; -- clk
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outclk_2 : out std_logic; -- clk
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| 423 | markw | outclk_3 : out std_logic; -- clk
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| 382 | markw | locked : out std_logic -- export
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);
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end component pll;
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