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-- megafunction wizard: %ALTIOBUF%
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-- GENERATION: STANDARD
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-- VERSION: WM1.0
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-- MODULE: altiobuf_bidir
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-- ============================================================
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-- File Name: altiobuf.vhd
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-- Megafunction Name(s):
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-- altiobuf_bidir
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--
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-- Simulation Library Files(s):
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-- altera_mf
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-- ============================================================
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-- ************************************************************
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-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
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--
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-- 14.0.0 Build 200 06/17/2014 SJ Web Edition
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-- ************************************************************
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--Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
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--Your use of Altera Corporation's design tools, logic functions
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--and other software and tools, and its AMPP partner logic
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--functions, and any output files from any of the foregoing
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--(including device programming or simulation files), and any
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--associated documentation or information are expressly subject
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--to the terms and conditions of the Altera Program License
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--Subscription Agreement, the Altera Quartus II License Agreement,
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--the Altera MegaCore Function License Agreement, or other
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--applicable license agreement, including, without limitation,
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--that your use is for the sole purpose of programming logic
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--devices manufactured by Altera and sold by Altera or its
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--authorized distributors. Please refer to the applicable
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--agreement for further details.
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--altiobuf_bidir CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Cyclone V" ENABLE_BUS_HOLD="FALSE" NUMBER_OF_CHANNELS=4 OPEN_DRAIN_OUTPUT="FALSE" USE_DIFFERENTIAL_MODE="TRUE" USE_DYNAMIC_TERMINATION_CONTROL="FALSE" USE_TERMINATION_CONTROL="FALSE" datain dataio dataio_b dataout oe oe_b
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--VERSION_BEGIN 14.0 cbx_altiobuf_bidir 2014:06:05:09:45:41:SJ cbx_mgl 2014:06:05:10:17:12:SJ cbx_stratixiii 2014:06:05:09:45:41:SJ cbx_stratixv 2014:06:05:09:45:41:SJ VERSION_END
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LIBRARY cyclonev;
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USE cyclonev.all;
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--synthesis_resources = cyclonev_io_ibuf 4 cyclonev_io_obuf 8 cyclonev_pseudo_diff_out 4
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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ENTITY altiobuf_iobuf_bidir_lup IS
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PORT
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(
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datain : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
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dataio : INOUT STD_LOGIC_VECTOR (3 DOWNTO 0);
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dataio_b : INOUT STD_LOGIC_VECTOR (3 DOWNTO 0);
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dataout : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
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oe : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
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oe_b : IN STD_LOGIC_VECTOR (3 DOWNTO 0) := (OTHERS => '1')
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);
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END altiobuf_iobuf_bidir_lup;
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ARCHITECTURE RTL OF altiobuf_iobuf_bidir_lup IS
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SIGNAL wire_ibufa_i : STD_LOGIC_VECTOR (3 DOWNTO 0);
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SIGNAL wire_ibufa_ibar : STD_LOGIC_VECTOR (3 DOWNTO 0);
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SIGNAL wire_ibufa_o : STD_LOGIC_VECTOR (3 DOWNTO 0);
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SIGNAL wire_obuf_ba_o : STD_LOGIC_VECTOR (3 DOWNTO 0);
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SIGNAL wire_obuf_ba_oe : STD_LOGIC_VECTOR (3 DOWNTO 0);
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SIGNAL wire_obufa_o : STD_LOGIC_VECTOR (3 DOWNTO 0);
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SIGNAL wire_obufa_oe : STD_LOGIC_VECTOR (3 DOWNTO 0);
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SIGNAL wire_pseudo_diffa_w_lg_oebout3w : STD_LOGIC_VECTOR (3 DOWNTO 0);
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SIGNAL wire_pseudo_diffa_w_lg_oeout2w : STD_LOGIC_VECTOR (3 DOWNTO 0);
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SIGNAL wire_pseudo_diffa_i : STD_LOGIC_VECTOR (3 DOWNTO 0);
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SIGNAL wire_pseudo_diffa_o : STD_LOGIC_VECTOR (3 DOWNTO 0);
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SIGNAL wire_pseudo_diffa_obar : STD_LOGIC_VECTOR (3 DOWNTO 0);
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SIGNAL wire_pseudo_diffa_oebout : STD_LOGIC_VECTOR (3 DOWNTO 0);
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SIGNAL wire_pseudo_diffa_oein : STD_LOGIC_VECTOR (3 DOWNTO 0);
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SIGNAL wire_pseudo_diffa_oeout : STD_LOGIC_VECTOR (3 DOWNTO 0);
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SIGNAL wire_w_lg_oe1w : STD_LOGIC_VECTOR (3 DOWNTO 0);
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COMPONENT cyclonev_io_ibuf
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GENERIC
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(
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bus_hold : STRING := "false";
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differential_mode : STRING := "false";
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simulate_z_as : STRING := "z";
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lpm_type : STRING := "cyclonev_io_ibuf"
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);
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PORT
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(
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dynamicterminationcontrol : IN STD_LOGIC := '0';
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i : IN STD_LOGIC := '0';
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ibar : IN STD_LOGIC := '0';
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o : OUT STD_LOGIC
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);
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END COMPONENT;
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COMPONENT cyclonev_io_obuf
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GENERIC
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(
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bus_hold : STRING := "false";
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open_drain_output : STRING := "false";
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shift_series_termination_control : STRING := "false";
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lpm_type : STRING := "cyclonev_io_obuf"
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);
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PORT
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(
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dynamicterminationcontrol : IN STD_LOGIC := '0';
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i : IN STD_LOGIC := '0';
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o : OUT STD_LOGIC;
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obar : OUT STD_LOGIC;
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oe : IN STD_LOGIC := '1';
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parallelterminationcontrol : IN STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0');
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seriesterminationcontrol : IN STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0')
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);
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END COMPONENT;
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COMPONENT cyclonev_pseudo_diff_out
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PORT
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(
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dtc : OUT STD_LOGIC;
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dtcbar : OUT STD_LOGIC;
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dtcin : IN STD_LOGIC := '0';
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i : IN STD_LOGIC := '0';
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o : OUT STD_LOGIC;
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obar : OUT STD_LOGIC;
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oebout : OUT STD_LOGIC;
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oein : IN STD_LOGIC := '0';
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oeout : OUT STD_LOGIC
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);
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END COMPONENT;
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BEGIN
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loop0 : FOR i IN 0 TO 3 GENERATE
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wire_w_lg_oe1w(i) <= NOT oe(i);
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END GENERATE loop0;
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dataio <= wire_obufa_o;
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dataio_b <= wire_obuf_ba_o;
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dataout <= wire_ibufa_o;
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wire_ibufa_i <= dataio;
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wire_ibufa_ibar <= dataio_b;
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loop1 : FOR i IN 0 TO 3 GENERATE
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ibufa : cyclonev_io_ibuf
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GENERIC MAP (
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bus_hold => "false",
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differential_mode => "true"
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)
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PORT MAP (
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i => wire_ibufa_i(i),
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ibar => wire_ibufa_ibar(i),
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o => wire_ibufa_o(i)
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);
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END GENERATE loop1;
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wire_obuf_ba_oe <= wire_pseudo_diffa_w_lg_oebout3w;
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loop2 : FOR i IN 0 TO 3 GENERATE
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obuf_ba : cyclonev_io_obuf
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GENERIC MAP (
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bus_hold => "false",
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open_drain_output => "false"
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)
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PORT MAP (
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i => wire_pseudo_diffa_obar(i),
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o => wire_obuf_ba_o(i),
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oe => wire_obuf_ba_oe(i)
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);
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END GENERATE loop2;
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wire_obufa_oe <= wire_pseudo_diffa_w_lg_oeout2w;
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loop3 : FOR i IN 0 TO 3 GENERATE
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obufa : cyclonev_io_obuf
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GENERIC MAP (
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bus_hold => "false",
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open_drain_output => "false"
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)
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PORT MAP (
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i => wire_pseudo_diffa_o(i),
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o => wire_obufa_o(i),
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oe => wire_obufa_oe(i)
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);
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END GENERATE loop3;
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loop4 : FOR i IN 0 TO 3 GENERATE
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wire_pseudo_diffa_w_lg_oebout3w(i) <= NOT wire_pseudo_diffa_oebout(i);
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END GENERATE loop4;
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loop5 : FOR i IN 0 TO 3 GENERATE
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wire_pseudo_diffa_w_lg_oeout2w(i) <= NOT wire_pseudo_diffa_oeout(i);
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END GENERATE loop5;
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wire_pseudo_diffa_i <= datain;
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wire_pseudo_diffa_oein <= wire_w_lg_oe1w;
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loop6 : FOR i IN 0 TO 3 GENERATE
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pseudo_diffa : cyclonev_pseudo_diff_out
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PORT MAP (
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i => wire_pseudo_diffa_i(i),
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o => wire_pseudo_diffa_o(i),
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obar => wire_pseudo_diffa_obar(i),
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oebout => wire_pseudo_diffa_oebout(i),
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oein => wire_pseudo_diffa_oein(i),
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oeout => wire_pseudo_diffa_oeout(i)
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);
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END GENERATE loop6;
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END RTL; --altiobuf_iobuf_bidir_lup
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--VALID FILE
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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ENTITY altiobuf IS
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PORT
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(
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datain : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
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oe : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
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oe_b : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
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dataio : INOUT STD_LOGIC_VECTOR (3 DOWNTO 0);
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dataio_b : INOUT STD_LOGIC_VECTOR (3 DOWNTO 0);
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dataout : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
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);
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END altiobuf;
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ARCHITECTURE RTL OF altiobuf IS
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SIGNAL sub_wire0 : STD_LOGIC_VECTOR (3 DOWNTO 0);
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COMPONENT altiobuf_iobuf_bidir_lup
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PORT (
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datain : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
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oe : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
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oe_b : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
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dataout : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
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dataio : INOUT STD_LOGIC_VECTOR (3 DOWNTO 0);
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dataio_b : INOUT STD_LOGIC_VECTOR (3 DOWNTO 0)
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);
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END COMPONENT;
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BEGIN
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dataout <= sub_wire0(3 DOWNTO 0);
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altiobuf_iobuf_bidir_lup_component : altiobuf_iobuf_bidir_lup
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PORT MAP (
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datain => datain,
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oe => oe,
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oe_b => oe_b,
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dataout => sub_wire0,
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dataio => dataio,
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dataio_b => dataio_b
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);
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END RTL;
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-- ============================================================
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-- CNX file retrieval info
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-- ============================================================
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-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
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-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
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-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
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-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
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-- Retrieval info: CONSTANT: enable_bus_hold STRING "FALSE"
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-- Retrieval info: CONSTANT: left_shift_series_termination_control STRING "FALSE"
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-- Retrieval info: CONSTANT: number_of_channels NUMERIC "4"
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-- Retrieval info: CONSTANT: open_drain_output STRING "FALSE"
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-- Retrieval info: CONSTANT: use_differential_mode STRING "TRUE"
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-- Retrieval info: CONSTANT: use_dynamic_termination_control STRING "FALSE"
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-- Retrieval info: CONSTANT: use_termination_control STRING "FALSE"
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-- Retrieval info: USED_PORT: datain 0 0 4 0 INPUT NODEFVAL "datain[3..0]"
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-- Retrieval info: USED_PORT: dataio 0 0 4 0 BIDIR NODEFVAL "dataio[3..0]"
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-- Retrieval info: USED_PORT: dataio_b 0 0 4 0 BIDIR NODEFVAL "dataio_b[3..0]"
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-- Retrieval info: USED_PORT: dataout 0 0 4 0 OUTPUT NODEFVAL "dataout[3..0]"
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-- Retrieval info: USED_PORT: oe 0 0 4 0 INPUT NODEFVAL "oe[3..0]"
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-- Retrieval info: USED_PORT: oe_b 0 0 4 0 INPUT NODEFVAL "oe_b[3..0]"
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-- Retrieval info: CONNECT: @datain 0 0 4 0 datain 0 0 4 0
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-- Retrieval info: CONNECT: @oe 0 0 4 0 oe 0 0 4 0
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-- Retrieval info: CONNECT: @oe_b 0 0 4 0 oe_b 0 0 4 0
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-- Retrieval info: CONNECT: dataio 0 0 4 0 @dataio 0 0 4 0
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-- Retrieval info: CONNECT: dataio_b 0 0 4 0 @dataio_b 0 0 4 0
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-- Retrieval info: CONNECT: dataout 0 0 4 0 @dataout 0 0 4 0
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-- Retrieval info: GEN_FILE: TYPE_NORMAL altiobuf.vhd TRUE
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-- Retrieval info: GEN_FILE: TYPE_NORMAL altiobuf.inc FALSE
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-- Retrieval info: GEN_FILE: TYPE_NORMAL altiobuf.cmp TRUE
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-- Retrieval info: GEN_FILE: TYPE_NORMAL altiobuf.bsf FALSE
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-- Retrieval info: GEN_FILE: TYPE_NORMAL altiobuf_inst.vhd FALSE
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-- Retrieval info: LIB_FILE: altera_mf
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