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//
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// sd_card.v
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//
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// This file implelents a sd card for the MIST board since on the board
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// the SD card is connected to the ARM IO controller and the FPGA has no
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// direct connection to the SD card. This file provides a SD card like
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// interface to the IO controller easing porting of cores that expect
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// a direct interface to the SD card.
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//
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// Copyright (c) 2014 Till Harbaum <till@harbaum.org>
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//
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// This source file is free software: you can redistribute it and/or modify
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// it under the terms of the Lesser GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This source file is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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// http://elm-chan.org/docs/mmc/mmc_e.html
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// TODO:
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// - CMD9: SEND_CSD (requires device capacity)
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// - CMD10: SEND_CID
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module sd_card (
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// link to user_io for io controller
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output [31:0] io_lba,
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output reg io_rd,
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output reg io_wr,
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input io_ack,
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output io_conf,
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output io_sdhc,
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// data coming in from io controller
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input [7:0] io_din,
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input io_din_strobe,
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// data going out to io controller
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output [7:0] io_dout,
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input io_dout_strobe,
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// configuration input
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input allow_sdhc,
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input sd_cs,
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input sd_sck,
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input sd_sdi,
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output reg sd_sdo
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);
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// set io_rd once read_state machine starts waiting (rising edge of req_io_rd)
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// and clear it once io controller uploads something (io_ack==1)
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// wire req_io_rd = (read_state == RD_STATE_WAIT_IO);
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wire req_io_rd = (read_state != RD_STATE_IDLE);
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always @(posedge req_io_rd or posedge io_ack) begin
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if(io_ack) io_rd <= 1'b0;
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else io_rd <= 1'b1;
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end
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wire req_io_wr = (write_state == WR_STATE_BUSY);
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always @(posedge req_io_wr or posedge io_ack) begin
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if(io_ack) io_wr <= 1'b0;
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else io_wr <= 1'b1;
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end
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wire [31:0] OCR = { 1'b0, io_sdhc, 30'h0 }; // bit30 = 1 -> high capaciry card (sdhc)
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wire [7:0] READ_DATA_TOKEN = 8'hfe;
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localparam NCR=4;
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// 0=idle, 1=wait for io ctrl, 2=wait for byte start, 3=send token, 4=send data, 5/6=send crc[0..1]
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localparam RD_STATE_IDLE = 3'd0;
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localparam RD_STATE_WAIT_IO = 3'd1;
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localparam RD_STATE_SEND_TOKEN = 3'd2;
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localparam RD_STATE_SEND_DATA = 3'd3;
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localparam RD_STATE_SEND_CRC0 = 3'd4;
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localparam RD_STATE_SEND_CRC1 = 3'd5;
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reg [2:0] read_state = RD_STATE_IDLE;
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// 0=idle
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localparam WR_STATE_IDLE = 3'd0;
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localparam WR_STATE_EXP_DTOKEN = 3'd1;
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localparam WR_STATE_RECV_DATA = 3'd2;
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localparam WR_STATE_RECV_CRC0 = 3'd3;
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localparam WR_STATE_RECV_CRC1 = 3'd4;
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localparam WR_STATE_SEND_DRESP = 3'd5;
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localparam WR_STATE_BUSY = 3'd6;
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reg [2:0] write_state = WR_STATE_IDLE;
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reg [6:0] sbuf;
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reg cmd55;
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reg new_cmd_rcvd;
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reg [7:0] cmd;
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reg [2:0] bit_cnt; // counts bits 0-7 0-7 ...
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reg [3:0] byte_cnt= 4'd15; // counts bytes
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reg [31:0] lba;
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assign io_lba = io_sdhc?lba:{9'd0, lba[31:9]};
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//assign io_lba = io_sdhc?{read_state, lba[31:3]}:{9'd0, lba[31:9]};
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// the command crc is actually never evaluated
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reg [7:0] crc;
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reg [7:0] reply;
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reg [7:0] reply0, reply1, reply2, reply3;
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reg [3:0] reply_len;
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// signals to address buffer on SD card write (data coming from SD spi)
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reg write_strobe;
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reg [7:0] write_data;
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// falling edge of io_ack signals that a sector to be read has been written into
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// the sector bufffer by the io controller. This signal is kept set as long
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// as the read state machine is in the "wait for io controller" state (state 1)
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// wire rd_wait_io = (read_state == RD_STATE_WAIT_IO);
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wire rd_wait_io = (read_state != RD_STATE_IDLE);
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reg rd_io_ack = 1'b0 /* synthesis noprune */;
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always @(negedge io_ack or negedge rd_wait_io) begin
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if(!rd_wait_io) rd_io_ack <= 1'b0;
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else rd_io_ack <= 1'b1;
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end
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wire wr_wait_io = (write_state == WR_STATE_BUSY);
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reg wr_io_ack = 1'b0 /* synthesis noprune */;
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always @(negedge io_ack or negedge wr_wait_io) begin
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if(!wr_wait_io) wr_io_ack <= 1'b0;
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else wr_io_ack <= 1'b1;
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end
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// ------------------------- SECTOR BUFFER -----------------------
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// access to the sector buffer is multiplexed. When reading sectors
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// the io controller writes into the buffer and the sd card implementation
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// reads. And vice versa when writing sectors
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wire reading = (read_state != RD_STATE_IDLE);
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wire writing = (write_state != WR_STATE_IDLE);
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// the buffer itself. Can hold one sector
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reg [8:0] buffer_wptr;
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reg [8:0] buffer_rptr;
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reg [7:0] buffer [511:0];
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reg [7:0] buffer_byte;
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// ---------------- buffer read engine -----------------------
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reg core_buffer_read_strobe;
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wire buffer_read_latch = reading?sd_sck:io_dout_strobe;
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wire buffer_read_strobe = reading?core_buffer_read_strobe:!io_dout_strobe;
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assign io_dout = buffer_byte;
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// sdo is sampled on negative sd clock so set it on positive edge
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always @(posedge buffer_read_latch)
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buffer_byte <= buffer[buffer_rptr];
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always @(posedge buffer_read_strobe or posedge new_cmd_rcvd) begin
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if(new_cmd_rcvd == 1) buffer_rptr <= 9'd0;
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else buffer_rptr <= buffer_rptr + 9'd1;
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end
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// ---------------- buffer write engine -----------------------
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wire [7:0] buffer_din = reading?io_din:write_data;
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wire buffer_din_strobe = reading?io_din_strobe:write_strobe;
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always @(negedge buffer_din_strobe or posedge new_cmd_rcvd) begin
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if(new_cmd_rcvd == 1) begin
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buffer_wptr <= 9'd0;
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end else begin
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buffer[buffer_wptr] <= buffer_din;
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buffer_wptr <= buffer_wptr + 9'd1;
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end
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end
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wire [7:0] WRITE_DATA_RESPONSE = 8'h05;
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// ------------------------- CSD/CID BUFFER ----------------------
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assign io_conf = (csd_wptr == 0); // csd_wptr still 0 -> configuration required
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// the 32 bytes as sent from the io controller
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reg [7:0] cid [15:0];
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reg [7:0] csd [15:0];
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reg [7:0] conf;
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reg [7:0] cid_byte;
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reg [7:0] csd_byte;
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reg [5:0] csd_wptr = 6'd0;
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// conf[0]==1 -> io controller is using an sdhc card
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wire io_has_sdhc = conf[0];
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assign io_sdhc = allow_sdhc && io_has_sdhc;
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always @(negedge io_din_strobe) begin
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// if io controller sends data without asserting io_ack, then it's
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// updating the config
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if(!io_ack && (csd_wptr <= 32)) begin
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if(csd_wptr < 16) // first 16 bytes are cid
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cid[csd_wptr] <= io_din;
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if((csd_wptr >= 16) && (csd_wptr < 32)) // then comes csd
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csd[csd_wptr-16] <= io_din;
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if(csd_wptr == 32) // finally a config byte
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conf <= io_din;
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csd_wptr <= csd_wptr + 1;
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end
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end
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always @(posedge buffer_read_latch)
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cid_byte <= cid[buffer_rptr];
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always @(posedge buffer_read_latch)
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csd_byte <= csd[buffer_rptr];
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// ----------------- spi transmitter --------------------
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reg rd_io_ackD, wr_io_ackD;
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reg illegal_state /* synthesis noprune */;
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always@(negedge sd_sck) begin
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if(sd_cs == 0) begin
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illegal_state <= 1'b0;
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core_buffer_read_strobe <= 1'b0;
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// using rd_io_ack directly brings the read state machine into an
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// non-existing state every now and then. For unknown reason
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rd_io_ackD <= rd_io_ack;
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// wait for end of command plus NCR before replying
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if(byte_cnt < 5+NCR) begin
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sd_sdo <= 1'b1; // reply $ff -> wait
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end else if(byte_cnt == 5+NCR) begin
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sd_sdo <= reply[~bit_cnt];
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if(bit_cnt == 7) begin
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// these three commands all have a reply_len of 0 and will thus
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// not send more than a single reply byte
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// CMD9: SEND_CSD
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// CMD10: SEND_CID
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if((cmd == 8'h49)||(cmd == 8'h4a))
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read_state <= RD_STATE_SEND_TOKEN; // jump directly to data transmission
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// CMD17: READ_SINGLE_BLOCK
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if(cmd == 8'h51)
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read_state <= RD_STATE_WAIT_IO; // start waiting for data from io controller
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end
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end
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else if((reply_len > 0) && (byte_cnt == 5+NCR+1))
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sd_sdo <= reply0[~bit_cnt];
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else if((reply_len > 1) && (byte_cnt == 5+NCR+2))
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sd_sdo <= reply1[~bit_cnt];
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else if((reply_len > 2) && (byte_cnt == 5+NCR+3))
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sd_sdo <= reply2[~bit_cnt];
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else if((reply_len > 3) && (byte_cnt == 5+NCR+4))
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sd_sdo <= reply3[~bit_cnt];
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else
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sd_sdo <= 1'b1;
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// ---------- read state machine processing -------------
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case(read_state)
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RD_STATE_IDLE: ;
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// don't do anything
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// waiting for io controller to return data
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RD_STATE_WAIT_IO: begin
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if(rd_io_ack && (bit_cnt == 7))
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read_state <= RD_STATE_SEND_TOKEN;
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end
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// send data token
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RD_STATE_SEND_TOKEN: begin
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sd_sdo <= READ_DATA_TOKEN[~bit_cnt];
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if(bit_cnt == 7)
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read_state <= RD_STATE_SEND_DATA; // next: send data
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end
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// send data
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RD_STATE_SEND_DATA: begin
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if(cmd == 8'h51) // CMD17: READ_SINGLE_BLOCK
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sd_sdo <= buffer_byte[~bit_cnt];
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else if(cmd == 8'h49) // CMD9: SEND_CSD
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sd_sdo <= csd_byte[~bit_cnt];
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else if(cmd == 8'h4a) // CMD10: SEND_CID
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sd_sdo <= cid_byte[~bit_cnt];
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else
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sd_sdo <= 1'b1;
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if(bit_cnt == 7) begin
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core_buffer_read_strobe <= 1'b1;
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// send 512 sector data bytes?
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if((cmd == 8'h51) && (buffer_rptr == 511))
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read_state <= RD_STATE_SEND_CRC0; // next: send crc
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// send 16 cid/csd data bytes?
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if(((cmd == 8'h49)||(cmd == 8'h4a)) && (buffer_rptr == 15))
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read_state <= RD_STATE_IDLE; // return to idle state
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end
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end
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// send crc[0]
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RD_STATE_SEND_CRC0: begin
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sd_sdo <= 1'b1;
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if(bit_cnt == 7)
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read_state <= RD_STATE_SEND_CRC1; // send second crc byte
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end
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// send crc[1]
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RD_STATE_SEND_CRC1: begin
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sd_sdo <= 1'b1;
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if(bit_cnt == 7)
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read_state <= RD_STATE_IDLE; // return to idle state
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end
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default:
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illegal_state <= 1'b1;
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// read_state <= RD_STATE_IDLE;
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endcase
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// ------------------ write support ----------------------
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// send write data response
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if(write_state == WR_STATE_SEND_DRESP)
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sd_sdo <= WRITE_DATA_RESPONSE[~bit_cnt];
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// busy after write until the io controller sends ack
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if(write_state == WR_STATE_BUSY)
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sd_sdo <= 1'b0;
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end
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end
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// spi receiver
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always @(posedge sd_sck or posedge sd_cs) begin
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// cs is active low
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if(sd_cs == 1) begin
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bit_cnt <= 3'd0;
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// byte_cnt <= 4'd15;
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// write_state <= WR_STATE_IDLE;
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// write_strobe <= 1'b0;
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end else begin
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new_cmd_rcvd <= 1'b0;
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write_strobe <= 1'b0;
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sbuf[6:0] <= { sbuf[5:0], sd_sdi };
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bit_cnt <= bit_cnt + 3'd1;
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// using wr_io_ack directly brings the write state machine into an
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// non-existing state every now and then. For unknown reason
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wr_io_ackD <= wr_io_ack;
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// finished reading command byte
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if(bit_cnt == 7) begin
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// byte counter runs against 15 byte boundary
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if(byte_cnt != 15)
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byte_cnt <= byte_cnt + 8'd1;
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// byte_cnt > 6 -> complete command received
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// first byte of valid command is 01xxxxxx
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if((byte_cnt > 5) && (write_state == WR_STATE_IDLE) && sbuf[6:5] == 2'b01)
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byte_cnt <= 4'd0;
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// don't accept new commands once a write command has been accepted
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if((write_state == WR_STATE_IDLE) && (byte_cnt > 5)&&(sbuf[6:5] == 2'b01)) begin
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cmd <= { sbuf, sd_sdi};
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new_cmd_rcvd <= 1'b1;
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// set cmd55 flag if previous command was 55
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cmd55 <= (cmd == 8'h77);
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end
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// parse additional command bytes
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if(byte_cnt == 0) lba[31:24] <= { sbuf, sd_sdi};
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if(byte_cnt == 1) lba[23:16] <= { sbuf, sd_sdi};
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if(byte_cnt == 2) lba[15:8] <= { sbuf, sd_sdi};
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if(byte_cnt == 3) lba[7:0] <= { sbuf, sd_sdi};
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// last byte received, evaluate
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if(byte_cnt == 4) begin
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// crc is currently unused
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crc <= { sbuf, sd_sdi};
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// default:
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reply <= 8'h04; // illegal command
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reply_len <= 4'd0; // no extra reply bytes
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// CMD0: GO_IDLE_STATE
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if(cmd == 8'h40)
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reply <= 8'h01; // ok, busy
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// CMD1: SEND_OP_COND
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else if(cmd == 8'h41)
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reply <= 8'h00; // ok, not busy
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// CMD8: SEND_IF_COND (V2 only)
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else if(cmd == 8'h48) begin
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reply <= 8'h01; // ok, busy
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reply0 <= 8'h00;
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reply1 <= 8'h00;
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reply2 <= 8'h01;
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reply3 <= 8'hAA;
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reply_len <= 4'd4;
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end
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// CMD9: SEND_CSD
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else if(cmd == 8'h49)
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reply <= 8'h00; // ok
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// CMD10: SEND_CID
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else if(cmd == 8'h4a)
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reply <= 8'h00; // ok
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// CMD16: SET_BLOCKLEN
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else if(cmd == 8'h50) begin
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// we only support a block size of 512
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if(io_lba == 32'd512)
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reply <= 8'h00; // ok
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else
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reply <= 8'h40; // parmeter error
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end
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// CMD17: READ_SINGLE_BLOCK
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else if(cmd == 8'h51)
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reply <= 8'h00; // ok
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// CMD24: WRITE_BLOCK
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else if(cmd == 8'h58) begin
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reply <= 8'h00; // ok
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write_state <= WR_STATE_EXP_DTOKEN; // expect data token
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end
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// ACMD41: APP_SEND_OP_COND
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else if(cmd55 && (cmd == 8'h69))
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reply <= 8'h00; // ok, not busy
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// CMD55: APP_COND
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else if(cmd == 8'h77)
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reply <= 8'h01; // ok, busy
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// CMD58: READ_OCR
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else if(cmd == 8'h7a) begin
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reply <= 8'h00; // ok
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reply0 <= OCR[31:24]; // bit 30 = 1 -> high capacity card
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reply1 <= OCR[23:16];
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reply2 <= OCR[15:8];
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reply3 <= OCR[7:0];
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reply_len <= 4'd4;
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end
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end
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// ---------- handle write -----------
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// waiting for data token
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if(write_state == WR_STATE_EXP_DTOKEN) begin
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if({ sbuf, sd_sdi} == 8'hfe )
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write_state <= WR_STATE_RECV_DATA;
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end
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// transfer 512 bytes
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if(write_state == WR_STATE_RECV_DATA) begin
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// push one byte into local buffer
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write_strobe <= 1'b1;
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write_data <= { sbuf, sd_sdi};
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if(buffer_wptr == 511)
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write_state <= WR_STATE_RECV_CRC0;
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end
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// transfer 1st crc byte
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if(write_state == WR_STATE_RECV_CRC0)
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write_state <= WR_STATE_RECV_CRC1;
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// transfer 2nd crc byte
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if(write_state == WR_STATE_RECV_CRC1)
|
|
write_state <= WR_STATE_SEND_DRESP;
|
|
|
|
// send data response
|
|
if(write_state == WR_STATE_SEND_DRESP)
|
|
write_state <= WR_STATE_BUSY;
|
|
end
|
|
|
|
// wait for io controller to accept data
|
|
// this happens outside the bit_cnt == 7 test as the
|
|
// transition may happen at any time
|
|
if(write_state == WR_STATE_BUSY && wr_io_ackD)
|
|
write_state <= WR_STATE_IDLE;
|
|
end
|
|
end
|
|
|
|
endmodule
|