repo2/ultimate_cart/veronica/load_tsk.v @ 446
| 438 | markw | // ============================================================================
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// __
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// \\__/ o\ (C) 2013,2014 Robert Finch, Stratford
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// \ __ / All rights reserved.
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// \/_// robfinch<remove>@opencores.org
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// ||
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//
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// This source file is free software: you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This source file is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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// ============================================================================
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//
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//task load_tsk;
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//input [7:0] db;
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begin
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case(load_what)
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`BYTE_70:
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begin
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b8 <= db;
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state <= BYTE_CALC;
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end
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`BYTE_71:
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begin
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moveto_ifetch();
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res8 <= db;
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end
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`HALF_70:
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begin
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b16[7:0] <= db;
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load_what <= `HALF_158;
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radr <= radr+24'd1;
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state <= LOAD_MAC1;
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end
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`HALF_158:
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begin
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b16[15:8] <= db;
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if (isTribyte) begin
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radr <= radr+24'd1;
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load_what <= `TRIP_2316;
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next_state(LOAD_MAC1);
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end
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else
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state <= HALF_CALC;
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end
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`TRIP_2316: begin
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b24 <= db;
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next_state(HALF_CALC);
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end
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`HALF_71:
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begin
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res16[7:0] <= db;
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load_what <= `HALF_159;
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radr <= radr+32'd1;
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next_state(LOAD_MAC1);
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end
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`HALF_159:
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begin
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res16[15:8] <= db;
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moveto_ifetch();
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end
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`HALF_71S:
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begin
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res16[7:0] <= db;
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load_what <= `HALF_159S;
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inc_sp();
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next_state(LOAD_MAC1);
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end
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`HALF_159S:
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begin
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res16[15:8] <= db;
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moveto_ifetch();
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end
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`BYTE_72:
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begin
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wdat[7:0] <= db;
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radr <= mvndst_address;
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wadr <= mvndst_address;
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store_what <= `STW_DEF8;
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acc[15:0] <= acc_dec[15:0];
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if (ir9==`MVN) begin
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x[15:0] <= x_inc[15:0];
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y[15:0] <= y_inc[15:0];
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end
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else begin
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x[15:0] <= x_dec[15:0];
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y[15:0] <= y_dec[15:0];
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end
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next_state(STORE1);
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end
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`SR_70: begin
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cf <= db[0];
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zf <= db[1];
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if (db[2])
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im <= 1'b1;
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else
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imcd <= 3'b110;
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df <= db[3];
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if (m816) begin
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x_bit <= db[4];
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m_bit <= db[5];
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if (db[4]) begin
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x[15:8] <= 8'd0;
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y[15:8] <= 8'd0;
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end
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//if (db[5]) acc[31:8] <= 24'd0;
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end
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// The following load of the break flag is different than the '02
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// which never loads the flag.
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else
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bf <= db[4];
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vf <= db[6];
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nf <= db[7];
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if (isRTI) begin
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load_what <= `PC_70;
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inc_sp();
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state <= LOAD_MAC1;
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end
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else begin // PLP
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moveto_ifetch();
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end
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end
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`PC_70: begin
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pc[7:0] <= db;
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load_what <= `PC_158;
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if (isRTI|isRTS|isRTL) begin
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inc_sp();
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end
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else begin // JMP (abs)
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radr <= radr + 24'd1;
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end
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state <= LOAD_MAC1;
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end
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`PC_158: begin
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pc[15:8] <= db;
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if ((isRTI&m816)|isRTL) begin
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load_what <= `PC_2316;
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inc_sp();
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state <= LOAD_MAC1;
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end
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else if (isRTS) // rts instruction
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next_state(RTS1);
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else // jmp (abs)
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begin
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vpb <= `FALSE;
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next_state(IFETCH0);
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end
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end
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`PC_2316: begin
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pc[23:16] <= db;
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if (isRTL) begin
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load_what <= `NOTHING;
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next_state(RTS1);
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end
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else begin
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load_what <= `NOTHING;
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next_state(IFETCH0);
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// load_what <= `PC_3124;
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// if (isRTI) begin
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// inc_sp();
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// end
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// state <= LOAD_MAC1;
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end
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end
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// `PC_3124: begin
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// pc[31:24] <= db;
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// load_what <= `NOTHING;
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// next_state(BYTE_IFETCH);
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// end
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`IA_70:
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begin
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radr <= radr + 24'd1;
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ia[7:0] <= db;
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load_what <= `IA_158;
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state <= LOAD_MAC1;
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end
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`IA_158:
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begin
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ia[15:8] <= db;
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ia[23:16] <= dbr;
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if (isIY24|isI24) begin
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radr <= radr + 24'd1;
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load_what <= `IA_2316;
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state <= LOAD_MAC1;
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end
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else
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state <= isIY ? BYTE_IY5 : BYTE_IX5;
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end
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`IA_2316:
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begin
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ia[23:16] <= db;
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state <= isIY24 ? BYTE_IY5 : BYTE_IX5;
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end
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endcase
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end
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//endtask
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