repo2/ultimate_cart/veronica/FT816Sys2.v @ 446
| 438 | markw | `timescale 1ns / 1ps
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// ============================================================================
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// __
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// \\__/ o\ (C) 2014 Robert Finch, Stratford
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// \ __ / All rights reserved.
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// \/_// robfinch<remove>@finitron.ca
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// ||
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//
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// FT816Sys2.v
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// - Top Module for 16 bit CPU
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//
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// This source file is free software: you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This source file is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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// ============================================================================
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//
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`define TRUE 1'b1
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`define FALSE 1'b0
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module FT816Sys2(btn, xclk, Led, sw, kclk, kd,
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HDMIOUTCLKP, HDMIOUTCLKN,
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HDMIOUTD0P,HDMIOUTD0N,
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HDMIOUTD1P,HDMIOUTD1N,
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HDMIOUTD2P,HDMIOUTD2N,
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HDMIOUTSCL,HDMIOUTSDA
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);
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input [5:0] btn;
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input xclk;
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output [7:0] Led;
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reg [7:0] Led;
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input [7:0] sw;
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inout kclk;
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tri kclk;
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inout kd;
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tri kd;
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output HDMIOUTCLKP;
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output HDMIOUTCLKN;
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output HDMIOUTD0P;
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output HDMIOUTD0N;
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output HDMIOUTD1P;
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output HDMIOUTD1N;
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output HDMIOUTD2P;
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output HDMIOUTD2N;
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inout HDMIOUTSCL;
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inout HDMIOUTSDA;
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tri HDMIOUTSCL;
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tri HDMIOUTSDA;
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wire xreset = ~btn[0];
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wire irq = btn[1];
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reg [32:0] rommem [4095:0];
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reg [7:0] rammem [16383:0];
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wire rw;
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wire vda;
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wire [23:0] ad;
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tri [7:0] db;
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wire cs0,cs1,cs4,cs6;
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wire rst;
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wire vclk,vclk2,vclk10;
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wire hsync,vsync,blank,border;
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wire [24:0] tc_rgb;
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wire [3:0] TMDS;
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wire [3:0] TMDSB;
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assign HDMIOUTCLKP = TMDS[3];
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assign HDMIOUTCLKN = TMDSB[3];
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assign HDMIOUTD0P = TMDS[0];
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assign HDMIOUTD0N = TMDSB[0];
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assign HDMIOUTD1P = TMDS[1];
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assign HDMIOUTD1N = TMDSB[1];
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assign HDMIOUTD2P = TMDS[2];
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assign HDMIOUTD2N = TMDSB[2];
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//assign HDMIOUTSCL = 1'b0;
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//assign HDMIOUTSDA = 1'b0;
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initial begin
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`include "..\..\software\asm\FTBios816.ver"
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end
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wire locked;
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wire clk200u,clk85u,clk,sys_clk;
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clkgen1366x768 u2
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(
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.xreset(xreset),
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.xclk(xclk),
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.rst(rst),
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.clk100(),
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.clk25(),
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.clk200(),
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.clk125(), // ETHERMAC clock
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.vclk(vclk), // 85.7MHz
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.vclk2(vclk2),
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.vclk10(vclk10),
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.bmp_clk(),
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.sys_clk(sys_clk),
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.dram_clk(),
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.locked(locked),
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.pulse1000Hz(),
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.pulse100Hz()
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);
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assign clk = sys_clk;
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dvi_out_native u3
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(
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.reset(rst),
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.pll_lckd(locked),
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.clkin(vclk), // pixel clock, from bufg
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.clkx2in(vclk2), // pixel clock x2, from bufg
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.clkx10in(vclk10), // pixel clock x10, unbuffered
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.blue_din(tc_rgb[7:0]), // Blue data in
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.green_din(tc_rgb[15:8]), // Green data in
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.red_din(tc_rgb[23:16]), // Red data in
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.hsync(hsync), // hsync data
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.vsync(vsync), // vsync data
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.de(!blank), // data enable
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.TMDS(TMDS),
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.TMDSB(TMDSB)
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);
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//VGASyncGen640x480_60Hz u4
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WXGASyncGen1366x768_60Hz u4
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(
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.rst(rst),
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.clk(vclk),
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.hSync(hsync),
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.vSync(vsync),
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.blank(blank),
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.border(border)
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);
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wire tc_rdy;
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rtfTextController816 tc1
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(
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.rst(rst),
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.clk(clk),
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.rdy(tc_rdy),
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.rw(rw),
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.vda(vda),
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.ad(ad),
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.db(db),
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.vclk(vclk),
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.hsync(hsync),
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.vsync(vsync),
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.blank(blank),
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.border(border),
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.rgbIn(25'h0),
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.rgbOut(tc_rgb)
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);
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wire kbd_rst;
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wire kbd_rdy;
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PS2KbdToAscii #(.pIOAddress(32'h00FEA110)) u_kbd
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(
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.rst_i(rst),
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.clk_i(clk),
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.cyc_i(vda),
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.stb_i(vda),
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.ack_o(kbd_rdy),
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.we_i(~rw),
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.adr_i({8'h00,ad}),
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.dat_i(db),
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.dat_o(),
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.db(db),
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.kclk(kclk),
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.kd(kd),
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.irq(),
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.rst_o(kbd_rst)
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);
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PRNG u_prng
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(
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.rst(rst),
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.clk(clk),
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.vda(vda),
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.rw(rw),
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.ad(ad),
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.db(db),
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.rdy(prng_rdy)
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);
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always @(posedge clk)
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if (~locked)
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Led <= 8'h00;
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else begin
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if (~cs0 && ~rw && ad[7:0]==8'h00)
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Led <= db;
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end
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always @(posedge clk)
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if (~cs6 & ~rw && ad[23:15]==17'h0000)
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rammem[ad[13:0]] <= db;
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reg [7:0] ro;
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always @(posedge clk)
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case(ad[1:0])
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2'd0: ro <= rommem[ad[13:2]][7:0];
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2'd1: ro <= rommem[ad[13:2]][15:8];
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2'd2: ro <= rommem[ad[13:2]][23:16];
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2'd3: ro <= rommem[ad[13:2]][31:24];
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endcase
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/*
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always @(posedge clk)
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if (~cs4 & ~rw)
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case(ad[1:0])
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2'd0: rommem[ad[13:2]][7:0] <= db;
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2'd0: rommem[ad[13:2]][15:8] <= db;
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2'd0: rommem[ad[13:2]][23:16] <= db;
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2'd0: rommem[ad[13:2]][31:24] <= db;
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endcase
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*/
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reg [7:0] ramo;
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reg ramrdy;
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always @(posedge clk)
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ramo <= rammem[ad[13:0]];
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always @(posedge clk)
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ramrdy <= ~cs6;
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assign db = rw & ~cs1 ? sw : {8{1'bz}};
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assign db = rw & ~cs4 ? ro : {8{1'bz}};
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assign db = (rw & ~cs6 && ad[23:15]==17'h0000) ? ramo : {8{1'bz}};
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wire ram_rdy = ~cs6 ? (~rw ? 1'b1 : ramrdy) : 1'b1;
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FT816mpu u1
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(
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.rst(~rst),
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.clk(clk),
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.phi11(),
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.phi12(),
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.phi81(),
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.phi82(),
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.rdy(prng_rdy & tc_rdy & ram_rdy),
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.e(),
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.mx(),
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.nmi(~kbd_rst),
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.irq(~btn[1]),
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.abort(1'b1),
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.be(1'b1),
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.vpa(),
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.vda(vda),
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.mlb(),
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.vpb(),
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.rw(rw),
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.ad(ad),
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.db(db),
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.cs0(cs0),
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.cs1(cs1),
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.cs2(),
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.cs3(),
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.cs4(cs4),
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.cs5(),
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.cs6(cs6)
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);
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endmodule
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