EclaireXL

Register bus_data before we write it

Fixed c0 decode and made more explicit

Simulated and repaired 6502 bus and sram bus

constraint all cart input/outputs - 1.79MHz so not a problem. Improve sram constraints - including adding a bit of hold time.

register output data

Missed commit

Simulated/corrected sram back-back write timings

First cut implementation of veronica clone for ultimate cart - does not work yet, but getting close. Project to try out Rob Finchs 65816 core.