Revision 445
Added by markw about 9 years ago
| ultimate_cart/veronica/slave_timing_6502.vhd | ||
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when state_write =>
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if (delay_reg(2)='1') then -- n+4 cycles
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bus_data_in_next <= bus_data;
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end if;
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if (delay_reg(3)='1') then -- n+4 cycles
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bus_request <= '1';
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state_next <= state_phi;
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bus_request <= '1';
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end if;
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when state_read_start =>
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if (delay_reg(0)='1') then -- n+4 cycles
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Also available in: Unified diff
Register bus_data before we write it