Revision 442
Added by markw over 9 years ago
| ultimate_cart/veronica/veronica.sdc | ||
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derive_clock_uncertainty
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create_clock -period 14MHz -name sram_clk
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create_clock -period 98MHz -name fast_sram_clk
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set_output_delay -clock sram_clk -max 60.0 [get_ports EXT_SRAM_ADDR[*]]
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set_output_delay -clock sram_clk -min 0.0 [get_ports EXT_SRAM_ADDR[*]]
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set_output_delay -clock sram_clk -min -1.0 [get_ports EXT_SRAM_ADDR[*]]
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set_output_delay -clock sram_clk -max 60.0 [get_ports EXT_SRAM_DATA[*]]
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set_output_delay -clock sram_clk -min 0.0 [get_ports EXT_SRAM_DATA[*]]
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set_output_delay -clock fast_sram_clk -max 1.0 [get_ports EXT_SRAM_WE]
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set_output_delay -clock fast_sram_clk -min 0.0 [get_ports EXT_SRAM_WE]
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set_output_delay -clock fast_sram_clk -max 1.0 [get_ports EXT_SRAM_DATA[*]]
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set_output_delay -clock fast_sram_clk -min -1.0 [get_ports EXT_SRAM_DATA[*]]
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set_input_delay -clock sram_clk -max 60.0 [get_ports EXT_SRAM_DATA[*]]
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set_input_delay -clock sram_clk -min 0.0 [get_ports EXT_SRAM_DATA[*]]
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create_clock -period 14MHz -name cart_clk
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set_input_delay -clock cart_clk -max 0.0 [get_ports CART_ADDR[*]]
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set_input_delay -clock cart_clk -min 0.0 [get_ports CART_ADDR[*]]
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set_input_delay -clock cart_clk -max 0.0 [get_ports CART_DATA[*]]
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set_input_delay -clock cart_clk -min 0.0 [get_ports CART_DATA[*]]
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set_input_delay -clock cart_clk -max 0.0 [get_ports CART_CTL]
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set_input_delay -clock cart_clk -min 0.0 [get_ports CART_CTL]
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set_input_delay -clock cart_clk -max 0.0 [get_ports CART_S4]
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set_input_delay -clock cart_clk -min 0.0 [get_ports CART_S4]
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set_input_delay -clock cart_clk -max 0.0 [get_ports CART_S5]
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set_input_delay -clock cart_clk -min 0.0 [get_ports CART_S5]
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set_input_delay -clock cart_clk -max 0.0 [get_ports CART_RW]
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set_input_delay -clock cart_clk -min 0.0 [get_ports CART_RW]
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set_input_delay -clock cart_clk -max 0.0 [get_ports CART_PHI2]
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set_input_delay -clock cart_clk -min 0.0 [get_ports CART_PHI2]
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set_output_delay -clock cart_clk -max 0.0 [get_ports CART_DATA[*]]
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set_output_delay -clock cart_clk -min 0.0 [get_ports CART_DATA[*]]
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set_output_delay -clock cart_clk -max 0.0 [get_ports CART_RD4]
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set_output_delay -clock cart_clk -min 0.0 [get_ports CART_RD4]
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set_output_delay -clock cart_clk -max 0.0 [get_ports CART_RD5]
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set_output_delay -clock cart_clk -min 0.0 [get_ports CART_RD5]
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Also available in: Unified diff
constraint all cart input/outputs - 1.79MHz so not a problem. Improve sram constraints - including adding a bit of hold time.