repo2/ultimate_cart/veronica/veronica.sdc @ 441
| 438 | markw | create_clock -period 40MHz [get_ports CLK]
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derive_pll_clocks
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derive_clock_uncertainty
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create_clock -period 14MHz -name sram_clk
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set_output_delay -clock sram_clk -max 60.0 [get_ports EXT_SRAM_ADDR[*]]
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set_output_delay -clock sram_clk -min 0.0 [get_ports EXT_SRAM_ADDR[*]]
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set_output_delay -clock sram_clk -max 60.0 [get_ports EXT_SRAM_DATA[*]]
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set_output_delay -clock sram_clk -min 0.0 [get_ports EXT_SRAM_DATA[*]]
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set_input_delay -clock sram_clk -max 60.0 [get_ports EXT_SRAM_DATA[*]]
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set_input_delay -clock sram_clk -min 0.0 [get_ports EXT_SRAM_DATA[*]]
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