EclaireXL

oldcpu_enable => ENABLE_179_MEMWAIT,

CPU_ENABLE_OUT => CPU_SHARED_ENABLE);

cpu6502 : entity work.cpu

PORT MAP(CLK => CLK,

RESET => CPU_6502_RESET,

DMA_ADDR : in std_logic_vector(23 downto 0);

DMA_WRITE_DATA : in std_logic_vector(31 downto 0);

MEMORY_READY_DMA : out std_logic; -- op complete

-- Special config params

RAM_SELECT : in std_logic_vector(2 downto 0); -- 64K,128K,320KB Compy, 320KB Rambo, 576K Compy, 576K Rambo, 1088K, 4MB

-- PBI

PBI_ADDR => open,

PBI_WRITE_ENABLE => open,

PBI_WRITE_DATA => PBI_WRITE_DATA,

PBI_WIDTH_8bit_ACCESS => SDRAM_8BIT_WRITE_ENABLE,

PBI_WIDTH_16bit_ACCESS => SDRAM_16BIT_WRITE_ENABLE,