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       Index: atari800core_mcc.vhd
 
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       ===================================================================
 
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       --- atari800core_mcc.vhd	(revision 270)
 
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       +++ atari800core_mcc.vhd	(working copy)
 
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       @@ -245,8 +223,15 @@
 
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        	signal CLK_SDRAM : std_logic;
 
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        	-- SDRAM
 
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       +	signal PREREG_SDRAM_REQUEST : std_logic;
 
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       +	signal PREREG_SDRAM_READ_ENABLE :  STD_LOGIC;
 
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       +	signal PREREG_SDRAM_WRITE_ENABLE : std_logic;
 
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       +	signal PREREG_SDRAM_ADDR : STD_LOGIC_VECTOR(22 DOWNTO 0);
 
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       +	SIGNAL PREREG_SDRAM_DI : std_logic_vector(31 downto 0);
 
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       +	SIGNAL PREREG_SDRAM_WIDTH_32BIT_ACCESS : std_logic;
 
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       +	SIGNAL PREREG_SDRAM_WIDTH_16BIT_ACCESS : std_logic;
 
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       +	SIGNAL PREREG_SDRAM_WIDTH_8BIT_ACCESS : std_logic;
 
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        	signal SDRAM_REQUEST : std_logic;
 
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       -	signal SDRAM_REQUEST_COMPLETE : std_logic;
 
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        	signal SDRAM_READ_ENABLE :  STD_LOGIC;
 
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        	signal SDRAM_WRITE_ENABLE : std_logic;
 
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        	signal SDRAM_ADDR : STD_LOGIC_VECTOR(22 DOWNTO 0);
 
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       @@ -254,6 +239,8 @@
 
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        	SIGNAL SDRAM_WIDTH_32BIT_ACCESS : std_logic;
 
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        	SIGNAL SDRAM_WIDTH_16BIT_ACCESS : std_logic;
 
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        	SIGNAL SDRAM_WIDTH_8BIT_ACCESS : std_logic;
 
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       +
 
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       +	signal SDRAM_REQUEST_COMPLETE : std_logic;
 
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        	signal SDRAM_REFRESH : std_logic;
 
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       @@ -570,16 +535,16 @@
 
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        		CONSOL_SELECT => CONSOL_SELECT,
 
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        		CONSOL_START => CONSOL_START,
 
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       -		SDRAM_REQUEST => SDRAM_REQUEST,
 
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       +		SDRAM_REQUEST => PREREG_SDRAM_REQUEST,
 
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        		SDRAM_REQUEST_COMPLETE => SDRAM_REQUEST_COMPLETE,
 
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       -		SDRAM_READ_ENABLE => SDRAM_READ_ENABLE,
 
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       -		SDRAM_WRITE_ENABLE => SDRAM_WRITE_ENABLE,
 
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       -		SDRAM_ADDR => SDRAM_ADDR,
 
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       +		SDRAM_READ_ENABLE => PREREG_SDRAM_READ_ENABLE,
 
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       +		SDRAM_WRITE_ENABLE => PREREG_SDRAM_WRITE_ENABLE,
 
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       +		SDRAM_ADDR => PREREG_SDRAM_ADDR,
 
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        		SDRAM_DO => ram_do_reg,
 
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       -		SDRAM_DI => SDRAM_DI,
 
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       -		SDRAM_32BIT_WRITE_ENABLE => SDRAM_WIDTH_32bit_ACCESS,
 
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       -		SDRAM_16BIT_WRITE_ENABLE => SDRAM_WIDTH_16bit_ACCESS,
 
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       -		SDRAM_8BIT_WRITE_ENABLE => SDRAM_WIDTH_8bit_ACCESS,
 
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       +		SDRAM_DI => PREREG_SDRAM_DI,
 
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       +		SDRAM_32BIT_WRITE_ENABLE => PREREG_SDRAM_WIDTH_32bit_ACCESS,
 
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       +		SDRAM_16BIT_WRITE_ENABLE => PREREG_SDRAM_WIDTH_16bit_ACCESS,
 
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       +		SDRAM_8BIT_WRITE_ENABLE => PREREG_SDRAM_WIDTH_8bit_ACCESS,
 
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        		SDRAM_REFRESH => SDRAM_REFRESH,
 
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        		DMA_FETCH => dma_fetch,
 
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       @@ -605,7 +570,7 @@
 
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        	process(clk_sdram,sdram_reset_ctrl_n_reg)
 
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        	begin
 
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        		if (sdram_reset_ctrl_n_reg='0') then
 
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       -			seq_reg <= "100000000000";
 
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       +			seq_reg <= "010000000000";
 
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        			seq_ph_reg <= '1';
 
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        			ref_reg <= '0';
 
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       @@ -653,7 +618,7 @@
 
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        	process(seq_reg, seq_next, sdram_rdy, sdram_reset_n_reg, reset_atari)
 
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        	begin
 
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        		sdram_reset_n_next <= sdram_reset_n_reg;
 
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       -		if (sdram_rdy = '1' and seq_next(8)='1' and seq_reg(8)='0') then
 
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       +		if (sdram_rdy = '1' and seq_next(7)='1' and seq_reg(7)='0') then
 
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        			sdram_reset_n_next <= '1';
 
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        		end if;
 
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        		if (reset_atari = '1') then
 
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       @@ -661,10 +626,34 @@
 
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        		end if;
 
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        	end process;
 
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       +	-- register sdram request on the falling edge, 1/3 timing not enough, but 1/2 timing should be... This pushes back request 1 clock cycle. Result can also be clocking on the falling edge!
 
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       +	process(clk,reset_n)
 
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       +	begin
 
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       +		if (reset_n='0') then
 
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       +			SDRAM_REQUEST <= '0';
 
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       +			SDRAM_READ_ENABLE <= '0';
 
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       +			SDRAM_WRITE_ENABLE <= '0';
 
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       +			SDRAM_ADDR <= (others=>'0');
 
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       +			SDRAM_DI <= (others=>'0');
 
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       +			SDRAM_WIDTH_32BIT_ACCESS <= '0';
 
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       +			SDRAM_WIDTH_16BIT_ACCESS <= '0';
 
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       +			SDRAM_WIDTH_8BIT_ACCESS <= '0';
 
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       +		elsif(clk'event and clk='0') then -- FALLING EDGE
 
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       +			SDRAM_REQUEST <= PREREG_SDRAM_REQUEST;
 
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       +			SDRAM_READ_ENABLE <= PREREG_SDRAM_READ_ENABLE;
 
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       +			SDRAM_WRITE_ENABLE <= PREREG_SDRAM_WRITE_ENABLE;
 
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       +			SDRAM_ADDR <= PREREG_SDRAM_ADDR;
 
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       +			SDRAM_DI <= PREREG_SDRAM_DI;
 
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       +			SDRAM_WIDTH_32BIT_ACCESS <= PREREG_SDRAM_WIDTH_32BIT_ACCESS;
 
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       +			SDRAM_WIDTH_16BIT_ACCESS <= PREREG_SDRAM_WIDTH_16BIT_ACCESS;
 
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       +			SDRAM_WIDTH_8BIT_ACCESS <= PREREG_SDRAM_WIDTH_8BIT_ACCESS;
 
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       +		end if;
 
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       +	end process;
 
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       +
 
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        	-- Adapt SDRAM
 
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        	process(sdram_request_reg, sdram_request, sdram_request_complete_reg, ram_do_reg, seq_reg, ram_do, ram_rd_active, ram_wr_active, SDRAM_WIDTH_8BIT_ACCESS, SDRAM_WRITE_ENABLE, SDRAM_READ_ENABLE, SDRAM_DI, SDRAM_ADDR)
 
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        	begin
 
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       -		sdram_request_next <= sdram_request_reg or sdram_request;
 
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       +		sdram_request_next <= (sdram_request_reg or sdram_request) and not(sdram_request_complete_reg);
 
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        		sdram_request_complete_next <= sdram_request_complete_reg;
 
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        		ram_bena_next <= "00";
 
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        		ram_di_next <= (others=>'0');
 
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       @@ -699,9 +688,9 @@
 
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        		when "000000001000" =>
 
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        			-- nop
 
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        		when "000000010000" =>
 
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       -			sdram_request_complete_next <= '0';
 
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        			-- nop
 
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        		when "000000100000" =>
 
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       +			sdram_request_complete_next <= '0';
 
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        			-- nop
 
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        		when "000001000000" =>
 
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        			if (SDRAM_READ_ENABLE = '1') then
 
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       @@ -732,9 +721,9 @@
 
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        		when "001000000000" =>
 
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        			-- nop
 
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        		when "010000000000" =>
 
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       -			sdram_request_complete_next <= '0';
 
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        			-- nop
 
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        		when "100000000000" =>
 
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       +			sdram_request_complete_next <= '0';
 
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        			-- nop
 
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        		when others =>
 
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        			-- never
 
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