Revision 423
Added by markw over 9 years ago
| pll_0002.v | ||
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// interface 'outclk2'
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output wire outclk_2,
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// interface 'outclk3'
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output wire outclk_3,
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// interface 'locked'
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output wire locked
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);
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| ... | ... | |
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.fractional_vco_multiplier("false"),
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.reference_clock_frequency("5.0 MHz"),
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.operation_mode("normal"),
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.number_of_clocks(3),
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.number_of_clocks(4),
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.output_clock_frequency0("113.500000 MHz"),
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.phase_shift0("0 ps"),
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.duty_cycle0(50),
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| ... | ... | |
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.output_clock_frequency2("113.500000 MHz"),
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.phase_shift2("4405 ps"),
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.duty_cycle2(50),
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.output_clock_frequency3("0 MHz"),
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.output_clock_frequency3("28.375 MHz"),
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.phase_shift3("0 ps"),
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.duty_cycle3(50),
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.output_clock_frequency4("0 MHz"),
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| ... | ... | |
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.pll_subtype("General")
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) altera_pll_i (
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.rst (rst),
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.outclk ({outclk_2, outclk_1, outclk_0}),
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.outclk ({outclk_3, outclk_2, outclk_1, outclk_0}),
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.locked (locked),
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.fboutclk ( ),
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.fbclk (1'b0),
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Also available in: Unified diff
Added build for svideo/composite mode