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---------------------------------------------------------------------------
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-- (c) 2013 mark watson
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-- I am happy for anyone to use this for non-commercial use.
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-- If my vhdl files are used commercially or otherwise sold,
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-- please contact me for explicit permission at scrameta (gmail).
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-- This applies for source and binary form and derived works.
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---------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity gpiov3 is
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generic
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(
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cartridge_cycle_length : in integer := 32
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);
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port
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(
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clk : in std_logic;
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reset_n : in std_logic;
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gpio_enable : in std_logic;
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-- pia
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porta_in : out std_logic_vector(7 downto 0);
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porta_out : in std_logic_vector(7 downto 0);
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porta_output : in std_logic_vector(7 downto 0);
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CA1_IN : OUT STD_LOGIC;
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CA2_DIR_OUT : IN std_logic;
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CA2_OUT : IN std_logic;
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CA2_IN : OUT STD_LOGIC;
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CB1_IN : OUT STD_LOGIC;
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CB2_DIR_OUT : IN std_logic;
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CB2_OUT : IN std_logic;
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CB2_IN : OUT STD_LOGIC;
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-- gtia
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trig_in : out std_logic_vector(3 downto 0);
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-- antic
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lightpen : out std_logic;
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-- pokey
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pot_reset : in std_logic;
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pot_in : out std_logic_vector(7 downto 0);
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keyboard_scan : in std_logic_vector(5 downto 0);
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keyboard_response : out std_logic_vector(1 downto 0);
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SIO_IN : OUT STD_LOGIC;
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SIO_OUT : IN STD_LOGIC;
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SIO_CLOCKIN : OUT STD_LOGIC;
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SIO_CLOCKOUT : IN STD_LOGIC;
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-- cartridge
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enable_179_early : in std_logic;
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pbi_addr_out : in std_logic_vector(15 downto 0);
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pbi_write_enable : in std_logic;
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cart_data_read : out std_logic_vector(7 downto 0);
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cart_request : in std_logic;
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cart_complete : out std_logic;
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cart_data_write : in std_logic_vector(7 downto 0);
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rd4 : out std_logic;
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rd5 : out std_logic;
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s4_n : in std_logic;
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s5_n : in std_logic;
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cctl_n : in std_logic;
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-- gpio connections
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GPIO_0_IN : in std_logic_vector(35 downto 0);
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GPIO_0_OUT : out std_logic_vector(35 downto 0);
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GPIO_0_DIR_OUT : out std_logic_vector(35 downto 0);
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GPIO_1_IN : in std_logic_vector(35 downto 0);
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GPIO_1_OUT : out std_logic_vector(35 downto 0);
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GPIO_1_DIR_OUT : out std_logic_vector(35 downto 0)
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);
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end gpiov3;
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architecture vhdl of gpiov3 is
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signal gpio0_out_next : std_logic_vector(35 downto 0);
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signal gpio0_out_reg : std_logic_vector(35 downto 0);
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signal gpio1_out_next : std_logic_vector(35 downto 0);
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signal gpio1_out_reg : std_logic_vector(35 downto 0);
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signal gpio0_dir_next : std_logic_vector(35 downto 0);
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signal gpio0_dir_reg : std_logic_vector(35 downto 0);
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signal gpio1_dir_next : std_logic_vector(35 downto 0);
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signal gpio1_dir_reg : std_logic_vector(35 downto 0);
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signal bit_next : std_logic_vector(5 downto 0);
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signal bit_reg : std_logic_vector(5 downto 0);
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constant state_clear : std_logic_vector(1 downto 0) := "00";
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constant state_read : std_logic_vector(1 downto 0) := "01";
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constant state_drive : std_logic_vector(1 downto 0) := "10";
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signal state_next : std_logic_vector(1 downto 0);
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signal state_reg : std_logic_vector(1 downto 0);
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signal mem_write : std_logic;
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begin
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CA2_in <= '1';
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CB2_in <= '1';
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SIO_IN <= '1';
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pot_in <= (others=>'0');
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porta_in <= (others=>'1');
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trig_in <= "0111";
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lightpen <= '1';
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-- keyboard
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keyboard_response <= (others=>'1');
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cart_data_read <= (others=>'1');
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cart_complete <= '1';
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rd4 <= '0';
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rd5 <= '0';
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process(clk,reset_n)
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begin
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if (reset_n='0') then
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bit_reg <= (others=>'0');
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gpio0_out_reg <= (others=>'0');
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gpio1_out_reg <= (others=>'0');
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gpio0_dir_reg <= (others=>'1');
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gpio1_dir_reg <= (others=>'1');
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state_reg <= state_clear;
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elsif (clk'event and clk='1') then
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bit_reg <= bit_next;
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gpio0_out_reg <= gpio0_out_next;
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gpio1_out_reg <= gpio1_out_next;
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gpio0_dir_reg <= gpio0_dir_next;
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gpio1_dir_reg <= gpio1_dir_next;
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state_reg <= state_next;
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end if;
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end process;
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-- Process is as follows
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-- i) drive all to 0, drive on everywhere
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-- ii) drive a bit to 1, drive on only that bit
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-- iii) read the value of all gpios and store
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-- iv) next bit
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process(enable_179_early,state_reg,bit_reg,gpio0_out_reg,gpio0_dir_reg,gpio1_out_reg,gpio1_dir_reg,gpio_0_in,gpio_1_in)
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begin
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bit_next <= bit_reg;
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gpio0_out_next <= gpio0_out_reg;
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gpio1_out_next <= gpio1_out_reg;
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gpio0_dir_next <= gpio0_dir_reg;
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gpio1_dir_next <= gpio1_dir_reg;
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state_next <= state_reg;
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mem_write <= '0';
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if (enable_179_early = '1') then
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case state_reg is
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when state_clear =>
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state_next <= state_drive;
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-- prepare to drive
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gpio0_out_next <= (others=>'0');
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gpio1_out_next <= (others=>'0');
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gpio0_dir_next <= (others=>'0');
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gpio1_dir_next <= (others=>'0');
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gpio0_out_next(to_integer(unsigned(bit_reg))) <= '1';
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gpio0_dir_next(to_integer(unsigned(bit_reg))) <= '1';
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when state_drive =>
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state_next <= state_read;
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--prepare to read
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gpio0_dir_next <= (others=>'0');
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gpio1_dir_next <= (others=>'0');
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when state_read =>
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state_next <= state_clear;
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-- store to ram
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mem_write <= '1';
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-- prepare to clear
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gpio0_out_next <= (others=>'0');
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gpio1_out_next <= (others=>'0');
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gpio0_dir_next <= (others=>'1');
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gpio1_dir_next <= (others=>'1');
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-- next bit!
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bit_next <= std_logic_vector(unsigned(bit_reg)+1);
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if (bit_reg=std_logic_vector(to_unsigned(35,6))) then
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bit_next <= (others=>'0');
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end if;
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when others=>
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state_next <= state_clear;
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end case;
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end if;
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end process;
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gpioram: ENTITY work.gpioram
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PORT MAP
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(
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address => bit_reg,
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clock => clk,
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data => gpio_0_in&gpio_1_in,
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wren => mem_write,
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q => open
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);
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GPIO_0_OUT <= gpio0_out_reg;
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GPIO_0_DIR_OUT <= gpio0_dir_reg;
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GPIO_1_OUT <= gpio1_out_reg;
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GPIO_1_DIR_OUT <= gpio1_dir_reg;
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end vhdl;
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