EclaireXL

cd ../mist

./build.sh > build.log 2> build.err&

cd ../mcc216

SIGNAL q_ram : std_logic_vector(data_width-1 downto 0);

SIGNAL we_ram : std_logic;

BEGIN

PROCESS (clock)

BEGIN

IF (clock'event AND clock = '1') THEN

IF (we_ram = '1') THEN

q_ram <= data;

ELSE

END IF;

END IF;

END PROCESS;

begin

q <= (others=>'1');

we_ram <= '0';

IF (to_integer(to_01(unsigned(address))) < space) THEN

q <= q_ram;

we_ram <= we;

end if;

end process;

END rtl;

use ieee.numeric_std.all;

ENTITY scandoubler IS

PORT

(

CLK : IN STD_LOGIC;

constant CLK_A_PERIOD : time := 1 us / (1.79*32);

signal AUDIO_L : std_logic_vector(15 downto 0);

signal AUDIO_R : std_logic_vector(15 downto 0);

GENERIC MAP

(

cycle_length => 32,

)

PORT MAP

(

CLK => clk_a,

RESET_N => reset_n,

AUDIO_L => audio_l,

AUDIO_R => audio_r,

GPIO_0(1) <= SIO_COMMAND;

-- THROTTLE

-- VIDEO

VGA_HS <= not(VGA_HS_RAW xor VGA_VS_RAW);

CLK => CLK,

RESET_N => RESET_N and SDRAM_RESET_N and not(SYSTEM_RESET_REQUEST),

AUDIO_L => AUDIO_LEFT,

AUDIO_R => AUDIO_RIGHT,

SDRAM_ADDR => SDRAM_ADDR,

SDRAM_DO => SDRAM_DO,

RAM_ADDR => RAM_ADDR,

RAM_DO => RAM_DO,

TV : integer; -- 1 = PAL, 0=NTSC

VIDEO : integer; -- 1 = SVIDEO, 2 = VGA

SCANDOUBLE : integer; -- 1 = YES, 0=NO, (+ later scanlines etc)

);

PORT

(

FPGA_CLK : IN STD_LOGIC;

PS2K_CLK : IN STD_LOGIC;

PS2K_DAT : IN STD_LOGIC;

PS2M_CLK : IN STD_LOGIC;

signal sdram_dq_i : std_logic_vector(15 downto 0);

signal sdram_rdy : std_logic;

-- pokey keyboard

SIGNAL KEYBOARD_SCAN : std_logic_vector(5 downto 0);

dac_out => audio_r

);

end generate;

end generate;

reset_n <= PLL_LOCKED;

JOY2_IN_N <= JOY2_n(4)&JOY2_n(0)&JOY2_n(1)&JOY2_n(2)&JOY2_n(3);

-- THROTTLE

--atari800xl : entity work.atari800core_helloworld

-- GENERIC MAP

(

CLK => CLK,

--RESET_N => RESET_N and SDRAM_RESET_N and not(SYSTEM_RESET_REQUEST),

VIDEO_VS => VIDEO_VS,

VIDEO_HS => VIDEO_HS,

THROTTLE_COUNT_6502 => THROTTLE_COUNT_6502

);

begin

ref_reg <= '0';

ram_do_reg <= (others=>'0');

end if;

end process;

-- Generate sdram sequence

process(seq_reg, seq_ph_reg, ref_reg)

begin

seq_next <= seq_reg(10 downto 0)&seq_reg(11);

seq_ph_next <= seq_ph_reg;

ref_next <= ref_reg;

seq_ph_next <= not(seq_ph_reg);

ref_next <= not(ref_reg);

end if;

end process;

-- Adapt SDRAM

process(sdram_request_reg, sdram_request, sdram_request_complete_reg, ram_do_reg, seq_reg, ram_do, ram_rd_active, ram_wr_active, SDRAM_WIDTH_8BIT_ACCESS, SDRAM_WRITE_ENABLE, SDRAM_READ_ENABLE, SDRAM_DI, SDRAM_ADDR)

begin

when "000000001000" =>

-- nop

when "000000010000" =>

-- nop

when "000000100000" =>

-- nop

when "000001000000" =>

if (SDRAM_READ_ENABLE = '1') then

if (SDRAM_WIDTH_8BIT_ACCESS = '1') then

if (SDRAM_ADDR(0) = '0') then

when "001000000000" =>

-- nop

when "010000000000" =>

-- nop

when "100000000000" =>

-- nop

when others =>

-- never

PORT MAP

(

CLK => CLK_SDRAM,

seq_cyc => seq_reg(11 downto 0),

seq_ph => seq_ph_reg,

--refr_cyc => ref_reg,

refr_cyc => SDRAM_REFRESH,

ap1_address => '0'&SDRAM_ADDR(22 downto 1),

ap1_rden => SDRAM_READ_ENABLE,

ap1_wren => SDRAM_WRITE_ENABLE,

"TV" => $PAL,

"SCANDOUBLE" => 0,

"VIDEO" => $VGA,

},

"PAL_SVIDEO" =>

{

"TV" => $PAL,

"SCANDOUBLE" => 0,

"VIDEO" => $SVIDEO,

},

"PAL_VGA" =>

{

"TV" => $PAL,

"SCANDOUBLE" => 1,

"VIDEO" => $VGA,

},

"NTSC_SVIDEO" =>

{

"TV" => $NTSC,

"SCANDOUBLE" => 0,

"VIDEO" => $SVIDEO,

},

"NTSC_VGA" =>

{

"TV" => $NTSC,

"SCANDOUBLE" => 1,

"VIDEO" => $VGA,

}

);

cp `find ../../common/a8core/ -iname "*.vhdl"` .

cp `find ../../common/components/ -iname "*.vhd"` .

cp `find ../../common/components/ -iname "*.vhdl"` .

cp ../sdram_ctrl_3_ports.v .

# set up project definition file

ls *.v | perl -e 'while (<>){s/(.*)/verilog work $1/;print $_;}' | cat > $name.prj

architecture rtl of atari800core_mcc_tb is

signal reset_n : std_logic;

signal reset : std_logic;

signal SDRAM_DQ : std_logic_vector(15 downto 0);

begin

begin

end process;

begin

end process;

reset_n <= '0', '1' after 1000ns;

reset <= not(reset_n);

atari : ENTITY work.atari800core_mcc

port map

(

PS2K_CLK => '1',

PS2K_DAT => '1',

PS2M_CLK => '1',

reset_n <= PLL_LOCKED;

-- THROTTLE

atarixl_simple_sdram1 : entity work.atari800core_simple_sdram

GENERIC MAP

CLK => CLK,

RESET_N => RESET_N and SDRAM_RESET_N and not(SYSTEM_RESET_REQUEST),

AUDIO_L => AUDIO_L_PCM,

AUDIO_R => AUDIO_R_PCM,

gtia_player.vhdl

gtia_priority.vhdl

gtia.vhdl

irq_glue.vhdl

pia.vhdl

pokey_countdown_timer.vhdl

basic.vhdl

os16.vhdl

os16_loop.vhdl

covox.vhd

atari800core.vhd

atari800core_simple_sdram.vhd

#How does this not conflict with RAM? I use this area...

[MENU]

option = "Med (1)", 0x00020000

option = "Min (0)", 0x00000000

## menu entry - ATARIXL SETUP

title = "800XL Setup"

option = "OSB original",0x00000028

option = "OSA original",0x00000030

i_Rst_Core : in bit1;

i_Halt_Core : in bit1;

i_HD_Mode : in bit1; -- selects between the HD and SD video mode generic

o_act_led_n : out bit1;

--

i_Audio_lvl : in word(1 downto 0);

CONF_DI : in word(7 downto 0);

ram_select : in word(2 downto 0);

);

end;

constant int_dla_core_debug : boolean := false;

signal PLL_LOCKED : std_logic;

signal res_s : bit1;

signal core_en_s : bit1;

signal keyboard_scan_inv : std_logic_vector(5 downto 0);

signal matrix_out_match : std_logic_vector(7 downto 0);

begin

-- core control

res_s <= i_Rst_Core;

CONSOL_OPTION <= static_keys(4);

-- system_reset_request <= static_keys(3);

atarixl_simple_sdram1 : entity work.atari800core_simple_sdram

GENERIC MAP

CLK => i_clk_sys,

RESET_N => PLL_LOCKED,

AUDIO_L => lsound_s,

AUDIO_R => rsound_s,

u_Kbd : entity work.Replay_TranslatePS2

generic map (

)

port map (

i_ClK_Sys => i_ClK_Sys,

i_Rst_Sys => i_Rst_Sys,

--

i_HD_Mode => i_HD_Mode,

--

i_Vid_r => std_logic_vector(core_r_s),

i_Vid_g => std_logic_vector(core_g_s),

if (i_rst_sys = '1') then

ddr_request_pending_reg <= '0';

ddr_response_pending_reg <= '0';

elsif (i_clk_sys'event and i_clk_sys='1') then

ddr_request_pending_reg <= ddr_request_pending_next;

ddr_response_pending_reg <= ddr_response_pending_next;

end if;

end process;

i_Rst_Core => rst_soft,

i_Halt_Core => halt_soft,

i_HD_Mode => cfg_dynamic(16),

o_act_led_n => o_Disk_Led,

--

i_Audio_lvl => cfg_dynamic(18 downto 17),

CONF_DI => mch_data,

--

ram_select => cfg_dynamic(2 downto 0),

);

-- 8 16 1 1 1 1 1 1 1 1 1 1 2