EclaireXL

CONSOL_OPTION : IN STD_LOGIC;

CONSOL_SELECT : IN STD_LOGIC;

CONSOL_START : IN STD_LOGIC;

-----------------------

-- After here all FPGA implementation specific

-- TODO - review/explain what all these are for

SIGNAL CPU_SHARED_ENABLE : STD_LOGIC;

SIGNAL ENABLE_179_MEMWAIT : STD_LOGIC;

SIGNAL POKEY_ENABLE_179 : STD_LOGIC;

SIGNAL ANTIC_ENABLE_179 : STD_LOGIC;

SIGNAL SCANDOUBLER_SHARED_ENABLE_HIGH : STD_LOGIC;

SIGNAL PIA_IRQB : STD_LOGIC;

SIGNAL PIA_READ_ENABLE : STD_LOGIC;

SIGNAL PIA_WRITE_ENABLE : STD_LOGIC;

BEGIN

PBI_WIDTH_8bit_ACCESS <= WIDTH_8bit_access;

PBI_WRITE_DATA <= WRITE_DATA;

PBI_SNOOP_DATA <= MEMORY_DATA;

enables : entity work.shared_enable

GENERIC MAP(cycle_length => cycle_length)

PORT MAP(CLK => CLK,

RESET_N => RESET_N,

MEMORY_READY_CPU => MEMORY_READY_CPU,

MEMORY_READY_ANTIC => MEMORY_READY_ANTIC,

THROTTLE_COUNT_6502 => THROTTLE_COUNT_6502,

POKEY_ENABLE_179 => POKEY_ENABLE_179,

ANTIC_ENABLE_179 => ANTIC_ENABLE_179,

SCANDOUBLER_ENABLE_HIGH => SCANDOUBLER_SHARED_ENABLE_HIGH);

cpu6502 : entity work.cpu

PORT MAP(CLK => CLK,

RESET => CPU_6502_RESET,

ANTIC_ENABLE_179 => ANTIC_ENABLE_179,

PAL => PAL,

lightpen => LIGHTPEN,

CPU_DATA_IN => WRITE_DATA(7 DOWNTO 0),

MEMORY_DATA_IN => MEMORY_DATA(7 DOWNTO 0),

NMI_N_OUT => NMI_n,

ANTIC_MEMORY_READY => MEMORY_READY_ANTIC,

WR_EN => POKEY2_WRITE_ENABLE,

RESET_N => RESET_N,

DATA_IN => WRITE_DATA(7 DOWNTO 0),

CHANNEL_0_OUT => POKEY2_CHANNEL0,

CHANNEL_1_OUT => POKEY2_CHANNEL1,

CB2_DIR_OUT => CB2_DIR_OUT,

CB2_IN => CB2_IN,

CB2_OUT => CB2_OUT,

CPU_DATA_IN => WRITE_DATA(7 DOWNTO 0),

IRQA_N => PIA_IRQA,

IRQB_N => PIA_IRQB,

PORTA_OUT => PORTA_OUT,

PORTB_IN => PORTB_IN,

PORTB_DIR_OUT => PORTB_DIR_OUT,

mmu1 : entity work.address_decoder

PORT MAP(CLK => CLK,

CACHE_POKEY2_DATA => CACHE_POKEY2_DO,

POKEY_DATA => POKEY_DO,

CACHE_POKEY_DATA => CACHE_POKEY_DO,

RAM_DATA => RAM_DO,

ram_select => RAM_SELECT(2 downto 0),

ROM_DATA => ROM_DO,

rom_select => ROM_SELECT,

SDRAM_DATA => SDRAM_DO,

MEMORY_READY_ANTIC => MEMORY_READY_ANTIC,

MEMORY_READY_DMA => MEMORY_READY_DMA,

MEMORY_READY_CPU => MEMORY_READY_CPU,

SDRAM_REQUEST => SDRAM_REQUEST,

SDRAM_REFRESH => SDRAM_REFRESH,

MEMORY_DATA => MEMORY_DATA,

RAM_ADDR => RAM_ADDR,

ROM_ADDR => ROM_ADDR,

SDRAM_ADDR => SDRAM_ADDR,

SIO_IN1 => SIO_RXD,

SIO_IN2 => '1',

SIO_IN3 => '1',

DATA_IN => WRITE_DATA(7 DOWNTO 0),

keyboard_response => KEYBOARD_RESPONSE,

POT_IN => POT_IN,

CONSOL_START => CONSOL_START,

CONSOL_SELECT => CONSOL_SELECT,

CONSOL_OPTION => CONSOL_OPTION,

AN => ANTIC_AN,

CPU_DATA_IN => WRITE_DATA(7 DOWNTO 0),

MEMORY_DATA_IN => MEMORY_DATA(7 DOWNTO 0),

generic map(BYTES=>16,WIDTH=>4)

port map(

CLK => CLK,

DATA_IN => WRITE_DATA(7 downto 0),

WR_EN => POKEY_WRITE_ENABLE,

DATA_OUT => CACHE_POKEY_DO

generic map(BYTES=>16,WIDTH=>4)

port map(

CLK => CLK,

DATA_IN => WRITE_DATA(7 downto 0),

WR_EN => POKEY2_WRITE_ENABLE,

DATA_OUT => CACHE_POKEY2_DO

generic map(BYTES=>32,WIDTH=>5)

port map(

CLK => CLK,

DATA_IN => WRITE_DATA(7 downto 0),

WR_EN => GTIA_WRITE_ENABLE,

DATA_OUT => CACHE_GTIA_DO

generic map(BYTES=>16,WIDTH=>4)

port map(

CLK => CLK,

DATA_IN => WRITE_DATA(7 downto 0),

WR_EN => ANTIC_WRITE_ENABLE,

DATA_OUT => CACHE_ANTIC_DO

PORT map

(

clk => clk,

data_in => WRITE_DATA(7 DOWNTO 0),

wr_en => covox_write_enable,

covox_channel0 => covox_channel0,

covox_channel3 => covox_channel3

);

END bdf_type;

-- Simple version that:

-- i) needs: CLK(58 or 28MHZ) joystick,PS2 keyboard

-- ii) provides: VIDEO,AUDIO,ROM,RAM

(

-- use CLK of 1.79*cycle_length

-- I've tested 16 and 32 only, but 4 and 8 might work...

internal_ram : integer := 16384 -- at start of memory map

);

-- video standard

PAL : in STD_LOGIC

end atari800core_helloworld;

ARCHITECTURE vhdl OF atari800core_helloworld IS

SIGNAL CONSOL_START : std_logic;

SIGNAL CONSOL_SELECT : std_logic;

SIGNAL CONSOL_OPTION : std_logic;

BEGIN

-- PS2 to pokey

PORT MAP

(

CLK => clk,

);

-- THROTTLE

GENERIC MAP

(

cycle_length => cycle_length,

internal_rom => 1,

internal_ram =>internal_ram

(

CLK => CLK,

RESET_N => RESET_N,

CONSOL_OPTION => CONSOL_OPTION,

CONSOL_SELECT => CONSOL_SELECT,

SDRAM_REQUEST => open,

SDRAM_REQUEST_COMPLETE => '1',

-- Simple version that:

-- i) needs: CLK(58 or 28MHZ) SDRAM,joystick,keyboard

-- ii) provides: VIDEO,AUDIO

-- THIS SHOULD DO FOR ALL PLATFORMS EXCEPT THOSE USING GPIO FOR PBI etc

GENERIC

(

-- use CLK of 1.79*cycle_length

-- I've tested 16 and 32 only, but 4 and 8 might work...

-- For initial port may help to have no

internal_ram : integer := 16384 -- at start of memory map

);

PORT

RAM_SELECT : in std_logic_vector(2 downto 0); -- 64K,128K,320KB Compy, 320KB Rambo, 576K Compy, 576K Rambo, 1088K, 4MB

ROM_SELECT : in std_logic_vector(5 downto 0); -- 16KB ROM Bank - 0 is illegal (slot used for BASIC!)

PAL : in STD_LOGIC;

-- PIA

SIGNAL CA1_IN : STD_LOGIC;

SIGNAL CA2_OUT : STD_LOGIC;

SIGNAL CA2_DIR_OUT: STD_LOGIC;

SIGNAL CB2_OUT : STD_LOGIC;

SIGNAL CA2_IN: STD_LOGIC;

SIGNAL CB2_IN: STD_LOGIC;

SIGNAL PORTA_IN : STD_LOGIC_VECTOR(7 DOWNTO 0);

SIGNAL PORTB_IN : STD_LOGIC_VECTOR(7 DOWNTO 0);

-- CARTRIDGE ACCESS

SIGNAL CART_RD4 : STD_LOGIC;

SIGNAL CART_RD5 : STD_LOGIC;

SIGNAL ROM_REQUEST : STD_LOGIC;

SIGNAL ROM_REQUEST_COMPLETE : STD_LOGIC;

BEGIN

-- PIA mapping

PORTA_IN <= ((JOY1_n(3)&JOY1_n(2)&JOY1_n(1)&JOY1_n(0)&JOY2_n(3)&JOY2_n(2)&JOY2_n(1)&JOY2_n(0)) and not (porta_dir_out)) or (porta_dir_out and porta_out);

PORTB_IN <= PORTB_OUT;

-- Cartridge not inserted

CART_RD4 <= '0';

CART_RD5 <= '0';

GENERIC MAP

(

internal_rom => internal_rom,

PORT MAP (

clock => CLK,

reset_n => RESET_N,

ROM_ADDR => ROM_ADDR,

ROM_REQUEST => ROM_REQUEST,

ROM_DATA => ROM_DO,

RAM_ADDR => RAM_ADDR,

RAM_DATA_IN => PBI_WRITE_DATA(7 downto 0),

RAM_REQUEST_COMPLETE => RAM_REQUEST_COMPLETE,

RAM_REQUEST => RAM_REQUEST,

);

atari800xl : entity work.atari800core

GENERIC MAP

(

cycle_length => cycle_length

PORT MAP

(

CLK => CLK,

VGA_VS => VGA_VS,

VGA_HS => VGA_HS,

CONSOL_OPTION => CONSOL_OPTION,

CONSOL_SELECT => CONSOL_SELECT,

CONSOL_START=> CONSOL_START,

SDRAM_REQUEST => SDRAM_REQUEST,

SDRAM_REQUEST_COMPLETE => SDRAM_REQUEST_COMPLETE,

ninebits := rmwBits;

end case;

varZ := rmwBits(1);

varZ := '1';

else

varZ := '0';

null;

end case;

varN := rmwBits(7);

else

varN := nineBits(7);

end if;

varC := ninebits(8);

varC := aluInput(7);

varV := aluInput(7) xor aluInput(6);

end if;

nextOpcode <= myNextOpcode;

end process;

process(clk)

begin

if rising_edge(clk) then

BEGIN

IF (clock'event AND clock = '1') THEN

q<= (others=>'1');

IF (we = '1') THEN

END IF;

END IF;

END IF;

END PROCESS;

ENTITY internalromram IS

GENERIC

(

internal_ram : integer := 16384

);

PORT(

end if;

end process;

rom16a : os16

PORT MAP(clock => clock,

address => rom_addr(13 downto 0),

rom_request_complete <= rom_request_reg;

end generate;

ROM16_data <= (others=>'0');

end generate;

ramint1 : generic_ram_infer

generic map

(

);

ram_request_complete <= ram_request_reg;

end generate;

ram_request_complete <='0';

ram_data <= (others=>'1');

end generate;

KEYBOARD_SCAN : IN STD_LOGIC_VECTOR(5 downto 0);

KEYBOARD_RESPONSE : OUT STD_LOGIC_VECTOR(1 downto 0);

);

signal ps2_keys_next : std_logic_vector(255 downto 0);

signal ps2_keys_reg : std_logic_vector(255 downto 0);

signal atari_keyboard : std_logic_vector(63 downto 0);

SIGNAL SHIFT_PRESSED : STD_LOGIC;

SIGNAL BREAK_PRESSED : STD_LOGIC;

SIGNAL CONTROL_PRESSED : STD_LOGIC;

BEGIN

PORT MAP

(

CLK => CLK,

end process;

-- map to atari key code

begin

atari_keyboard <= (others=>'0');

shift_pressed <= '0';

control_pressed <= '0';

break_pressed <= '0';

end process;

-- provide results as if we were a grid to pokey...

keyboard_response(1) <= '0';

end if;

end process;

END vhdl;