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Revision 381

Added by markw about 10 years ago

No idea what this is or why I checked it in;-)

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eclaireXL/atari800core_eclaireXL.qpf
# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, the Altera Quartus II License Agreement,
# the Altera MegaCore Function License Agreement, or other
# applicable license agreement, including, without limitation,
# that your use is for the sole purpose of programming logic
# devices manufactured by Altera and sold by Altera or its
# authorized distributors. Please refer to the applicable
# agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 14.0.0 Build 200 06/17/2014 SJ Web Edition
# Date created = 20:32:21 July 11, 2015
#
# -------------------------------------------------------------------------- #
QUARTUS_VERSION = "14.0"
DATE = "20:32:21 July 11, 2015"
# Revisions
PROJECT_REVISION = "atari800core_eclaireXL"
eclaireXL/atari800core_eclaireXL.qsf
# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, the Altera Quartus II License Agreement,
# the Altera MegaCore Function License Agreement, or other
# applicable license agreement, including, without limitation,
# that your use is for the sole purpose of programming logic
# devices manufactured by Altera and sold by Altera or its
# authorized distributors. Please refer to the applicable
# agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 14.0.0 Build 200 06/17/2014 SJ Web Edition
# Date created = 20:32:21 July 11, 2015
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# atari800core_eclaireXL_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY "Cyclone V"
set_global_assignment -name DEVICE 5CEBA2F23C8
set_global_assignment -name TOP_LEVEL_ENTITY atari800core_eclaireXL
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 14.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "20:32:21 JULY 11, 2015"
set_global_assignment -name LAST_QUARTUS_VERSION 14.0
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
set_global_assignment -name VHDL_FILE atari800core_eclaireXL.vhd
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name VHDL_FILE gpio.vhd
set_global_assignment -name VHDL_FILE gpiov2.vhd
set_global_assignment -name VHDL_FILE atari800core_de1.vhd
set_global_assignment -name QIP_FILE pll_pal.qip
set_global_assignment -name QIP_FILE pll_ntsc.qip
set_global_assignment -name QIP_FILE pll.qip
set_global_assignment -name VHDL_FILE zpu_rom.vhdl
set_location_assignment PIN_H16 -to CLOCK_5
set_location_assignment PIN_A5 -to VGA_R[0]
set_location_assignment PIN_B5 -to VGA_R[1]
set_location_assignment PIN_B6 -to VGA_R[2]
set_location_assignment PIN_D6 -to VGA_R[3]
set_location_assignment PIN_C6 -to VGA_R[4]
set_location_assignment PIN_A7 -to VGA_R[5]
set_location_assignment PIN_B7 -to VGA_R[6]
set_location_assignment PIN_E7 -to VGA_R[7]
set_location_assignment PIN_D7 -to VGA_G[0]
set_location_assignment PIN_F7 -to VGA_G[1]
set_location_assignment PIN_A8 -to VGA_G[2]
set_location_assignment PIN_G8 -to VGA_G[3]
set_location_assignment PIN_C8 -to VGA_G[4]
set_location_assignment PIN_H8 -to VGA_G[5]
set_location_assignment PIN_A9 -to VGA_G[6]
set_location_assignment PIN_D9 -to VGA_G[7]
set_location_assignment PIN_C9 -to VGA_BLANK_N
set_location_assignment PIN_E9 -to VGA_B[0]
set_location_assignment PIN_F9 -to VGA_B[1]
set_location_assignment PIN_A10 -to VGA_B[2]
set_location_assignment PIN_B10 -to VGA_B[3]
set_location_assignment PIN_E10 -to VGA_B[4]
set_location_assignment PIN_F10 -to VGA_B[5]
set_location_assignment PIN_G10 -to VGA_B[6]
set_location_assignment PIN_B11 -to VGA_B[7]
set_location_assignment PIN_G11 -to VGA_CLK
set_location_assignment PIN_C11 -to VGA_HS
set_location_assignment PIN_H11 -to VGA_VS
set_location_assignment PIN_J11 -to AUDIO_LEFT
set_location_assignment PIN_A12 -to AUDIO_RIGHT
set_location_assignment PIN_B12 -to GPIOC[17]
set_location_assignment PIN_D12 -to GPIOC[16]
set_location_assignment PIN_E12 -to GPIOC[15]
set_location_assignment PIN_F12 -to GPIOC[14]
set_location_assignment PIN_A13 -to GPIOC[13]
set_location_assignment PIN_B13 -to GPIOC[12]
set_location_assignment PIN_D13 -to GPIOC[11]
set_location_assignment PIN_C13 -to GPIOC[10]
set_location_assignment PIN_F13 -to GPIOC[9]
set_location_assignment PIN_G13 -to GPIOC[8]
set_location_assignment PIN_A14 -to GPIOC[7]
set_location_assignment PIN_E14 -to GPIOC[6]
set_location_assignment PIN_F14 -to GPIOC[5]
set_location_assignment PIN_H14 -to GPIOC[4]
set_location_assignment PIN_A15 -to GPIOC[3]
set_location_assignment PIN_B15 -to GPIOC[2]
set_location_assignment PIN_E15 -to GPIOC[1]
set_location_assignment PIN_C15 -to GPIOC[0]
set_location_assignment PIN_F15 -to GPIOA[0]
set_location_assignment PIN_G15 -to GPIOB[0]
set_location_assignment PIN_B16 -to GPIOA[1]
set_location_assignment PIN_E16 -to GPIOB[1]
set_location_assignment PIN_C16 -to GPIOA[2]
set_location_assignment PIN_D17 -to GPIOB[2]
set_location_assignment PIN_G17 -to GPIOA[3]
set_location_assignment PIN_G18 -to GPIOB[3]
set_location_assignment PIN_G16 -to GPIOA[4]
set_location_assignment PIN_H18 -to GPIOB[4]
set_location_assignment PIN_J18 -to GPIOA[5]
set_location_assignment PIN_J19 -to GPIOB[5]
set_location_assignment PIN_J17 -to GPIOA[6]
set_location_assignment PIN_K22 -to GPIOB[6]
set_location_assignment PIN_K21 -to GPIOA[7]
set_location_assignment PIN_K19 -to GPIOB[7]
set_location_assignment PIN_K20 -to GPIOA[8]
set_location_assignment PIN_K17 -to GPIOB[8]
set_location_assignment PIN_K16 -to GPIOA[9]
set_location_assignment PIN_L22 -to GPIOB[9]
set_location_assignment PIN_L19 -to GPIOA[10]
set_location_assignment PIN_L18 -to GPIOB[10]
set_location_assignment PIN_L17 -to GPIOA[11]
set_location_assignment PIN_M22 -to GPIOB[11]
set_location_assignment PIN_M21 -to GPIOA[12]
set_location_assignment PIN_M18 -to GPIOB[12]
set_location_assignment PIN_M20 -to GPIOA[13]
set_location_assignment PIN_M16 -to GPIOB[13]
set_location_assignment PIN_N21 -to GPIOA[14]
set_location_assignment PIN_N19 -to GPIOB[14]
set_location_assignment PIN_N20 -to GPIOA[15]
set_location_assignment PIN_N16 -to GPIOB[15]
set_location_assignment PIN_P22 -to GPIOA[16]
set_location_assignment PIN_P18 -to GPIOB[16]
set_location_assignment PIN_P19 -to GPIOA[17]
set_location_assignment PIN_P17 -to GPIOB[17]
set_location_assignment PIN_P16 -to GPIOA[18]
set_location_assignment PIN_R22 -to GPIOB[18]
set_location_assignment PIN_R21 -to GPIOA[19]
set_location_assignment PIN_R17 -to GPIOB[19]
set_location_assignment PIN_R16 -to GPIOA[20]
set_location_assignment PIN_T22 -to GPIOB[20]
set_location_assignment PIN_T19 -to GPIOA[21]
set_location_assignment PIN_T20 -to GPIOB[21]
set_location_assignment PIN_T18 -to GPIOA[22]
set_location_assignment PIN_T17 -to GPIOB[22]
set_location_assignment PIN_U22 -to GPIOA[23]
set_location_assignment PIN_U21 -to GPIOB[23]
set_location_assignment PIN_U20 -to GPIOA[24]
set_location_assignment PIN_V21 -to GPIOB[24]
set_location_assignment PIN_V19 -to GPIOA[25]
set_location_assignment PIN_V20 -to GPIOB[25]
set_location_assignment PIN_W22 -to GPIOA[26]
set_location_assignment PIN_W21 -to GPIOB[26]
set_location_assignment PIN_Y22 -to GPIOA[27]
set_location_assignment PIN_Y21 -to GPIOB[27]
set_location_assignment PIN_AA22 -to GPIOA[28]
set_location_assignment PIN_AB22 -to GPIOB[28]
set_location_assignment PIN_AB21 -to GPIOA[29]
set_location_assignment PIN_AB20 -to GPIOB[29]
set_location_assignment PIN_AA20 -to GPIOA[30]
set_location_assignment PIN_Y20 -to GPIOB[30]
set_location_assignment PIN_AA19 -to GPIOA[31]
set_location_assignment PIN_W19 -to GPIOB[31]
set_location_assignment PIN_Y19 -to GPIOA[32]
set_location_assignment PIN_AB18 -to GPIOB[32]
set_location_assignment PIN_AA18 -to GPIOA[33]
set_location_assignment PIN_V18 -to GPIOB[33]
set_location_assignment PIN_AB17 -to GPIOA[34]
set_location_assignment PIN_AA17 -to GPIOB[34]
set_location_assignment PIN_U17 -to GPIOA[35]
set_location_assignment PIN_Y17 -to GPIOB[35]
set_location_assignment PIN_Y16 -to GPIOC[35]
set_location_assignment PIN_V16 -to GPIOC[34]
set_location_assignment PIN_W16 -to GPIOC[33]
set_location_assignment PIN_U16 -to GPIOC[32]
set_location_assignment PIN_AB15 -to GPIOC[31]
set_location_assignment PIN_AA15 -to GPIOC[30]
set_location_assignment PIN_V15 -to GPIOC[29]
set_location_assignment PIN_Y15 -to GPIOC[28]
set_location_assignment PIN_U15 -to GPIOC[27]
set_location_assignment PIN_T15 -to GPIOC[26]
set_location_assignment PIN_AA14 -to GPIOC[25]
set_location_assignment PIN_V14 -to GPIOC[24]
set_location_assignment PIN_Y14 -to GPIOC[23]
set_location_assignment PIN_T14 -to GPIOC[22]
set_location_assignment PIN_R14 -to GPIOC[21]
set_location_assignment PIN_AB13 -to GPIOC[20]
set_location_assignment PIN_AA13 -to GPIOC[19]
set_location_assignment PIN_V13 -to GPIOC[18]
set_location_assignment PIN_U13 -to SD_WRITEPROTECT
set_location_assignment PIN_T13 -to SD_DETECT
set_location_assignment PIN_AB12 -to SD_DAT1
set_location_assignment PIN_AA12 -to SD_DAT0
set_location_assignment PIN_U12 -to SD_CLK
set_location_assignment PIN_T12 -to SD_CMD
set_location_assignment PIN_R12 -to SD_DAT3
set_location_assignment PIN_AB11 -to SD_DAT2
set_location_assignment PIN_U11 -to PS2CLK
set_location_assignment PIN_Y11 -to PS2DAT
set_location_assignment PIN_R11 -to USB2DM
set_location_assignment PIN_AB10 -to USB2DP
set_location_assignment PIN_AA10 -to USB1DM
set_location_assignment PIN_V10 -to USB1DP
set_location_assignment PIN_Y10 -to DRAM_ADDR[4]
set_location_assignment PIN_U10 -to DRAM_ADDR[5]
set_location_assignment PIN_T10 -to DRAM_ADDR[6]
set_location_assignment PIN_AA9 -to DRAM_ADDR[7]
set_location_assignment PIN_W9 -to DRAM_ADDR[8]
set_location_assignment PIN_Y9 -to DRAM_ADDR[9]
set_location_assignment PIN_V9 -to DRAM_ADDR[11]
set_location_assignment PIN_T9 -to DRAM_ADDR[12]
set_location_assignment PIN_AB8 -to DRAM_CKE
set_location_assignment PIN_AA8 -to DRAM_CLK
set_location_assignment PIN_U8 -to DRAM_UDQM
set_location_assignment PIN_W8 -to DRAM_DQ[8]
set_location_assignment PIN_T8 -to DRAM_DQ[9]
set_location_assignment PIN_AB7 -to DRAM_DQ[10]
set_location_assignment PIN_AA7 -to DRAM_DQ[11]
set_location_assignment PIN_U7 -to DRAM_DQ[12]
set_location_assignment PIN_AB6 -to DRAM_DQ[13]
set_location_assignment PIN_V6 -to DRAM_DQ[14]
set_location_assignment PIN_AB5 -to DRAM_DQ[15]
set_location_assignment PIN_U6 -to DRAM_ADDR[3]
set_location_assignment PIN_T7 -to DRAM_ADDR[2]
set_location_assignment PIN_R5 -to DRAM_ADDR[1]
set_location_assignment PIN_R6 -to DRAM_ADDR[0]
set_location_assignment PIN_R7 -to DRAM_ADDR[10]
set_location_assignment PIN_P6 -to DRAM_BA_1
set_location_assignment PIN_P7 -to DRAM_BA_0
set_location_assignment PIN_P8 -to DRAM_CS_N
set_location_assignment PIN_N6 -to DRAM_RAS_N
set_location_assignment PIN_N8 -to DRAM_CAS_N
set_location_assignment PIN_N9 -to DRAM_WE_N
set_location_assignment PIN_M6 -to DRAM_LDQM
set_location_assignment PIN_M7 -to DRAM_DQ[7]
set_location_assignment PIN_M8 -to DRAM_DQ[6]
set_location_assignment PIN_L7 -to DRAM_DQ[5]
set_location_assignment PIN_L8 -to DRAM_DQ[4]
set_location_assignment PIN_K7 -to DRAM_DQ[0]
set_location_assignment PIN_K9 -to DRAM_DQ[1]
set_location_assignment PIN_J7 -to DRAM_DQ[2]
set_location_assignment PIN_J8 -to DRAM_DQ[3]
set_location_assignment PIN_H6 -to ADC_SDA
set_location_assignment PIN_G6 -to ADC_SCL
eclaireXL/atari800core_eclaireXL.sdc
create_clock -period 50MHz [get_ports CLOCK_5]
derive_pll_clocks
eclaireXL/atari800core_eclaireXL.vhd
---------------------------------------------------------------------------
-- (c) 2013 mark watson
-- I am happy for anyone to use this for non-commercial use.
-- If my vhdl files are used commercially or otherwise sold,
-- please contact me for explicit permission at scrameta (gmail).
-- This applies for source and binary form and derived works.
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.numeric_std.all;
LIBRARY work;
ENTITY atari800core_eclaireXL IS
GENERIC
(
TV : integer; -- 1 = PAL, 0=NTSC
GPIO : integer -- 1 = OLD GPIO LAYOUT, 2=NEW GPIO LAYOUT (WIP)
);
PORT
(
CLOCK_5 : IN STD_LOGIC;
PS2CLK : IN STD_LOGIC;
PS2DAT : IN STD_LOGIC;
GPIOA : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0);
GPIOB : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0);
GPIOC: INOUT STD_LOGIC_VECTOR(35 DOWNTO 0);
DRAM_BA_0 : OUT STD_LOGIC;
DRAM_BA_1 : OUT STD_LOGIC;
DRAM_CS_N : OUT STD_LOGIC;
DRAM_RAS_N : OUT STD_LOGIC;
DRAM_CAS_N : OUT STD_LOGIC;
DRAM_WE_N : OUT STD_LOGIC;
DRAM_LDQM : OUT STD_LOGIC;
DRAM_UDQM : OUT STD_LOGIC;
DRAM_CLK : OUT STD_LOGIC;
DRAM_CKE : OUT STD_LOGIC;
DRAM_ADDR : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
DRAM_DQ : INOUT STD_LOGIC_VECTOR(15 DOWNTO 0);
SD_WRITEPROTECT : IN STD_LOGIC;
SD_DETECT : IN STD_LOGIC;
--SD_DAT1 : IN STD_LOGIC;
SD_DAT0 : IN STD_LOGIC;
SD_CLK : OUT STD_LOGIC;
SD_CMD : OUT STD_LOGIC;
SD_DAT3 : OUT STD_LOGIC;
--SD_DAT2 : IN STD_LOGIC;
VGA_VS : OUT STD_LOGIC;
VGA_HS : OUT STD_LOGIC;
VGA_B : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
VGA_G : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
VGA_R : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
VGA_BLANK_N : OUT STD_LOGIC;
VGA_CLK : OUT STD_LOGIC;
AUDIO_LEFT : OUT STD_LOGIC;
AUDIO_RIGHT : OUT STD_LOGIC;
USB2DM: INOUT STD_LOGIC;
USB2DP: INOUT STD_LOGIC;
USB1DM: INOUT STD_LOGIC;
USB1DP: INOUT STD_LOGIC;
ADC_SDA: INOUT STD_LOGIC;
ADC_SCL: INOUT STD_LOGIC
);
END atari800core_eclaireXL;
ARCHITECTURE vhdl OF atari800core_eclaireXL IS
component hq_dac
port (
reset :in std_logic;
clk :in std_logic;
clk_ena : in std_logic;
pcm_in : in std_logic_vector(19 downto 0);
dac_out : out std_logic
);
end component;
-- SYSTEM
SIGNAL CLK : STD_LOGIC;
SIGNAL CLK_SDRAM : STD_LOGIC;
SIGNAL RESET_N : STD_LOGIC;
signal SDRAM_RESET_N : std_logic;
SIGNAL PLL_LOCKED : STD_LOGIC;
-- PIA
SIGNAL CA1_IN : STD_LOGIC;
SIGNAL CB1_IN: STD_LOGIC;
SIGNAL CA2_OUT : STD_LOGIC;
SIGNAL CA2_DIR_OUT: STD_LOGIC;
SIGNAL CB2_OUT : STD_LOGIC;
SIGNAL CB2_DIR_OUT: STD_LOGIC;
SIGNAL CA2_IN: STD_LOGIC;
SIGNAL CB2_IN: STD_LOGIC;
SIGNAL PORTA_IN : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL PORTA_OUT : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL PORTA_DIR_OUT : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL PORTB_IN : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL PORTB_OUT : STD_LOGIC_VECTOR(7 DOWNTO 0);
--SIGNAL PORTB_DIR_OUT : STD_LOGIC_VECTOR(7 DOWNTO 0);
-- GTIA
signal GTIA_TRIG : std_logic_vector(3 downto 0);
-- ANTIC
signal ANTIC_LIGHTPEN : std_logic;
-- CARTRIDGE ACCESS
SIGNAL CART_RD4 : STD_LOGIC;
SIGNAL CART_RD5 : STD_LOGIC;
SIGNAL CART_S4_n : STD_LOGIC;
SIGNAL CART_S5_n : STD_LOGIC;
SIGNAL CART_CCTL_n : STD_LOGIC;
-- PBI
SIGNAL PBI_WRITE_DATA : std_logic_vector(31 downto 0);
SIGNAL PBI_WIDTH_32BIT_ACCESS : std_logic;
SIGNAL PBI_WIDTH_16BIT_ACCESS : std_logic;
SIGNAL PBI_WIDTH_8BIT_ACCESS : std_logic;
-- INTERNAL ROM/RAM
SIGNAL RAM_ADDR : STD_LOGIC_VECTOR(18 DOWNTO 0);
SIGNAL RAM_DO : STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL RAM_REQUEST : STD_LOGIC;
SIGNAL RAM_REQUEST_COMPLETE : STD_LOGIC;
SIGNAL RAM_WRITE_ENABLE : STD_LOGIC;
SIGNAL ROM_ADDR : STD_LOGIC_VECTOR(21 DOWNTO 0);
SIGNAL ROM_DO : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL ROM_REQUEST : STD_LOGIC;
SIGNAL ROM_REQUEST_COMPLETE : STD_LOGIC;
-- SDRAM
signal SDRAM_REQUEST : std_logic;
signal SDRAM_REQUEST_COMPLETE : std_logic;
signal SDRAM_READ_ENABLE : STD_LOGIC;
signal SDRAM_WRITE_ENABLE : std_logic;
signal SDRAM_ADDR : STD_LOGIC_VECTOR(22 DOWNTO 0);
signal SDRAM_DO : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal SDRAM_REFRESH : std_logic;
-- pokey keyboard
SIGNAL KEYBOARD_SCAN : std_logic_vector(5 downto 0);
SIGNAL KEYBOARD_RESPONSE : std_logic_vector(1 downto 0);
-- gtia consol keys
SIGNAL CONSOL_START : std_logic;
SIGNAL CONSOL_SELECT : std_logic;
SIGNAL CONSOL_OPTION : std_logic;
-- SIO
SIGNAL SIO_RXD : std_logic;
SIGNAL SIO_COMMAND : std_logic;
SIGNAL SIO_TXD : std_logic;
SIGNAL GPIO_SIO_RXD : std_logic;
SIGNAL SIO_CLOCKOUT : std_logic;
SIGNAL SIO_CLOCKIN : std_logic;
-- VIDEO
signal VGA_VS_RAW : std_logic;
signal VGA_HS_RAW : std_logic;
signal VGA_CS_RAW : std_logic;
signal VGA_BLANK : std_logic;
-- AUDIO
signal AUDIO_L_PCM : std_logic_vector(15 downto 0);
signal AUDIO_R_PCM : std_logic_vector(15 downto 0);
-- dma/virtual drive
signal DMA_ADDR_FETCH : std_logic_vector(23 downto 0);
signal DMA_WRITE_DATA : std_logic_vector(31 downto 0);
signal DMA_FETCH : std_logic;
signal DMA_32BIT_WRITE_ENABLE : std_logic;
signal DMA_16BIT_WRITE_ENABLE : std_logic;
signal DMA_8BIT_WRITE_ENABLE : std_logic;
signal DMA_READ_ENABLE : std_logic;
signal DMA_MEMORY_READY : std_logic;
signal DMA_MEMORY_DATA : std_logic_vector(31 downto 0);
signal ZPU_ADDR_ROM : std_logic_vector(15 downto 0);
signal ZPU_ROM_DATA : std_logic_vector(31 downto 0);
signal ZPU_OUT1 : std_logic_vector(31 downto 0);
signal ZPU_OUT2 : std_logic_vector(31 downto 0);
signal ZPU_OUT3 : std_logic_vector(31 downto 0);
signal ZPU_OUT4 : std_logic_vector(31 downto 0);
signal zpu_pokey_enable : std_logic;
signal zpu_sio_txd : std_logic;
signal zpu_sio_rxd : std_logic;
signal zpu_sio_command : std_logic;
SIGNAL FKEYS : std_logic_vector(11 downto 0);
-- system control from zpu
signal ram_select : std_logic_vector(2 downto 0);
signal reset_atari : std_logic;
signal pause_atari : std_logic;
SIGNAL speed_6502 : std_logic_vector(5 downto 0);
signal emulated_cartridge_select: std_logic_vector(5 downto 0);
-- GPIO
signal GPIOA_DIR_OUT : std_logic_vector(35 downto 0);
signal GPIOA_OUT : std_logic_vector(35 downto 0);
signal GPIOB_DIR_OUT : std_logic_vector(35 downto 0);
signal GPIOB_OUT : std_logic_vector(35 downto 0);
signal TRIGGERS : std_logic_vector(3 downto 0);
signal POT_RESET : std_logic;
signal POT_IN : std_logic_vector(7 downto 0);
signal GPIO_KEYBOARD_RESPONSE : std_logic_vector(1 downto 0);
signal PS2_KEYBOARD_RESPONSE : std_logic_vector(1 downto 0);
signal PBI_WRITE_ENABLE : std_logic;
signal PBI_ADDRESS : std_logic_vector(15 downto 0);
signal cart_request : std_logic;
signal cart_request_complete : std_logic;
signal cart_data : std_logic_vector(7 downto 0);
signal pbi_addr : std_logic_vector(15 downto 0);
signal enable_179_early : std_logic;
-- scandoubler
signal half_scandouble_enable_reg : std_logic;
signal half_scandouble_enable_next : std_logic;
signal VIDEO_B : std_logic_vector(7 downto 0);
signal freezer_enable : std_logic;
signal freezer_activate: std_logic;
signal freezer_state: std_logic_vector(2 downto 0);
signal pbi_enable: std_logic;
signal pal : std_logic;
signal PS2_KEYS : STD_LOGIC_VECTOR(511 downto 0);
signal PS2_KEYS_NEXT : STD_LOGIC_VECTOR(511 downto 0);
BEGIN
-- TODO
pbi_enable <= '1'; --SW(4);
PAL <= '1';-- SW(8);
-- ANYTHING NOT CONNECTED...
--GPIOA(0) <= 'Z';
--GPIOA(35 downto 2) <= (others=>'Z');
--GPIOB(35 downto 0) <= (others=>'Z');
sdram_adaptor : entity work.sdram_statemachine
GENERIC MAP(ADDRESS_WIDTH => 22,
AP_BIT => 10,
COLUMN_WIDTH => 8,
ROW_WIDTH => 12
)
PORT MAP(CLK_SYSTEM => CLK,
CLK_SDRAM => CLK_SDRAM,
RESET_N => RESET_N,
READ_EN => SDRAM_READ_ENABLE,
WRITE_EN => SDRAM_WRITE_ENABLE,
REQUEST => SDRAM_REQUEST,
BYTE_ACCESS => PBI_WIDTH_8BIT_ACCESS,
WORD_ACCESS => PBI_WIDTH_16BIT_ACCESS,
LONGWORD_ACCESS => PBI_WIDTH_32BIT_ACCESS,
REFRESH => SDRAM_REFRESH,
ADDRESS_IN => SDRAM_ADDR,
DATA_IN => PBI_WRITE_DATA(31 downto 0),
SDRAM_DQ => DRAM_DQ,
COMPLETE => SDRAM_REQUEST_COMPLETE,
SDRAM_BA0 => DRAM_BA_0,
SDRAM_BA1 => DRAM_BA_1,
SDRAM_CKE => DRAM_CKE,
SDRAM_CS_N => DRAM_CS_N,
SDRAM_RAS_N => DRAM_RAS_N,
SDRAM_CAS_N => DRAM_CAS_N,
SDRAM_WE_N => DRAM_WE_N,
SDRAM_ldqm => DRAM_LDQM,
SDRAM_udqm => DRAM_UDQM,
DATA_OUT => SDRAM_DO,
SDRAM_ADDR => DRAM_ADDR(11 downto 0),
reset_client_n => SDRAM_RESET_N
);
-- PIA mapping
-- emulate pull-up on command line
SIO_COMMAND <= CB2_OUT when CB2_DIR_OUT='1' else '1';
-- SIO_COMMAND <= CB2_OUT;
--PORTA_IN <= ((JOY2_n(3)&JOY2_n(2)&JOY2_n(1)&JOY2_n(0)&JOY1_n(3)&JOY1_n(2)&JOY1_n(1)&JOY1_n(0)) and not (porta_dir_out)) or (porta_dir_out and porta_out);
--PORTA_IN <= (not (porta_dir_out)) or (porta_dir_out and porta_out);
PORTB_IN <= PORTB_OUT;
-- GTIA triggers
--GTIA_TRIG <= CART_RD5&"1"&JOY2_n(4)&JOY1_n(4);
GTIA_TRIG <= "11"&TRIGGERS(1 downto 0);
-- Cartridge not inserted
--CART_RD4 <= '0';
--CART_RD5 <= '0';
-- Internal rom/ram
internalromram1 : entity work.internalromram
GENERIC MAP
(
internal_rom => 0,
internal_ram => 0
)
PORT MAP (
clock => CLK,
reset_n => RESET_N,
ROM_ADDR => ROM_ADDR,
ROM_REQUEST_COMPLETE => ROM_REQUEST_COMPLETE,
ROM_REQUEST => ROM_REQUEST,
ROM_DATA => ROM_DO,
RAM_ADDR => RAM_ADDR,
RAM_WR_ENABLE => RAM_WRITE_ENABLE,
RAM_DATA_IN => PBI_WRITE_DATA(7 downto 0),
RAM_REQUEST_COMPLETE => open,
RAM_REQUEST => RAM_REQUEST,
RAM_DATA => open
);
GPIOA_gen:
for I in 0 to 35 generate
GPIOA(I) <= GPIOA_out(I) when GPIOA_dir_out(I)='1' else 'Z';
end generate GPIOA_gen;
GPIO1_gen:
for I in 0 to 35 generate
GPIOB(I) <= GPIOB_out(I) when GPIOB_dir_out(I)='1' else 'Z';
end generate GPIO1_gen;
gen_old_gpio : if gpio=1 generate
GPIO1 : entity work.gpio
GENERIC MAP(
cartridge_cycle_length => 26
)
PORT MAP(clk => CLK,
reset_n => reset_n,
gpio_enable => pbi_enable,
pot_reset => pot_reset,
pbi_write_enable => pbi_write_enable,
enable_179_early => enable_179_early,
cart_request => cart_request,
cart_complete => cart_request_complete,
cart_data_read => cart_data,
s4_n => cart_s4_n,
s5_n => cart_s5_n,
cctl_n => cart_cctl_n,
cart_data_write => pbi_write_data(7 downto 0),
GPIO_0_IN => GPIOA,
GPIO_0_OUT => GPIOA_OUT,
GPIO_0_DIR_OUT => GPIOA_DIR_OUT,
GPIO_1_IN => GPIOB,
GPIO_1_OUT => GPIOB_OUT,
GPIO_1_DIR_OUT => GPIOB_DIR_OUT,
keyboard_scan => KEYBOARD_SCAN,
pbi_addr_out => pbi_addr,
porta_out => PORTA_OUT,
porta_output => PORTA_DIR_OUT,
lightpen => ANTIC_LIGHTPEN,
rd4 => CART_RD4,
rd5 => CART_RD5,
keyboard_response => GPIO_KEYBOARD_RESPONSE,
porta_in => PORTA_IN,
pot_in => pot_in,
trig_in => TRIGGERS,
CA2_DIR_OUT => CA2_DIR_OUT,
CA2_OUT => CA2_OUT,
CA2_IN => open,
CB2_DIR_OUT => CB2_DIR_OUT,
CB2_OUT => CB2_OUT,
CB2_IN => open,
SIO_IN => GPIO_SIO_RXD,
SIO_OUT => SIO_TXD
);
CA1_IN <= '1';
CB1_IN <= '1';
CA2_IN <= CA2_OUT when CA2_DIR_OUT='1' else '1';
CB2_IN <= CB2_OUT when CB2_DIR_OUT='1' else '1';
end generate gen_old_gpio;
gen_new_gpio : if gpio=2 generate
gpio2 : entity work.gpiov2
GENERIC MAP(
cartridge_cycle_length => 26
)
PORT MAP(clk => CLK,
reset_n => reset_n,
gpio_enable => pbi_enable,
pot_reset => pot_reset,
pbi_write_enable => pbi_write_enable,
enable_179_early => enable_179_early,
cart_request => cart_request,
cart_complete => cart_request_complete,
cart_data_read => cart_data,
s4_n => cart_s4_n,
s5_n => cart_s5_n,
cctl_n => cart_cctl_n,
cart_data_write => pbi_write_data(7 downto 0),
GPIO_0_IN => GPIOA,
GPIO_0_OUT => GPIOA_OUT,
GPIO_0_DIR_OUT => GPIOA_DIR_OUT,
GPIO_1_IN => GPIOB,
GPIO_1_OUT => GPIOB_OUT,
GPIO_1_DIR_OUT => GPIOB_DIR_OUT,
keyboard_scan => KEYBOARD_SCAN,
pbi_addr_out => pbi_addr,
porta_out => PORTA_OUT,
porta_output => PORTA_DIR_OUT,
lightpen => ANTIC_LIGHTPEN,
rd4 => CART_RD4,
rd5 => CART_RD5,
keyboard_response => GPIO_KEYBOARD_RESPONSE,
porta_in => PORTA_IN,
pot_in => pot_in,
trig_in => TRIGGERS,
CA2_DIR_OUT => CA2_DIR_OUT,
CA2_OUT => CA2_OUT,
CA2_IN => CA2_IN,
CB2_DIR_OUT => CB2_DIR_OUT,
CB2_OUT => CB2_OUT,
CB2_IN => CB2_IN,
SIO_IN => GPIO_SIO_RXD,
SIO_OUT => SIO_TXD,
SIO_CLOCKIN => SIO_CLOCKIN,
SIO_CLOCKOUT => SIO_CLOCKOUT
);
end generate gen_new_gpio;
process(clk,RESET_N,SDRAM_RESET_N,reset_atari)
begin
if ((RESET_N and SDRAM_RESET_N and not(reset_atari))='0') then
half_scandouble_enable_reg <= '0';
elsif (clk'event and clk='1') then
half_scandouble_enable_reg <= half_scandouble_enable_next;
end if;
end process;
half_scandouble_enable_next <= not(half_scandouble_enable_reg);
scandoubler : entity work.scandoubler
GENERIC MAP
(
video_bits=>8
)
PORT MAP(CLK => CLK,
RESET_N => RESET_N and SDRAM_RESET_N and not(reset_atari),
VGA => '0', -- TODO SW(7),
COMPOSITE_ON_HSYNC => '1', -- SW(6),
colour_enable => half_scandouble_enable_reg,
doubled_enable => '1',
scanlines_on => '0', -- SW(5),
vsync_in => VGA_VS_RAW,
hsync_in => VGA_HS_RAW,
csync_in => VGA_CS_RAW,
pal => PAL,
colour_in => VIDEO_B,
VSYNC => VGA_VS,
HSYNC => VGA_HS,
B => VGA_B,
G => VGA_G,
R => VGA_R);
VGA_BLANK_N <= NOT(VGA_BLANK);
-- TODO VGA_CLK <= '0';
--gen_ntsc_pll : if tv=0 generate
--pll : entity work.pll_ntsc
--PORT MAP(inclk0 => CLOCK_27(0),
-- c0 => CLK_SDRAM,
-- c1 => CLK,
-- c2 => DRAM_CLK,
-- locked => PLL_LOCKED);
--end generate;
--
--gen_pal_pll : if tv=1 generate
--pll : entity work.pll_pal
--PORT MAP(inclk0 => CLOCK_27(0),
-- c0 => CLK_SDRAM,
-- c1 => CLK,
-- c2 => DRAM_CLK,
-- locked => PLL_LOCKED);
--end generate;
--
--gen_old_pll : if tv=2 generate
pll : entity work.pll
PORT MAP(inclk0 => CLOCK_5, -- new PLL!
c0 => CLK_SDRAM,
c1 => CLK,
c2 => DRAM_CLK,
locked => PLL_LOCKED);
--end generate;
RESET_N <= PLL_LOCKED;
-- PS2 to pokey
keyboard_map1 : entity work.ps2_to_atari800
PORT MAP
(
CLK => clk,
RESET_N => reset_n,
PS2_CLK => ps2clk,
PS2_DAT => ps2dat,
KEYBOARD_SCAN => KEYBOARD_SCAN,
KEYBOARD_RESPONSE => PS2_KEYBOARD_RESPONSE,
CONSOL_START => CONSOL_START,
CONSOL_SELECT => CONSOL_SELECT,
CONSOL_OPTION => CONSOL_OPTION,
FKEYS => FKEYS,
FREEZER_ACTIVATE => freezer_activate,
PS2_KEYS_NEXT_OUT => ps2_keys_next,
PS2_KEYS => ps2_keys
);
KEYBOARD_RESPONSE <= PS2_KEYBOARD_RESPONSE and GPIO_KEYBOARD_RESPONSE;
-- SIO
-- TODO combine
--SIO_RXD <= UART_RXD;
--UART_TXD <= SIO_TXD;
--GPIOA(1) <= SIO_COMMAND;
zpu_sio_command <= SIO_COMMAND;
zpu_sio_rxd <= SIO_TXD;
SIO_RXD <= zpu_sio_txd and GPIO_SIO_RXD;
-- VIDEO
--VGA_HS <= not(VGA_HS_RAW xor VGA_VS_RAW);
--VGA_VS <= not(VGA_VS_RAW);
atari800 : entity work.atari800core
GENERIC MAP
(
cycle_length => 32,
video_bits => 8,
palette => 0
)
PORT MAP
(
CLK => CLK,
RESET_N => RESET_N and SDRAM_RESET_N and not(reset_atari),
VIDEO_VS => VGA_VS_RAW,
VIDEO_HS => VGA_HS_RAW,
VIDEO_CS => VGA_CS_RAW,
VIDEO_B => VIDEO_B,
VIDEO_G => open,
VIDEO_R => open,
VIDEO_BLANK => VGA_BLANK,
VIDEO_BURST => open,
VIDEO_START_OF_FIELD => open,
VIDEO_ODD_LINE => open,
AUDIO_L => AUDIO_L_PCM,
AUDIO_R => AUDIO_R_PCM,
CA1_IN => CA1_IN,
CB1_IN => CB1_IN,
CA2_IN => CA2_IN,
CA2_OUT => CA2_OUT,
CA2_DIR_OUT => CA2_DIR_OUT,
CB2_IN => CB2_IN,
CB2_OUT => CB2_OUT,
CB2_DIR_OUT => CB2_DIR_OUT,
PORTA_IN => PORTA_IN and not("0000"&ps2_keys(16#174#)&ps2_keys(16#16B#)&ps2_keys(16#172#)&ps2_keys(16#175#)),
PORTA_DIR_OUT => PORTA_DIR_OUT,
PORTA_OUT => PORTA_OUT,
PORTB_IN => PORTB_IN,
PORTB_DIR_OUT => open,--PORTB_DIR_OUT,
PORTB_OUT => PORTB_OUT,
KEYBOARD_RESPONSE => KEYBOARD_RESPONSE,
KEYBOARD_SCAN => KEYBOARD_SCAN,
POT_IN => POT_IN,
POT_RESET => POT_RESET,
ENABLE_179_EARLY => ENABLE_179_EARLY,
PBI_ADDR => PBI_ADDR,
PBI_WRITE_ENABLE => PBI_WRITE_ENABLE,
PBI_SNOOP_DATA => open,
PBI_WRITE_DATA => PBI_WRITE_DATA,
PBI_WIDTH_8bit_ACCESS => PBI_WIDTH_8bit_ACCESS,
PBI_WIDTH_16bit_ACCESS => PBI_WIDTH_16bit_ACCESS,
PBI_WIDTH_32bit_ACCESS => PBI_WIDTH_32bit_ACCESS,
PBI_ROM_DO => CART_DATA,
PBI_REQUEST => CART_REQUEST,
PBI_REQUEST_COMPLETE => CART_REQUEST_COMPLETE,
CART_RD4 => CART_RD4,
CART_RD5 => CART_RD5,
CART_S4_n => CART_S4_n,
CART_S5_N => CART_S5_n,
CART_CCTL_N => CART_CCTL_n,
SIO_RXD => SIO_RXD,
SIO_TXD => SIO_TXD,
SIO_CLOCKIN => SIO_CLOCKIN,
SIO_CLOCKOUT => SIO_CLOCKOUT,
CONSOL_OPTION => CONSOL_OPTION,
CONSOL_SELECT => CONSOL_SELECT,
CONSOL_START=> CONSOL_START,
GTIA_TRIG => GTIA_TRIG and not("000"&ps2_keys(16#127#)),
ANTIC_LIGHTPEN => ANTIC_LIGHTPEN,
SDRAM_REQUEST => SDRAM_REQUEST,
SDRAM_REQUEST_COMPLETE => SDRAM_REQUEST_COMPLETE,
SDRAM_READ_ENABLE => SDRAM_READ_ENABLE,
SDRAM_WRITE_ENABLE => SDRAM_WRITE_ENABLE,
SDRAM_ADDR => SDRAM_ADDR,
SDRAM_DO => SDRAM_DO,
ANTIC_REFRESH => SDRAM_REFRESH,
RAM_ADDR => RAM_ADDR,
RAM_DO => RAM_DO,
RAM_REQUEST => RAM_REQUEST,
RAM_REQUEST_COMPLETE => RAM_REQUEST_COMPLETE,
RAM_WRITE_ENABLE => RAM_WRITE_ENABLE,
ROM_ADDR => ROM_ADDR,
ROM_DO => ROM_DO,
ROM_REQUEST => ROM_REQUEST,
ROM_REQUEST_COMPLETE => ROM_REQUEST_COMPLETE,
DMA_FETCH => dma_fetch,
DMA_READ_ENABLE => dma_read_enable,
DMA_32BIT_WRITE_ENABLE => dma_32bit_write_enable,
DMA_16BIT_WRITE_ENABLE => dma_16bit_write_enable,
DMA_8BIT_WRITE_ENABLE => dma_8bit_write_enable,
DMA_ADDR => dma_addr_fetch,
DMA_WRITE_DATA => dma_write_data,
MEMORY_READY_DMA => dma_memory_ready,
--DMA_MEMORY_DATA => dma_memory_data,
PBI_SNOOP_DATA => DMA_MEMORY_DATA,
RAM_SELECT => ram_select,
CART_EMULATION_SELECT => emulated_cartridge_select,
PAL => PAL,
USE_SDRAM => '1', --SW(9),
ROM_IN_RAM => '1',
THROTTLE_COUNT_6502 => speed_6502,
HALT => pause_atari,
freezer_enable => freezer_enable,
freezer_activate => freezer_activate,
freezer_state_out => freezer_state,
pbi_enable => pbi_enable
);
zpu: entity work.zpucore
GENERIC MAP
(
platform => 1,
spi_clock_div => 1 -- 28MHz/2. Max for SD cards is 25MHz...
)
PORT MAP
(
-- standard...
CLK => CLK,
RESET_N => RESET_N and sdram_reset_n,
-- dma bus master (with many waitstates...)
ZPU_ADDR_FETCH => dma_addr_fetch,
ZPU_DATA_OUT => dma_write_data,
ZPU_FETCH => dma_fetch,
ZPU_32BIT_WRITE_ENABLE => dma_32bit_write_enable,
ZPU_16BIT_WRITE_ENABLE => dma_16bit_write_enable,
ZPU_8BIT_WRITE_ENABLE => dma_8bit_write_enable,
ZPU_READ_ENABLE => dma_read_enable,
ZPU_MEMORY_READY => dma_memory_ready,
ZPU_MEMORY_DATA => dma_memory_data,
-- rom bus master
-- data on next cycle after addr
ZPU_ADDR_ROM => zpu_addr_rom,
ZPU_ROM_DATA => zpu_rom_data,
-- spi master
-- Too painful to bit bang spi from zpu, so we have a hardware master in here
ZPU_SD_DAT0 => sd_dat0,
ZPU_SD_CLK => sd_clk,
ZPU_SD_CMD => sd_cmd,
ZPU_SD_DAT3 => sd_dat3,
-- SIO
-- Ditto for speaking to Atari, we have a built in Pokey
ZPU_POKEY_ENABLE => zpu_pokey_enable,
ZPU_SIO_TXD => zpu_sio_txd,
ZPU_SIO_RXD => zpu_sio_rxd,
ZPU_SIO_COMMAND => zpu_sio_command,
-- external control
-- switches etc. sector DMA blah blah.
ZPU_IN1 => X"000"&
"00"&ps2_keys(16#76#)&ps2_keys(16#5A#)&ps2_keys(16#174#)&ps2_keys(16#16B#)&ps2_keys(16#172#)&ps2_keys(16#175#)& -- (esc)FLRDU
FKEYS,
ZPU_IN2 => X"00000000",
ZPU_IN3 => X"00000000",
ZPU_IN4 => X"00000000",
-- ouputs - e.g. Atari system control, halt, throttle, rom select
ZPU_OUT1 => zpu_out1,
ZPU_OUT2 => zpu_out2,
ZPU_OUT3 => zpu_out3,
ZPU_OUT4 => zpu_out4
);
pause_atari <= zpu_out1(0);
reset_atari <= zpu_out1(1);
speed_6502 <= zpu_out1(7 downto 2);
ram_select <= zpu_out1(10 downto 8);
emulated_cartridge_select <= zpu_out1(22 downto 17);
freezer_enable <= zpu_out1(25);
zpu_rom1: entity work.zpu_rom
port map(
clock => clk,
address => zpu_addr_rom(13 downto 2),
q => zpu_rom_data
);
enable_179_clock_div_zpu_pokey : entity work.enable_divider
generic map (COUNT=>32) -- cycle_length
port map(clk=>clk,reset_n=>reset_n,enable_in=>'1',enable_out=>zpu_pokey_enable);
dac_left : hq_dac
port map
(
reset => not(reset_n),
clk => clk,
clk_ena => '1',
pcm_in => AUDIO_L_PCM&"0000",
dac_out => AUDIO_LEFT
);
dac_right : hq_dac
port map
(
reset => not(reset_n),
clk => clk,
clk_ena => '1',
pcm_in => AUDIO_R_PCM&"0000",
dac_out => AUDIO_RIGHT
);
END vhdl;
eclaireXL/build.sh
#!/usr/bin/perl -w
use strict;
my $wanted_variant = shift @ARGV;
my $name="eclaireXL";
#variants...
my $PAL = 1;
my $NTSC = 0;
my $RGB = 1; # i.e. not scandoubled
my $VGA = 2;
#Added like this to the generated qsf
#set_parameter -name TV 1
my %variants =
(
# "PAL" =>
# {
# "TV" => $PAL
# },
# "NTSC" =>
# {
# "TV" => $NTSC
# },
"BOTH" =>
{
"TV" => 2,
"GPIO" => 1
},
"PRIVATE" =>
{
"TV" => 2,
"GPIO" => 2
}
);
if (not defined $wanted_variant or (not exists $variants{$wanted_variant} and $wanted_variant ne "ALL"))
{
die "Provide variant of ALL or ".join ",",sort keys %variants;
}
foreach my $variant (sort keys %variants)
{
next if ($wanted_variant ne $variant and $wanted_variant ne "ALL");
print "Building $variant of $name\n";
my $dir = "build_$variant";
`rm -rf $dir`;
mkdir $dir;
`cp atari800core_eclaireXL.vhd $dir`;
`cp *pll*.* $dir`;
`cp *.v $dir`;
`cp *.vhd* $dir`;
`cp atari800core*.sdc $dir`;
`mkdir $dir/common`;
`mkdir $dir/common/a8core`;
`mkdir $dir/common/components`;
`mkdir $dir/common/zpu`;
`cp ../common/a8core/* ./$dir/common/a8core`;
`cp ../common/components/* ./$dir/common/components`;
`cp ../common/zpu/* ./$dir/common/zpu`;
chdir $dir;
`../makeqsf ../atari800core_eclaireXL.qsf ./common/a8core ./common/components ./common/zpu`;
`cat ../atari800core_eclaireXL.qsf_$variant >> atari800core_eclaireXL.qsf`;
foreach my $key (sort keys %{$variants{$variant}})
{
my $val = $variants{$variant}->{$key};
`echo set_parameter -name $key $val >> atari800core_eclaireXL.qsf`;
}
# `quartus_sh --flow compile atari800core > build.log 2> build.err`;
#
# `quartus_cpf --convert ../output_file.cof`;
chdir "..";
}
eclaireXL/gpio.vhd
---------------------------------------------------------------------------
-- (c) 2013 mark watson
-- I am happy for anyone to use this for non-commercial use.
-- If my vhdl files are used commercially or otherwise sold,
-- please contact me for explicit permission at scrameta (gmail).
-- This applies for source and binary form and derived works.
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity gpio is
generic
(
cartridge_cycle_length : in integer := 32
);
port
(
clk : in std_logic;
reset_n : in std_logic;
gpio_enable : in std_logic;
-- pia
porta_in : out std_logic_vector(7 downto 0);
porta_out : in std_logic_vector(7 downto 0);
porta_output : in std_logic_vector(7 downto 0);
CA2_DIR_OUT : IN std_logic;
CA2_OUT : IN std_logic;
CA2_IN : OUT STD_LOGIC;
CB2_DIR_OUT : IN std_logic;
CB2_OUT : IN std_logic;
CB2_IN : OUT STD_LOGIC;
-- gtia
trig_in : out std_logic_vector(3 downto 0);
-- antic
lightpen : out std_logic;
-- pokey
pot_reset : in std_logic;
pot_in : out std_logic_vector(7 downto 0);
keyboard_scan : in std_logic_vector(5 downto 0);
keyboard_response : out std_logic_vector(1 downto 0);
SIO_IN : OUT STD_LOGIC;
SIO_OUT : IN STD_LOGIC;
-- cartridge
enable_179_early : in std_logic;
pbi_addr_out : in std_logic_vector(15 downto 0);
pbi_write_enable : in std_logic;
cart_data_read : out std_logic_vector(7 downto 0);
cart_request : in std_logic;
cart_complete : out std_logic;
cart_data_write : in std_logic_vector(7 downto 0);
rd4 : out std_logic;
rd5 : out std_logic;
s4_n : in std_logic;
s5_n : in std_logic;
cctl_n : in std_logic;
-- gpio connections
GPIO_0_IN : in std_logic_vector(35 downto 0);
GPIO_0_OUT : out std_logic_vector(35 downto 0);
GPIO_0_DIR_OUT : out std_logic_vector(35 downto 0);
GPIO_1_IN : in std_logic_vector(35 downto 0);
GPIO_1_OUT : out std_logic_vector(35 downto 0);
GPIO_1_DIR_OUT : out std_logic_vector(35 downto 0)
);
end gpio;
architecture vhdl of gpio is
component synchronizer IS
PORT
(
CLK : IN STD_LOGIC;
RAW : IN STD_LOGIC;
SYNC : OUT STD_LOGIC
);
END component;
signal pot_in_async : std_logic_vector(7 downto 0);
signal porta_in_async : std_logic_vector(7 downto 0);
signal trig_in_async : std_logic_vector(3 downto 0);
signal trig_in_sync : std_logic_vector(3 downto 0);
signal bus_data_in : std_logic_vector(7 downto 0);
signal bus_data_out : std_logic_vector(7 downto 0);
signal bus_data_oe : std_logic;
signal bus_addr_out : std_logic_vector(15 downto 0);
signal bus_addr_oe : std_logic;
signal bus_write_n : std_logic;
signal bus_s4_n : std_logic;
signal bus_s5_n : std_logic;
signal bus_cctl_n : std_logic;
signal bus_control_oe : std_logic;
signal phi2 : std_logic;
signal rd4_async : std_logic;
signal rd5_async : std_logic;
signal keyboard_response_async : std_logic_vector(1 downto 0);
signal keyboard_response_gpio : std_logic_vector(1 downto 0);
signal porta_in_gpio : std_logic_vector(7 downto 0);
begin
-- OUTPUTS TO GPIO
-- unused
GPIO_1_DIR_OUT(18 downto 8) <= (others=>'0');
GPIO_1_OUT(18 downto 8) <= (others=>'0');
-- sio
GPIO_0_DIR_OUT(0) <= CA2_dir_out;
GPIO_0_OUT(0) <= CA2_out;
GPIO_0_DIR_OUT(1) <= CB2_dir_out;
GPIO_0_OUT(1) <= CB2_out;
GPIO_0_DIR_OUT(2) <= '1';
GPIO_0_OUT(2) <= SIO_OUT;
GPIO_0_DIR_OUT(3) <= '0';
GPIO_0_OUT(3) <= '0';
GPIO_0_DIR_OUT(4) <= 'Z';
GPIO_0_OUT(4) <= '0'; -- zpu output for logic analyzer
CA2_in <= GPIO_0_IN(0);
CB2_in <= GPIO_0_IN(1);
SIO_IN <= GPIO_0_IN(3);
-- sticks
GPIO_1_OUT(35 downto 19) <= (others=>'0');
GPIO_1_DIR_OUT(35) <= '0'; -- trig 0
GPIO_1_DIR_OUT(34) <= gpio_enable and porta_output(0) and not(porta_out(0)); -- stick 0
GPIO_1_DIR_OUT(33) <= '0';
GPIO_1_DIR_OUT(32) <= gpio_enable and porta_output(1) and not(porta_out(1)); -- stick 0
GPIO_1_DIR_OUT(31) <= '0';
GPIO_1_DIR_OUT(30) <= gpio_enable and porta_output(2) and not(porta_out(2)); -- stick 0
GPIO_1_DIR_OUT(29) <= gpio_enable and pot_reset;
GPIO_1_DIR_OUT(28) <= gpio_enable and porta_output(3) and not(porta_out(3)); -- stick 0
GPIO_1_DIR_OUT(27) <= gpio_enable and pot_reset;
GPIO_1_DIR_OUT(26) <= gpio_enable and pot_reset;
GPIO_1_DIR_OUT(25) <= '0'; -- trig 1
GPIO_1_DIR_OUT(24) <= gpio_enable and porta_output(4) and not(porta_out(4)); -- stick 1
GPIO_1_DIR_OUT(23) <= gpio_enable and porta_output(7) and not(porta_out(7)); -- stick 1
GPIO_1_DIR_OUT(22) <= gpio_enable and porta_output(5) and not(porta_out(5)); -- stick 1
GPIO_1_DIR_OUT(21) <= gpio_enable and pot_reset;
GPIO_1_DIR_OUT(20) <= gpio_enable and porta_output(6) and not(porta_out(6)); -- stick 1
GPIO_1_DIR_OUT(19 downto 8) <= (others=>'0');
-- keyboard
GPIO_1_OUT(7 downto 0) <= (others=>'0');
GPIO_1_DIR_OUT(7) <= '0'; -- keyboard response 2
GPIO_1_DIR_OUT(6) <= '0'; -- keyboard response 1
GPIO_1_DIR_OUT(5) <= gpio_enable and not(keyboard_scan(5)); -- keyboard scan 5
GPIO_1_DIR_OUT(4) <= gpio_enable and not(keyboard_scan(4)); -- keyboard scan 4
GPIO_1_DIR_OUT(3) <= gpio_enable and not(keyboard_scan(3)); -- keyboard scan 3
GPIO_1_DIR_OUT(2) <= gpio_enable and not(keyboard_scan(2)); -- keyboard scan 2
GPIO_1_DIR_OUT(1) <= gpio_enable and not(keyboard_scan(1)); -- keyboard scan 1
GPIO_1_DIR_OUT(0) <= gpio_enable and not(keyboard_scan(0)); -- keyboard scan 0
-- cart
GPIO_0_DIR_OUT(35) <= '1';
GPIO_0_OUT(35) <= phi2;
GPIO_0_DIR_OUT(34) <= gpio_enable;
GPIO_0_OUT(34) <= bus_write_n;
GPIO_0_DIR_OUT(33) <= gpio_enable and bus_addr_oe;
GPIO_0_OUT(33) <= bus_addr_out(10);
GPIO_0_DIR_OUT(32) <= gpio_enable and bus_addr_oe;
GPIO_0_OUT(32) <= bus_addr_out(11);
GPIO_0_DIR_OUT(31) <= gpio_enable and bus_data_oe; -- d7
GPIO_0_OUT(31) <= bus_data_out(7); -- d7
GPIO_0_DIR_OUT(30) <= gpio_enable and bus_data_oe; -- d3
GPIO_0_OUT(30) <= bus_data_out(3); -- d3
GPIO_0_DIR_OUT(29) <= gpio_enable and bus_addr_oe;
GPIO_0_OUT(29) <= bus_addr_out(12);
GPIO_0_DIR_OUT(28) <= gpio_enable and bus_addr_oe;
GPIO_0_OUT(28) <= bus_addr_out(9);
GPIO_0_DIR_OUT(27) <= gpio_enable and bus_addr_oe;
GPIO_0_OUT(27) <= bus_addr_out(8);
GPIO_0_DIR_OUT(26) <= gpio_enable and bus_addr_oe;
GPIO_0_OUT(26) <= bus_addr_out(7);
GPIO_0_DIR_OUT(25) <= gpio_enable and bus_addr_oe;
GPIO_0_OUT(25) <= bus_addr_out(6);
GPIO_0_DIR_OUT(24) <= gpio_enable and bus_addr_oe;
GPIO_0_OUT(24) <= bus_addr_out(5);
GPIO_0_DIR_OUT(23) <= gpio_enable and bus_addr_oe;
GPIO_0_OUT(23) <= bus_addr_out(4);
GPIO_0_DIR_OUT(22) <= '0'; -- RD4 rom present
GPIO_0_OUT(22) <= '0'; -- RD4 rom present
GPIO_0_DIR_OUT(21) <= gpio_enable and bus_control_oe;
GPIO_0_OUT(21) <= bus_s4_n;
GPIO_0_DIR_OUT(20) <= gpio_enable and bus_addr_oe;
GPIO_0_OUT(20) <= bus_addr_out(3);
GPIO_0_DIR_OUT(19) <= gpio_enable and bus_addr_oe;
GPIO_0_OUT(19) <= bus_addr_out(2);
GPIO_0_DIR_OUT(18) <= gpio_enable and bus_addr_oe;
GPIO_0_OUT(18) <= bus_addr_out(1);
GPIO_0_DIR_OUT(17) <= gpio_enable and bus_addr_oe;
GPIO_0_OUT(17) <= bus_addr_out(0);
GPIO_0_DIR_OUT(16) <= gpio_enable and bus_data_oe; -- d4
GPIO_0_OUT(16) <= bus_data_out(4); -- d4
GPIO_0_DIR_OUT(15) <= gpio_enable and bus_data_oe; -- d5
GPIO_0_OUT(15) <= bus_data_out(5); -- d5
GPIO_0_DIR_OUT(14) <= gpio_enable and bus_data_oe; -- d2
GPIO_0_OUT(14) <= bus_data_out(2); -- d2
GPIO_0_DIR_OUT(13) <= gpio_enable and bus_data_oe; -- d1
GPIO_0_OUT(13) <= bus_data_out(1); -- d1
GPIO_0_DIR_OUT(12) <= gpio_enable and bus_data_oe; -- d0
GPIO_0_OUT(12) <= bus_data_out(0); -- d0
GPIO_0_DIR_OUT(11) <= gpio_enable and bus_data_oe; -- d6
GPIO_0_OUT(11) <= bus_data_out(6); -- d6
GPIO_0_DIR_OUT(10) <= gpio_enable and bus_control_oe;
GPIO_0_OUT(10) <= bus_s5_n;
GPIO_0_DIR_OUT(9) <= '0'; -- RD5 rom present
GPIO_0_OUT(9) <= '0'; -- RD5 rom present
GPIO_0_DIR_OUT(8) <= gpio_enable and bus_control_oe; -- cart control
GPIO_0_OUT(8) <= bus_cctl_n; -- cart control
-- PBI: A13-A15
GPIO_0_DIR_OUT(7) <= gpio_enable and bus_addr_oe;
GPIO_0_OUT(7) <= bus_addr_out(15);
GPIO_0_DIR_OUT(6) <= gpio_enable and bus_addr_oe;
GPIO_0_OUT(6) <= bus_addr_out(14);
GPIO_0_DIR_OUT(5) <= gpio_enable and bus_addr_oe;
GPIO_0_OUT(5) <= bus_addr_out(13);
-- INPUTS FROM GPIO
-- sticks
pot_in_async <=
gpio_enable&gpio_enable&gpio_enable&gpio_enable&gpio_enable&gpio_enable&gpio_enable&gpio_enable and
("0000"&
GPIO_1_IN(27)&GPIO_1_IN(21)& -- 32/24
GPIO_1_IN(26)&GPIO_1_IN(29)); -- 31/34
pot_in0_synchronizer : synchronizer
port map (clk=>clk, raw=>pot_in_async(0), sync=>pot_in(0));
pot_in1_synchronizer : synchronizer
port map (clk=>clk, raw=>pot_in_async(1), sync=>pot_in(1));
pot_in2_synchronizer : synchronizer
port map (clk=>clk, raw=>pot_in_async(2), sync=>pot_in(2));
pot_in3_synchronizer : synchronizer
port map (clk=>clk, raw=>pot_in_async(3), sync=>pot_in(3));
pot_in4_synchronizer : synchronizer
port map (clk=>clk, raw=>pot_in_async(4), sync=>pot_in(4));
pot_in5_synchronizer : synchronizer
port map (clk=>clk, raw=>pot_in_async(5), sync=>pot_in(5));
pot_in6_synchronizer : synchronizer
port map (clk=>clk, raw=>pot_in_async(6), sync=>pot_in(6));
pot_in7_synchronizer : synchronizer
port map (clk=>clk, raw=>pot_in_async(7), sync=>pot_in(7));
-- porta_in_async <=
-- not(gpio_enable&gpio_enable&gpio_enable&gpio_enable&gpio_enable&gpio_enable&gpio_enable&gpio_enable) or
-- GPIO_1_IN(23)&GPIO_1_IN(20)&GPIO_1_IN(22)&GPIO_1_IN(24)& -- 27/25/23/26
-- GPIO_1_IN(28)&GPIO_1_IN(30)&GPIO_1_IN(32)&GPIO_1_IN(34); -- 39/37/35/33
porta_in_async <=
GPIO_1_IN(23)&GPIO_1_IN(20)&GPIO_1_IN(22)&GPIO_1_IN(24)& -- 27/25/23/26
GPIO_1_IN(28)&GPIO_1_IN(30)&GPIO_1_IN(32)&GPIO_1_IN(34); -- 39/37/35/33
porta_in0_synchronizer : synchronizer
port map (clk=>clk, raw=>porta_in_async(0), sync=>porta_in_gpio(0));
porta_in1_synchronizer : synchronizer
port map (clk=>clk, raw=>porta_in_async(1), sync=>porta_in_gpio(1));
porta_in2_synchronizer : synchronizer
port map (clk=>clk, raw=>porta_in_async(2), sync=>porta_in_gpio(2));
porta_in3_synchronizer : synchronizer
port map (clk=>clk, raw=>porta_in_async(3), sync=>porta_in_gpio(3));
porta_in4_synchronizer : synchronizer
port map (clk=>clk, raw=>porta_in_async(4), sync=>porta_in_gpio(4));
porta_in5_synchronizer : synchronizer
port map (clk=>clk, raw=>porta_in_async(5), sync=>porta_in_gpio(5));
porta_in6_synchronizer : synchronizer
port map (clk=>clk, raw=>porta_in_async(6), sync=>porta_in_gpio(6));
porta_in7_synchronizer : synchronizer
port map (clk=>clk, raw=>porta_in_async(7), sync=>porta_in_gpio(7));
porta_in(7 downto 4) <= porta_in_gpio(7 downto 4);
porta_in(3 downto 0) <= porta_in_gpio(3 downto 0);
trig_in_async <= (not(gpio_enable&gpio_enable&"11") or (rd5_async&"1"&GPIO_1_IN(25)&GPIO_1_IN(35))); -- 28/40
trig_in0_synchronizer : synchronizer
port map (clk=>clk, raw=>trig_in_async(0), sync=>trig_in_sync(0));
trig_in1_synchronizer : synchronizer
port map (clk=>clk, raw=>trig_in_async(1), sync=>trig_in_sync(1));
trig_in2_synchronizer : synchronizer
port map (clk=>clk, raw=>trig_in_async(2), sync=>trig_in_sync(2));
trig_in3_synchronizer : synchronizer
port map (clk=>clk, raw=>trig_in_async(3), sync=>trig_in_sync(3));
trig_in <= trig_in_sync;
lightpen <= trig_in_sync(0) and trig_in_sync(1); -- either joystick button
-- keyboard
keyboard_response_async <= not(gpio_enable&gpio_enable) or (GPIO_1_IN(7)& GPIO_1_IN(6));
keyboard_response1_synchronizer : synchronizer
port map (clk=>clk, raw=>keyboard_response_async(0), sync=>keyboard_response_gpio(0));
keyboard_response2_synchronizer : synchronizer
port map (clk=>clk, raw=>keyboard_response_async(1), sync=>keyboard_response_gpio(1));
keyboard_response <= keyboard_response_gpio;
-- cartridge
-- 1(21). S4' Chip Select--$8000 to $9FFF A(22). RD4 ROM present--$8000 to $9FFF
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