Revision 362
Added by markw over 10 years ago
| common/a8core/pokey.vhdl | ||
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end process;
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-- serial port output
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serout_sync_reset <= serial_reset;
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-- urghhh (TODO: If timers are cleared with stimer_write, some clocks are still triggering. This workaround fixes the acid test. Investigate the proper fix)
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serout_sync_reset <= serial_reset or stimer_write_delayed;
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serout_clock_delay : delay_line
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generic map (count=>2)
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port map (clk=>clk, sync_reset=>serout_sync_reset,data_in=>serout_enable, enable=>enable_179, reset_n=>reset_n, data_out=>serout_enable_delayed);
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Also available in: Unified diff
Reverted the change that broke acid