Revision 359
Added by markw over 10 years ago
| common/a8core/atari800core.vhd | ||
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     		-- SIO
 
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     		SIO_RXD : in std_logic;
 
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     		SIO_TXD : out std_logic;
 
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     		SIO_CLOCKIN : in std_logic :='1';
 
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     		SIO_CLOCKOUT : out std_logic;
 
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     		-- SIO_COMMAND_TX - see PIA PB2
 
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     		-- TODO CLOCK IN/CLOCK OUT (unused almost everywhere...)
 
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| ... | ... | |
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     		 SIO_IN1 => SIO_RXD,
 
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     		 SIO_IN2 => '1',
 
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     		 SIO_IN3 => '1',
 
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     		 SIO_CLOCKIN => SIO_CLOCKIN,
 
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     		 ADDR => PBI_ADDR_INT(3 DOWNTO 0),
 
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     		 DATA_IN => WRITE_DATA(7 DOWNTO 0),
 
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     		 keyboard_response => KEYBOARD_RESPONSE,
 
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| ... | ... | |
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     		 SIO_OUT1 => SIO_TXD,
 
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     		 SIO_OUT2 => open,
 
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     		 SIO_OUT3 => open,
 
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     		 SIO_CLOCKOUT => SIO_CLOCKOUT,
 
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     		 POT_RESET => POT_RESET,
 
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     		 CHANNEL_0_OUT => POKEY1_CHANNEL0,
 
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     		 CHANNEL_1_OUT => POKEY1_CHANNEL1,
 
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| common/a8core/pokey.vhdl | ||
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     	SIO_OUT2 : OUT std_logic;
 
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     	SIO_OUT3 : OUT std_logic;
 
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     	SIO_CLOCK : INOUT std_logic; -- TODO, should not use internally
 
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     	SIO_CLOCKIN : IN std_logic := '1';
 
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     	SIO_CLOCKOUT : OUT std_logic;
 
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     	POT_RESET : out std_logic
 
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     );
 
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| ... | ... | |
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     	end process;
 
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     	-- serial clocks
 
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     	process(sio_clock,skctl_reg,clock_reg,clock_sync_reg,audf1_pulse,audf2_pulse,audf3_pulse)
 
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     	process(sio_clockin,skctl_reg,clock_reg,clock_sync_reg,audf1_pulse,audf2_pulse,audf3_pulse)
 
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     	begin
 
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     		clock_next <= sio_clock;
 
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     		clock_next <= sio_clockin;
 
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     		clock_sync_next <= clock_reg;
 
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     		serout_enable <= '0';
 
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| ... | ... | |
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     	sio_out2 <= sio_out_reg;	
 
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     	sio_out3 <= sio_out_reg;	
 
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     	sio_clock <= audf3_pulse when clock_input='0' else 'Z';
 
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     	sio_clockout <= audf3_pulse when clock_input='0' else 'Z';
 
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     	pot_reset <= pot_reset_reg;
 
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| de1/atari800core_de1.vhd | ||
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     	SIGNAL GPIO_SIO_RXD : std_logic;
 
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     	SIGNAL SIO_CLOCKOUT : std_logic;
 
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     	SIGNAL SIO_CLOCKIN : std_logic;
 
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     	-- VIDEO
 
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     	signal VGA_VS_RAW : std_logic;
 
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     	signal VGA_HS_RAW : std_logic;
 
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| ... | ... | |
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     		 );
 
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     -- PIA mapping
 
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     CA1_IN <= '1';
 
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     CB1_IN <= '1';
 
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     CA2_IN <= CA2_OUT when CA2_DIR_OUT='1' else '1';
 
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     CB2_IN <= CB2_OUT when CB2_DIR_OUT='1' else '1';
 
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     SIO_COMMAND <= CB2_OUT;
 
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     --PORTA_IN <= ((JOY2_n(3)&JOY2_n(2)&JOY2_n(1)&JOY2_n(0)&JOY1_n(3)&JOY1_n(2)&JOY1_n(1)&JOY1_n(0)) and not (porta_dir_out)) or (porta_dir_out and porta_out);
 
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     --PORTA_IN <= (not (porta_dir_out)) or (porta_dir_out and porta_out);
 
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| ... | ... | |
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     		 SIO_IN => GPIO_SIO_RXD,
 
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     		 SIO_OUT => SIO_TXD
 
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     		 );
 
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     	CA1_IN <= '1';
 
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     	CB1_IN <= '1';
 
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     	CA2_IN <= CA2_OUT when CA2_DIR_OUT='1' else '1';
 
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     	CB2_IN <= CB2_OUT when CB2_DIR_OUT='1' else '1';
 
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     end generate gen_old_gpio;
 
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     gen_new_gpio : if gpio=2 generate
 
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| ... | ... | |
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     		 trig_in => TRIGGERS,
 
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     		 CA2_DIR_OUT => CA2_DIR_OUT,
 
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     		 CA2_OUT => CA2_OUT,
 
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     		 CA2_IN => open,
 
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     		 CA2_IN => CA2_IN,
 
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     		 CB2_DIR_OUT => CB2_DIR_OUT,
 
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     		 CB2_OUT => CB2_OUT,
 
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     		 CB2_IN => open,
 
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     		 CB2_IN => CB2_IN,
 
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     		 SIO_IN => GPIO_SIO_RXD,
 
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     		 SIO_OUT => SIO_TXD
 
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     		 SIO_OUT => SIO_TXD,
 
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     		 SIO_CLOCKIN => SIO_CLOCKIN,
 
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     		 SIO_CLOCKOUT => SIO_CLOCKOUT
 
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     		 );
 
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     end generate gen_new_gpio;
 
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| ... | ... | |
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     zpu_sio_command <= SIO_COMMAND;
 
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     zpu_sio_rxd <= SIO_TXD;
 
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     SIO_RXD <= zpu_sio_txd and UART_RXD;
 
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     SIO_RXD <= zpu_sio_txd and UART_RXD and GPIO_SIO_RXD;
 
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     -- VIDEO
 
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     --VGA_HS <= not(VGA_HS_RAW xor VGA_VS_RAW);
 
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| ... | ... | |
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     		SIO_RXD => SIO_RXD,
 
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     		SIO_TXD => SIO_TXD,
 
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     		SIO_CLOCKIN => SIO_CLOCKIN,
 
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     		SIO_CLOCKOUT => SIO_CLOCKOUT,
 
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     		CONSOL_OPTION => CONSOL_OPTION,
 
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     		CONSOL_SELECT => CONSOL_SELECT,
 
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     		CONSOL_START=> CONSOL_START,
 
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| de1/gpiov2.vhd | ||
|---|---|---|
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     	porta_in : out std_logic_vector(7 downto 0);
 
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     	porta_out : in std_logic_vector(7 downto 0);
 
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     	porta_output : in std_logic_vector(7 downto 0);
 
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     	CA1_IN : OUT STD_LOGIC;
 
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     	CA2_DIR_OUT : IN std_logic;
 
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     	CA2_OUT : IN std_logic;
 
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     	CA2_IN : OUT STD_LOGIC;
 
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     	CB1_IN : OUT STD_LOGIC;
 
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     	CB2_DIR_OUT : IN std_logic;
 
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     	CB2_OUT : IN std_logic;
 
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     	CB2_IN : OUT STD_LOGIC;
 
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| ... | ... | |
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     	keyboard_response : out std_logic_vector(1 downto 0);
 
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     	SIO_IN : OUT STD_LOGIC;
 
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     	SIO_OUT : IN STD_LOGIC;
 
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     	SIO_CLOCKIN : OUT STD_LOGIC;
 
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     	SIO_CLOCKOUT : IN STD_LOGIC;
 
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     	-- cartridge
 
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     	enable_179_early : in std_logic;
 
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| ... | ... | |
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     begin	
 
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     -- OUTPUTS TO GPIO
 
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     	-- unused
 
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     	GPIO_0_DIR_OUT(35 downto 4) <= (others=>'0');
 
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     	GPIO_0_OUT(35 downto 4) <= (others=>'0');
 
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     	--GPIO_0_DIR_OUT(35 downto 4) <= (others=>'0');
 
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     	GPIO_0_OUT(35 downto 0) <= (others=>'0');
 
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     	-- sio
 
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     	GPIO_0_DIR_OUT(0) <= CA2_dir_out;
 
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     	GPIO_0_OUT(0) <= CA2_out;
 
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     	GPIO_0_DIR_OUT(1) <= CB2_dir_out;
 
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     	GPIO_0_OUT(1) <= CB2_out;
 
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     	GPIO_0_DIR_OUT(2) <= '1';
 
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     	GPIO_0_OUT(2) <= SIO_OUT;
 
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     	GPIO_0_DIR_OUT(3) <= '0';
 
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     	GPIO_0_OUT(3) <= '0';
 
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     	--CB1=SIO_IRQ
 
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     	--CB2=SIO_COMMAND
 
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     	--CA1=SIO_PROCEED
 
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     	--CA2=SIO_MOTOR_RAW
 
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     	GPIO_0_DIR_OUT(0) <= '0';
 
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     	GPIO_0_DIR_OUT(1) <= CB2_dir_out and not(CB2_OUT) and gpio_enable;
 
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     	GPIO_0_DIR_OUT(2) <= '0';
 
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     	GPIO_0_DIR_OUT(3) <= CA2_dir_out and not(CA2_OUT) and gpio_enable;
 
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     	GPIO_0_DIR_OUT(4) <= not(SIO_OUT) and gpio_enable;
 
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     	GPIO_0_DIR_OUT(5) <= '0';
 
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     	GPIO_0_DIR_OUT(6) <= not(SIO_CLOCKOUT) and gpio_enable;
 
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     	GPIO_0_DIR_OUT(7) <= '0';
 
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     	GPIO_0_DIR_OUT(4) <= 'Z';
 
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     	GPIO_0_OUT(4) <= '0'; -- zpu output for logic analyzer
 
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     	CA2_in <= GPIO_0_IN(0);
 
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     	CB1_in <= GPIO_0_IN(0);
 
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     	CB2_in <= GPIO_0_IN(1);
 
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     	SIO_IN <= GPIO_0_IN(3);
 
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     	CA1_in <= GPIO_0_IN(2);
 
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     	CA2_in <= GPIO_0_IN(3);
 
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     	SIO_IN <= GPIO_0_IN(5);
 
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     	SIO_CLOCKIN <= GPIO_0_IN(7);
 
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     	-- sticks
 
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     	--GPIO_0_OUT(35 downto 19) <= (others=>'0');
 
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     	--GPIO_0_DIR_OUT(35) <= '0'; -- trig 0
 
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     	--GPIO_0_DIR_OUT(34) <= gpio_enable and porta_output(0) and not(porta_out(0)); -- stick 0
 
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     	--GPIO_0_DIR_OUT(33) <= '0';
 
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     	--GPIO_0_DIR_OUT(32) <= gpio_enable and porta_output(1) and not(porta_out(1)); -- stick 0
 
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     	--GPIO_0_DIR_OUT(31) <= '0';
 
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     	--GPIO_0_DIR_OUT(30) <= gpio_enable and porta_output(2) and not(porta_out(2)); -- stick 0
 
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     	--GPIO_0_DIR_OUT(29) <= gpio_enable and pot_reset;
 
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     	--GPIO_0_DIR_OUT(28) <= gpio_enable and porta_output(3) and not(porta_out(3)); -- stick 0
 
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     	--GPIO_0_DIR_OUT(27) <= gpio_enable and pot_reset;
 
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     	--GPIO_0_DIR_OUT(26) <= gpio_enable and pot_reset;
 
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     	--GPIO_0_DIR_OUT(25) <= '0'; -- trig 1
 
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     	--GPIO_0_DIR_OUT(24) <= gpio_enable and porta_output(4) and not(porta_out(4)); -- stick 1
 
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     	--GPIO_0_DIR_OUT(23) <= gpio_enable and porta_output(7) and not(porta_out(7)); -- stick 1
 
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     	--GPIO_0_DIR_OUT(22) <= gpio_enable and porta_output(5) and not(porta_out(5)); -- stick 1
 
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     	--GPIO_0_DIR_OUT(21) <= gpio_enable and pot_reset;
 
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     	--GPIO_0_DIR_OUT(20) <= gpio_enable and porta_output(6) and not(porta_out(6)); -- stick 1
 
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     	--GPIO_0_DIR_OUT(19 downto 8) <= (others=>'0');
 
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     	-- PORTA7,6,5,4,TRIG1,POT3,2,1,0,PORTA3,2,1,0,TRIG0
 
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     	GPIO_0_DIR_OUT(8) <= gpio_enable and porta_output(7) and not(porta_out(7)); -- stick
 
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     	GPIO_0_DIR_OUT(9) <= gpio_enable and porta_output(6) and not(porta_out(6)); -- stick
 
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     	GPIO_0_DIR_OUT(10) <= gpio_enable and porta_output(5) and not(porta_out(5)); -- stick
 
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     	GPIO_0_DIR_OUT(11) <= gpio_enable and porta_output(4) and not(porta_out(4)); -- stick
 
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     	GPIO_0_DIR_OUT(17) <= gpio_enable and porta_output(3) and not(porta_out(3)); -- stick
 
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     	GPIO_0_DIR_OUT(18) <= gpio_enable and porta_output(2) and not(porta_out(2)); -- stick
 
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     	GPIO_0_DIR_OUT(19) <= gpio_enable and porta_output(1) and not(porta_out(1)); -- stick
 
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     	GPIO_0_DIR_OUT(20) <= gpio_enable and porta_output(0) and not(porta_out(0)); -- stick
 
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     	GPIO_0_DIR_OUT(12) <= '0'; -- trig
 
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     	GPIO_0_DIR_OUT(21) <= '0'; -- trig
 
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     	GPIO_0_DIR_OUT(13) <= gpio_enable and pot_reset;
 
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     	GPIO_0_DIR_OUT(14) <= gpio_enable and pot_reset;
 
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     	GPIO_0_DIR_OUT(15) <= gpio_enable and pot_reset;
 
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     	GPIO_0_DIR_OUT(16) <= gpio_enable and pot_reset;
 
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     	-- ext
 
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     	GPIO_0_DIR_OUT(22) <= '0';
 
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     	GPIO_0_DIR_OUT(23) <= '0';
 
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     	GPIO_0_DIR_OUT(24) <= '0';
 
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     	GPIO_0_DIR_OUT(25) <= '0';
 
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     	GPIO_0_DIR_OUT(26) <= '0';
 
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     	GPIO_0_DIR_OUT(27) <= '0';
 
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     	-- keyboard
 
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     	--GPIO_0_OUT(7 downto 0) <= (others=>'0');
 
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     	--GPIO_0_DIR_OUT(7) <= '0'; -- keyboard response 2
 
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     	--GPIO_0_DIR_OUT(6) <= '0'; -- keyboard response 1
 
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     	--GPIO_0_DIR_OUT(5) <= gpio_enable and not(keyboard_scan(5)); -- keyboard scan 5
 
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     	--GPIO_0_DIR_OUT(4) <= gpio_enable and not(keyboard_scan(4)); -- keyboard scan 4
 
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     	--GPIO_0_DIR_OUT(3) <= gpio_enable and not(keyboard_scan(3)); -- keyboard scan 3
 
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     	--GPIO_0_DIR_OUT(2) <= gpio_enable and not(keyboard_scan(2)); -- keyboard scan 2
 
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     	--GPIO_0_DIR_OUT(1) <= gpio_enable and not(keyboard_scan(1)); -- keyboard scan 1
 
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     	--GPIO_0_DIR_OUT(0) <= gpio_enable and not(keyboard_scan(0)); -- keyboard scan 0
 
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     	GPIO_0_DIR_OUT(28) <= gpio_enable and not(keyboard_scan(2)); -- keyboard scan 2
 
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     	GPIO_0_DIR_OUT(29) <= gpio_enable and not(keyboard_scan(1)); -- keyboard scan 1
 
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     	GPIO_0_DIR_OUT(30) <= gpio_enable and not(keyboard_scan(0)); -- keyboard scan 0
 
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     	GPIO_0_DIR_OUT(31) <= '0'; -- keyboard response 1
 
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     	GPIO_0_DIR_OUT(32) <= gpio_enable and not(keyboard_scan(5)); -- keyboard scan 5
 
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     	GPIO_0_DIR_OUT(33) <= gpio_enable and not(keyboard_scan(4)); -- keyboard scan 4
 
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     	GPIO_0_DIR_OUT(34) <= gpio_enable and not(keyboard_scan(3)); -- keyboard scan 3
 
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     	GPIO_0_DIR_OUT(35) <= '0'; -- keyboard response 2
 
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     	-- cart
 
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     	GPIO_1_DIR_OUT(0) <= gpio_enable and bus_control_oe; -- cart control
 
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| ... | ... | |
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     -- INPUTS FROM GPIO	
 
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     	-- sticks
 
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     --	pot_in_async <= 
 
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     --					gpio_enable&gpio_enable&gpio_enable&gpio_enable&gpio_enable&gpio_enable&gpio_enable&gpio_enable and 
 
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     --					("0000"&
 
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     --					GPIO_1_IN(27)&GPIO_1_IN(21)& -- 32/24
 
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     --					GPIO_1_IN(26)&GPIO_1_IN(29)); -- 31/34
 
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     --	pot_in0_synchronizer : synchronizer
 
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     --		port map (clk=>clk, raw=>pot_in_async(0), sync=>pot_in(0));						
 
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     --	pot_in1_synchronizer : synchronizer
 
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     --		port map (clk=>clk, raw=>pot_in_async(1), sync=>pot_in(1));						
 
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     --	pot_in2_synchronizer : synchronizer
 
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     --		port map (clk=>clk, raw=>pot_in_async(2), sync=>pot_in(2));						
 
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     --	pot_in3_synchronizer : synchronizer
 
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     --		port map (clk=>clk, raw=>pot_in_async(3), sync=>pot_in(3));							
 
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     --	pot_in4_synchronizer : synchronizer
 
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     --		port map (clk=>clk, raw=>pot_in_async(4), sync=>pot_in(4));						
 
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     --	pot_in5_synchronizer : synchronizer
 
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     --		port map (clk=>clk, raw=>pot_in_async(5), sync=>pot_in(5));						
 
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     --	pot_in6_synchronizer : synchronizer
 
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     --		port map (clk=>clk, raw=>pot_in_async(6), sync=>pot_in(6));						
 
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     --	pot_in7_synchronizer : synchronizer
 
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     --		port map (clk=>clk, raw=>pot_in_async(7), sync=>pot_in(7));								
 
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     	pot_in(7 downto 0) <= (others=>'0');
 
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     	pot_in_async <= 
 
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     					gpio_enable&gpio_enable&gpio_enable&gpio_enable&gpio_enable&gpio_enable&gpio_enable&gpio_enable and 
 
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     					("0000"&
 
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     					GPIO_0_IN(13)&GPIO_0_IN(14)&
 
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     					GPIO_0_IN(15)&GPIO_0_IN(16));
 
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     	pot_in0_synchronizer : synchronizer
 
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     		port map (clk=>clk, raw=>pot_in_async(0), sync=>pot_in(0));						
 
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     	pot_in1_synchronizer : synchronizer
 
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     		port map (clk=>clk, raw=>pot_in_async(1), sync=>pot_in(1));						
 
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     	pot_in2_synchronizer : synchronizer
 
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     		port map (clk=>clk, raw=>pot_in_async(2), sync=>pot_in(2));						
 
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     	pot_in3_synchronizer : synchronizer
 
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     		port map (clk=>clk, raw=>pot_in_async(3), sync=>pot_in(3));							
 
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     	pot_in4_synchronizer : synchronizer
 
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| 
     		port map (clk=>clk, raw=>pot_in_async(4), sync=>pot_in(4));						
 
   | 
||
| 
     	pot_in5_synchronizer : synchronizer
 
   | 
||
| 
     		port map (clk=>clk, raw=>pot_in_async(5), sync=>pot_in(5));						
 
   | 
||
| 
     	pot_in6_synchronizer : synchronizer
 
   | 
||
| 
     		port map (clk=>clk, raw=>pot_in_async(6), sync=>pot_in(6));						
 
   | 
||
| 
     	pot_in7_synchronizer : synchronizer
 
   | 
||
| 
     		port map (clk=>clk, raw=>pot_in_async(7), sync=>pot_in(7));								
 
   | 
||
| 
     	porta_in_async <= 
 
   | 
||
| 
     					GPIO_0_IN(8)&GPIO_0_IN(9)&GPIO_0_IN(10)&GPIO_0_IN(11)& 
 
   | 
||
| 
     					GPIO_0_IN(17)&GPIO_0_IN(18)&GPIO_0_IN(19)&GPIO_0_IN(20); 
 
   | 
||
| 
     	porta_in0_synchronizer : synchronizer
 
   | 
||
| 
     		port map (clk=>clk, raw=>porta_in_async(0), sync=>porta_in_gpio(0));						
 
   | 
||
| 
     	porta_in1_synchronizer : synchronizer
 
   | 
||
| 
     		port map (clk=>clk, raw=>porta_in_async(1), sync=>porta_in_gpio(1));						
 
   | 
||
| 
     	porta_in2_synchronizer : synchronizer
 
   | 
||
| 
     		port map (clk=>clk, raw=>porta_in_async(2), sync=>porta_in_gpio(2));						
 
   | 
||
| 
     	porta_in3_synchronizer : synchronizer
 
   | 
||
| 
     		port map (clk=>clk, raw=>porta_in_async(3), sync=>porta_in_gpio(3));						
 
   | 
||
| 
     	porta_in4_synchronizer : synchronizer
 
   | 
||
| 
     		port map (clk=>clk, raw=>porta_in_async(4), sync=>porta_in_gpio(4));						
 
   | 
||
| 
     	porta_in5_synchronizer : synchronizer
 
   | 
||
| 
     		port map (clk=>clk, raw=>porta_in_async(5), sync=>porta_in_gpio(5));						
 
   | 
||
| 
     	porta_in6_synchronizer : synchronizer
 
   | 
||
| 
     		port map (clk=>clk, raw=>porta_in_async(6), sync=>porta_in_gpio(6));						
 
   | 
||
| 
     	porta_in7_synchronizer : synchronizer
 
   | 
||
| 
     		port map (clk=>clk, raw=>porta_in_async(7), sync=>porta_in_gpio(7));
 
   | 
||
| 
     | 
||
| 
     --	porta_in_async <= 
 
   | 
||
| 
     --					GPIO_1_IN(23)&GPIO_1_IN(20)&GPIO_1_IN(22)&GPIO_1_IN(24)& -- 27/25/23/26
 
   | 
||
| 
     --					GPIO_1_IN(28)&GPIO_1_IN(30)&GPIO_1_IN(32)&GPIO_1_IN(34); -- 39/37/35/33					
 
   | 
||
| 
     --	porta_in0_synchronizer : synchronizer
 
   | 
||
| 
     --		port map (clk=>clk, raw=>porta_in_async(0), sync=>porta_in_gpio(0));						
 
   | 
||
| 
     --	porta_in1_synchronizer : synchronizer
 
   | 
||
| 
     --		port map (clk=>clk, raw=>porta_in_async(1), sync=>porta_in_gpio(1));						
 
   | 
||
| 
     --	porta_in2_synchronizer : synchronizer
 
   | 
||
| 
     --		port map (clk=>clk, raw=>porta_in_async(2), sync=>porta_in_gpio(2));						
 
   | 
||
| 
     --	porta_in3_synchronizer : synchronizer
 
   | 
||
| 
     --		port map (clk=>clk, raw=>porta_in_async(3), sync=>porta_in_gpio(3));						
 
   | 
||
| 
     --	porta_in4_synchronizer : synchronizer
 
   | 
||
| 
     --		port map (clk=>clk, raw=>porta_in_async(4), sync=>porta_in_gpio(4));						
 
   | 
||
| 
     --	porta_in5_synchronizer : synchronizer
 
   | 
||
| 
     --		port map (clk=>clk, raw=>porta_in_async(5), sync=>porta_in_gpio(5));						
 
   | 
||
| 
     --	porta_in6_synchronizer : synchronizer
 
   | 
||
| 
     --		port map (clk=>clk, raw=>porta_in_async(6), sync=>porta_in_gpio(6));						
 
   | 
||
| 
     --	porta_in7_synchronizer : synchronizer
 
   | 
||
| 
     --		port map (clk=>clk, raw=>porta_in_async(7), sync=>porta_in_gpio(7));
 
   | 
||
| 
     --		
 
   | 
||
| 
     --	porta_in(7 downto 4) <= porta_in_gpio(7 downto 4);
 
   | 
||
| 
     --	porta_in(3 downto 0) <= porta_in_gpio(3 downto 0);
 
   | 
||
| 
     	porta_in(7 downto 0) <= (others=>'1');
 
   | 
||
| 
     	porta_in(7 downto 0) <= porta_in_gpio(7 downto 0);
 
   | 
||
| 
     | 
||
| 
     --	trig_in_async <= (not(gpio_enable&gpio_enable&"11") or (rd5_async&"1"&GPIO_1_IN(25)&GPIO_1_IN(35)));	-- 28/40
 
   | 
||
| 
     	trig_in_async <= (not(gpio_enable&gpio_enable&"11") or (rd5_async&"111"));
 
   | 
||
| 
     	trig_in_async <= (not(gpio_enable&gpio_enable&"11") or (rd5_async&"1"&GPIO_0_IN(12)&GPIO_0_IN(21)));
 
   | 
||
| 
     	trig_in0_synchronizer : synchronizer
 
   | 
||
| 
     		port map (clk=>clk, raw=>trig_in_async(0), sync=>trig_in_sync(0));							
 
   | 
||
| 
     	trig_in1_synchronizer : synchronizer
 
   | 
||
| ... | ... | |
| 
     	lightpen <= trig_in_sync(0) and trig_in_sync(1); -- either joystick button				
 
   | 
||
| 
     | 
||
| 
     	-- keyboard
 
   | 
||
| 
     	--keyboard_response_async <= not(gpio_enable&gpio_enable) or (GPIO_1_IN(7)& GPIO_1_IN(6));
 
   | 
||
| 
     	keyboard_response_async <= "11";
 
   | 
||
| 
     	keyboard_response_async <= not(gpio_enable&gpio_enable) or (GPIO_0_IN(35)& GPIO_0_IN(31));
 
   | 
||
| 
     	keyboard_response1_synchronizer : synchronizer
 
   | 
||
| 
     		port map (clk=>clk, raw=>keyboard_response_async(0), sync=>keyboard_response_gpio(0));						
 
   | 
||
| 
     	keyboard_response2_synchronizer : synchronizer
 
   | 
||
Add breakout board support. Pass clockin/clockout to pokey (untested).