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Revision 35

Added by markw over 11 years ago

First version that boots with sdram

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mcc216/atari800core.qsf
set_global_assignment -name QIP_FILE pll.qip
set_global_assignment -name SDC_FILE atari800core.sdc
set_global_assignment -name VERILOG_FILE sdram_ctrl_3_ports.v
set_global_assignment -name VHDL_FILE atari800core_mcc.vhd
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
mcc216/atari800core_mcc.cmd
#onerror {resume}
# GAME
#=====================
#run 18871970 ns
#isim force add {/replay_tb/uut/tpp2/cpu/dd_s} 11111111 -radix bin -cancel 250 ns
#run 200 ms
mcc216/atari800core_mcc.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.numeric_std.all;
LIBRARY work;
......
PORT
(
FPGA_CLK : IN STD_LOGIC;
PS2K_CLK : IN STD_LOGIC;
PS2K_DAT : IN STD_LOGIC;
PS2M_CLK : IN STD_LOGIC;
......
);
end component;
COMPONENT sdram_ctrl
port
(
--//--------------------
--// Clocks and reset --
--//--------------------
--// Global reset
rst : in std_logic;
--// Controller clock
clk : in std_logic;
--// Sequencer cycles
seq_cyc : in std_logic_vector(11 downto 0);
--// Sequencer phase
seq_ph : in std_logic;
--// Refresh cycle
refr_cyc : in std_logic;
--//------------------------
--// Access port #1 (CPU) --
--//------------------------
--// RAM select
ap1_ram_sel : in std_logic;
--// Address bus
ap1_address : in std_logic_vector(23 downto 1);
--// Read enable
ap1_rden : in std_logic;
--// Write enable
ap1_wren : in std_logic;
--// Byte enable
ap1_bena : in std_logic_vector(1 downto 0);
--// Data bus (read)
ap1_rddata : out std_logic_vector(15 downto 0);
--// Data bus (write)
ap1_wrdata : in std_logic_vector(15 downto 0);
--// Burst size
ap1_bst_siz : in std_logic_vector(2 downto 0);
--// Read burst active
ap1_rd_bst_act : out std_logic;
--// Write burst active
ap1_wr_bst_act : out std_logic;
--//------------------------
--// Access port #2 (GPU) --
--//------------------------
--// RAM select
ap2_ram_sel : in std_logic;
--// Address bus
ap2_address : in std_logic_vector(23 downto 1);
--// Read enable
ap2_rden : in std_logic;
--// Write enable
ap2_wren : in std_logic;
--// Byte enable
ap2_bena : in std_logic_vector(1 downto 0);
--// Data bus (read)
ap2_rddata : out std_logic_vector(15 downto 0);
--// Data bus (write)
ap2_wrdata : in std_logic_vector(15 downto 0);
--// Burst size
ap2_bst_siz : in std_logic_vector(2 downto 0);
--// Read burst active
ap2_rd_bst_act : out std_logic;
--// Write burst active
ap2_wr_bst_act : out std_logic;
--//------------------------
--// Access port #3 (CTL) --
--//------------------------
--// RAM select
ap3_ram_sel : in std_logic;
--// Address bus
ap3_address : in std_logic_vector(23 downto 1);
--// Read enable
ap3_rden : in std_logic;
--// Write enable
ap3_wren : in std_logic;
--// Byte enable
ap3_bena : in std_logic_vector(1 downto 0);
--// Data bus (read)
ap3_rddata : out std_logic_vector(15 downto 0);
--// Data bus (write)
ap3_wrdata : in std_logic_vector(15 downto 0);
--// Burst size
ap3_bst_siz : in std_logic_vector(2 downto 0);
--// Read burst active
ap3_rd_bst_act : out std_logic;
--// Write burst active
ap3_wr_bst_act : out std_logic;
--//------------------------
--// SDRAM memory signals --
--//------------------------
--// SDRAM controller ready
sdram_rdy : out std_logic;
--// SDRAM chip select
sdram_cs_n : out std_logic;
--// SDRAM row address strobe
sdram_ras_n : out std_logic;
--// SDRAM column address strobe
sdram_cas_n : out std_logic;
--// SDRAM write enable
sdram_we_n : out std_logic;
--// SDRAM DQ masks
sdram_dqm_n : out std_logic_vector(1 downto 0);
--// SDRAM bank address
sdram_ba : out std_logic_vector(1 downto 0);
--// SDRAM address
sdram_addr : out std_logic_vector(11 downto 0);
--// SDRAM data
sdram_dq_oe : out std_logic;
sdram_dq_o : out std_logic_vector(15 downto 0);
sdram_dq_i : in std_logic_vector(15 downto 0)
);
END COMPONENT;
COMPONENT pll
PORT(inclk0 : IN STD_LOGIC;
c0 : OUT STD_LOGIC;
......
);
END COMPONENT;
signal AUDIO_L_PCM : std_logic_vector(15 downto 0);
signal AUDIO_R_PCM : std_logic_vector(15 downto 0);
signal AUDIO_L_PCM : std_logic_vector(15 downto 0);
signal AUDIO_R_PCM : std_logic_vector(15 downto 0);
signal VGA_VS_RAW : std_logic;
signal VGA_HS_RAW : std_logic;
signal JOY1_IN_n : std_logic_vector(4 downto 0);
signal JOY2_IN_n : std_logic_vector(4 downto 0);
signal RESET_n : std_logic;
signal PLL_LOCKED : std_logic;
signal CLK : std_logic;
signal CLK_SDRAM : std_logic;
signal VGA_VS_RAW : std_logic;
signal VGA_HS_RAW : std_logic;
-- SDRAM
signal SDRAM_REQUEST : std_logic;
signal SDRAM_REQUEST_COMPLETE : std_logic;
signal SDRAM_READ_ENABLE : STD_LOGIC;
signal SDRAM_WRITE_ENABLE : std_logic;
signal SDRAM_ADDR : STD_LOGIC_VECTOR(22 DOWNTO 0);
SIGNAL SDRAM_DI : std_logic_vector(31 downto 0);
SIGNAL SDRAM_WIDTH_32BIT_ACCESS : std_logic;
SIGNAL SDRAM_WIDTH_16BIT_ACCESS : std_logic;
SIGNAL SDRAM_WIDTH_8BIT_ACCESS : std_logic;
signal SDRAM_REFRESH : std_logic;
signal JOY1_IN_n : std_logic_vector(4 downto 0);
signal JOY2_IN_n : std_logic_vector(4 downto 0);
signal SYSTEM_RESET_REQUEST: std_logic;
signal RESET_n : std_logic;
signal PLL_LOCKED : std_logic;
signal CLK : std_logic;
signal CLK_SDRAM : std_logic;
signal seq_reg : std_logic_vector(11 downto 0);
signal seq_next : std_logic_vector(11 downto 0);
signal seq_ph_reg : std_logic;
signal seq_ph_next : std_logic;
signal ref_reg : std_logic;
signal ref_next : std_logic;
signal sdram_request_complete_next : std_logic;
signal sdram_request_complete_reg : std_logic;
signal sdram_request_next : std_logic;
signal sdram_request_reg : std_logic;
signal ram_di_next : std_logic_vector(15 downto 0);
signal ram_di_reg : std_logic_vector(15 downto 0);
signal ram_do_next : std_logic_vector(31 downto 0);
signal ram_do_reg : std_logic_vector(31 downto 0);
signal ram_do : std_logic_vector(15 downto 0);
signal ram_bena_next : std_logic_vector(1 downto 0);
signal ram_bena_reg : std_logic_vector(1 downto 0);
signal ram_rd_active : std_logic;
signal ram_wr_active : std_logic;
signal sdram_dq_oe : std_logic;
signal sdram_dq_o : std_logic_vector(15 downto 0);
signal sdram_dq_i : std_logic_vector(15 downto 0);
signal sdram_rdy : std_logic;
-- pokey keyboard
SIGNAL KEYBOARD_SCAN : std_logic_vector(5 downto 0);
SIGNAL KEYBOARD_RESPONSE : std_logic_vector(1 downto 0);
-- gtia consol keys
SIGNAL CONSOL_START : std_logic;
SIGNAL CONSOL_SELECT : std_logic;
SIGNAL CONSOL_OPTION : std_logic;
-- 6502 throttling
SIGNAL THROTTLE_COUNT_6502 : std_logic_vector(5 downto 0);
BEGIN
dac_left : hq_dac
......
JOY1_IN_N <= JOY1_n(4)&JOY1_n(0)&JOY1_n(1)&JOY1_n(2)&JOY1_n(3);
JOY2_IN_N <= JOY2_n(4)&JOY2_n(0)&JOY2_n(1)&JOY2_n(2)&JOY2_n(3);
-- THROTTLE
THROTTLE_COUNT_6502 <= std_logic_vector(to_unsigned(32-1,6));
-- VIDEO
VGA_HS <= not(VGA_HS_RAW xor VGA_VS_RAW);
VGA_VS <= not(VGA_VS_RAW);
atari800xl : entity work.atari800core_helloworld
--atari800xl : entity work.atari800core_helloworld
-- GENERIC MAP
-- (
-- cycle_length => 32,
-- video_bits => 4,
-- internal_ram => 16384
-- )
-- PORT MAP
-- (
-- CLK => clk,
-- RESET_N => reset_n,
--
-- VGA_VS => vga_vs_raw,
-- VGA_HS => vga_hs_raw,
-- VGA_B => vga_b,
-- VGA_G => vga_g,
-- VGA_R => vga_r,
--
-- AUDIO_L => AUDIO_L_PCM,
-- AUDIO_R => AUDIO_R_PCM,
--
-- JOY1_n => JOY1_IN_n,
-- JOY2_n => JOY2_IN_n,
--
-- PS2_CLK => ps2k_clk,
-- PS2_DAT => ps2k_dat,
--
-- PAL => '1'
-- );
-- PS2 to pokey
keyboard_map1 : entity work.ps2_to_atari800
PORT MAP
(
CLK => clk,
RESET_N => reset_n,
PS2_CLK => ps2k_clk,
PS2_DAT => ps2k_dat,
KEYBOARD_SCAN => KEYBOARD_SCAN,
KEYBOARD_RESPONSE => KEYBOARD_RESPONSE,
CONSOL_START => CONSOL_START,
CONSOL_SELECT => CONSOL_SELECT,
CONSOL_OPTION => CONSOL_OPTION
-- TODO - reset!
);
atarixl_simple_sdram1 : entity work.atari800core_simple_sdram
GENERIC MAP
(
cycle_length => 32,
video_bits => 4,
internal_ram => 16384
cycle_length => 16,
internal_rom => 1,
internal_ram => 0,
video_bits => 4
)
PORT MAP
(
CLK => clk,
RESET_N => reset_n,
CLK => CLK,
--RESET_N => RESET_N and SDRAM_RESET_N and not(SYSTEM_RESET_REQUEST),
RESET_N => RESET_N and sdram_rdy,
VGA_VS => vga_vs_raw,
VGA_HS => vga_hs_raw,
VGA_B => vga_b,
VGA_G => vga_g,
VGA_R => vga_r,
VGA_VS => VGA_VS_RAW,
VGA_HS => VGA_HS_RAW,
VGA_B => VGA_B,
VGA_G => VGA_G,
VGA_R => VGA_R,
AUDIO_L => AUDIO_L_PCM,
AUDIO_R => AUDIO_R_PCM,
......
JOY1_n => JOY1_IN_n,
JOY2_n => JOY2_IN_n,
PS2_CLK => ps2k_clk,
PS2_DAT => ps2k_dat,
KEYBOARD_RESPONSE => KEYBOARD_RESPONSE,
KEYBOARD_SCAN => KEYBOARD_SCAN,
PAL => '1'
SIO_COMMAND => open,
SIO_RXD => '1',
SIO_TXD => open,
CONSOL_OPTION => CONSOL_OPTION,
CONSOL_SELECT => CONSOL_SELECT,
CONSOL_START => CONSOL_START,
SDRAM_REQUEST => SDRAM_REQUEST,
SDRAM_REQUEST_COMPLETE => SDRAM_REQUEST_COMPLETE,
SDRAM_READ_ENABLE => SDRAM_READ_ENABLE,
SDRAM_WRITE_ENABLE => SDRAM_WRITE_ENABLE,
SDRAM_ADDR => SDRAM_ADDR,
SDRAM_DO => ram_do_reg,
SDRAM_DI => SDRAM_DI,
SDRAM_32BIT_WRITE_ENABLE => SDRAM_WIDTH_32bit_ACCESS,
SDRAM_16BIT_WRITE_ENABLE => SDRAM_WIDTH_16bit_ACCESS,
SDRAM_8BIT_WRITE_ENABLE => SDRAM_WIDTH_8bit_ACCESS,
DMA_FETCH => '0',
DMA_READ_ENABLE => '0',
DMA_32BIT_WRITE_ENABLE => '0',
DMA_16BIT_WRITE_ENABLE => '0',
DMA_8BIT_WRITE_ENABLE => '0',
DMA_ADDR => (others=>'1'),
DMA_WRITE_DATA => (others=>'1'),
MEMORY_READY_DMA => open,
RAM_SELECT => (others=>'0'),
ROM_SELECT => "000001",
PAL => '1',
HALT => '0',
THROTTLE_COUNT_6502 => THROTTLE_COUNT_6502
);
--b2v_inst20 : sdram_statemachine_mcc
......
-- DATA_OUT => SDRAM_DO,
-- SDRAM_ADDR => SDRAM_A(12 downto 0)); -- TODO?
process(clk_sdram,reset_n)
begin
if (reset_n='0') then
seq_reg <= "000000000001";
seq_ph_reg <= '0';
ref_reg <= '0';
ram_do_reg <= (others=>'0');
ram_di_reg <= (others=>'0');
ram_bena_reg <= (others=>'0');
sdram_request_complete_reg <= '0';
sdram_request_reg <= '0';
elsif (clk_sdram'event and clk_sdram = '1') then
seq_reg <= seq_next;
seq_ph_reg <= seq_ph_next;
ref_reg <= ref_next;
ram_do_reg <= ram_do_next;
ram_di_reg <= ram_di_next;
ram_bena_reg <= ram_bena_next;
sdram_request_complete_reg <= sdram_request_complete_next;
sdram_request_reg <= sdram_request_next;
end if;
end process;
-- Generate sdram sequence
process(seq_reg, seq_ph_reg, ref_reg)
begin
seq_next <= seq_reg(10 downto 0)&seq_reg(11);
seq_ph_next <= seq_ph_reg;
ref_next <= ref_reg;
if (seq_reg(10) = '1') then
seq_ph_next <= not(seq_ph_reg);
ref_next <= not(ref_reg);
end if;
end process;
-- Adapt SDRAM
process(sdram_request_reg, sdram_request, sdram_request_complete_reg, ram_do_reg, seq_reg, ram_do, ram_rd_active, ram_wr_active, SDRAM_WIDTH_8BIT_ACCESS, SDRAM_WRITE_ENABLE, SDRAM_READ_ENABLE, SDRAM_DI, SDRAM_ADDR)
begin
sdram_request_next <= sdram_request_reg or sdram_request;
sdram_request_complete_next <= sdram_request_complete_reg;
ram_bena_next <= "00";
ram_di_next <= (others=>'0');
ram_do_next <= ram_do_reg;
case seq_reg is
when "000000000001" =>
-- nop
when "000000000010" => -- write data from next...
if (SDRAM_WRITE_ENABLE = '1') then
if (SDRAM_WIDTH_8BIT_ACCESS = '1') then
ram_di_next <= SDRAM_DI(7 downto 0)&SDRAM_DI(7 downto 0);
ram_bena_next <= SDRAM_ADDR(0)&not(SDRAM_ADDR(0));
else
ram_di_next <= SDRAM_DI(15 downto 0);
ram_bena_next <= "11";
end if;
end if;
when "000000000100" =>
if (SDRAM_WRITE_ENABLE = '1') then
if (SDRAM_WIDTH_8BIT_ACCESS = '1') then
ram_di_next <= (others=>'0');
else
ram_di_next <= SDRAM_DI(15 downto 0);
ram_bena_next <= "11";
end if;
end if;
if ((ram_wr_active)='1') then
sdram_request_complete_next <= '1';
sdram_request_next <= '0';
end if;
when "000000001000" =>
-- nop
when "000000010000" =>
-- nop
when "000000100000" =>
-- nop
when "000001000000" =>
sdram_request_complete_next <= '0';
if (SDRAM_READ_ENABLE = '1') then
if (SDRAM_WIDTH_8BIT_ACCESS = '1') then
if (SDRAM_ADDR(0) = '0') then
ram_do_next(15 downto 0) <= ram_do(7 downto 0)&ram_do(7 downto 0);
else
ram_do_next(15 downto 0) <= ram_do(15 downto 8)&ram_do(15 downto 8);
end if;
else
ram_do_next(15 downto 0) <= ram_do;
end if;
end if;
when "000010000000" =>
if (SDRAM_READ_ENABLE = '1') then
if (SDRAM_WIDTH_8BIT_ACCESS = '1') then
ram_do_next(31 downto 16) <= (others=>'0');
else
ram_do_next(31 downto 16) <= ram_do;
end if;
end if;
if ((ram_rd_active)='1') then
sdram_request_complete_next <= '1';
sdram_request_next <= '0';
end if;
when "000100000000" =>
-- nop
when "001000000000" =>
-- nop
when "010000000000" =>
-- nop
when "100000000000" =>
sdram_request_complete_next <= '0';
-- nop
when others =>
-- never
end case;
end process;
SDRAM_REQUEST_COMPLETE <= SDRAM_REQUEST_COMPLETE_REG;
sdram_controller : sdram_ctrl
PORT MAP
(
CLK => CLK_SDRAM,
rst => not(reset_n),
seq_cyc => seq_reg(11 downto 0),
seq_ph => seq_ph_reg,
refr_cyc => ref_reg,
ap1_ram_sel => SDRAM_REQUEST_REG,
ap1_address => '0'&SDRAM_ADDR(22 downto 1),
ap1_rden => SDRAM_READ_ENABLE,
ap1_wren => SDRAM_WRITE_ENABLE,
ap1_bena => ram_bena_reg,
ap1_rddata => ram_do,
ap1_wrdata => ram_di_reg,
ap1_bst_siz => "001",
ap1_rd_bst_act => ram_rd_active,
ap1_wr_bst_act => ram_wr_active,
ap2_ram_sel => '0',
ap2_address => "00000000000000000000000",
ap2_rden => '0',
ap2_wren => '0',
ap2_bena => "11",
ap2_rddata => open,
ap2_wrdata => X"0000",
ap2_bst_siz => "111",
ap2_rd_bst_act => open,
ap2_wr_bst_act => open,
ap3_ram_sel => '0',
ap3_address => "00000000000000000000000",
ap3_rden => '0',
ap3_wren => '0',
ap3_bena => "11",
ap3_rddata => open,
ap3_wrdata => X"0000",
ap3_bst_siz => "111",
ap3_rd_bst_act => open,
ap3_wr_bst_act => open,
sdram_rdy => sdram_rdy,
sdram_cs_n => sdram_cs_n,
sdram_ras_n => sdram_ras_n,
sdram_cas_n => sdram_cas_n,
sdram_we_n => sdram_we_n,
sdram_dqm_n => sdram_dqm_n,
sdram_ba => sdram_ba,
sdram_addr => sdram_a(11 downto 0),
sdram_dq_oe => sdram_dq_oe,
sdram_dq_o => sdram_dq_o,
sdram_dq_i => sdram_dq_i
);
sdram_dq <= sdram_dq_o when sdram_dq_oe='1' else (others=>'Z');
sdram_dq_i <= sdram_dq;
sdram_a(12) <= '1';
END vhdl;
mcc216/atari800core_mcc.wcfg
<?xml version="1.0" encoding="UTF-8"?>
<wave_config>
<wave_state>
</wave_state>
<db_ref_list>
<db_ref path="atari800core_mcc.wdb" id="1" type="auto">
<top_modules>
<top_module name="atari800core_mcc_tb" />
<top_module name="attributes" />
<top_module name="math_real" />
<top_module name="numeric_std" />
<top_module name="std_logic_1164" />
<top_module name="std_logic_arith" />
<top_module name="std_logic_misc" />
<top_module name="std_logic_textio" />
<top_module name="std_logic_unsigned" />
<top_module name="textio" />
<top_module name="vl_types" />
</top_modules>
</db_ref>
</db_ref_list>
<WVObjectSize size="35" />
<wvobject fp_name="/atari800core_mcc_tb/clk_a" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">clk_a</obj_property>
<obj_property name="ObjectShortName">clk_a</obj_property>
</wvobject>
<wvobject fp_name="/atari800core_mcc_tb/clk_b" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">clk_b</obj_property>
<obj_property name="ObjectShortName">clk_b</obj_property>
</wvobject>
<wvobject fp_name="/atari800core_mcc_tb/reset_n" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">reset_n</obj_property>
<obj_property name="ObjectShortName">reset_n</obj_property>
</wvobject>
<wvobject fp_name="/atari800core_mcc_tb/reset" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">reset</obj_property>
<obj_property name="ObjectShortName">reset</obj_property>
</wvobject>
<wvobject fp_name="/atari800core_mcc_tb/sdram_ba" type="array" db_ref_id="1">
<obj_property name="ElementShortName">sdram_ba[1:0]</obj_property>
<obj_property name="ObjectShortName">sdram_ba[1:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/atari800core_mcc_tb/sdram_cs_n" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">sdram_cs_n</obj_property>
<obj_property name="ObjectShortName">sdram_cs_n</obj_property>
</wvobject>
<wvobject fp_name="/atari800core_mcc_tb/sdram_ras_n" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">sdram_ras_n</obj_property>
<obj_property name="ObjectShortName">sdram_ras_n</obj_property>
</wvobject>
<wvobject fp_name="/atari800core_mcc_tb/sdram_cas_n" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">sdram_cas_n</obj_property>
<obj_property name="ObjectShortName">sdram_cas_n</obj_property>
</wvobject>
<wvobject fp_name="/atari800core_mcc_tb/sdram_we_n" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">sdram_we_n</obj_property>
<obj_property name="ObjectShortName">sdram_we_n</obj_property>
</wvobject>
<wvobject fp_name="/atari800core_mcc_tb/sdram_dqm_n" type="array" db_ref_id="1">
<obj_property name="ElementShortName">sdram_dqm_n[1:0]</obj_property>
<obj_property name="ObjectShortName">sdram_dqm_n[1:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/atari800core_mcc_tb/sdram_clk" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">sdram_clk</obj_property>
<obj_property name="ObjectShortName">sdram_clk</obj_property>
</wvobject>
<wvobject fp_name="/atari800core_mcc_tb/sdram_a" type="array" db_ref_id="1">
<obj_property name="ElementShortName">sdram_a[12:0]</obj_property>
<obj_property name="ObjectShortName">sdram_a[12:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/atari800core_mcc_tb/sdram_dq" type="array" db_ref_id="1">
<obj_property name="ElementShortName">sdram_dq[15:0]</obj_property>
<obj_property name="ObjectShortName">sdram_dq[15:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/atari800core_mcc_tb/atari/atarixl_simple_sdram1/atari800xl/cpu6502/reset" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">reset</obj_property>
<obj_property name="ObjectShortName">reset</obj_property>
</wvobject>
<wvobject fp_name="/atari800core_mcc_tb/atari/atarixl_simple_sdram1/atari800xl/cpu6502/di" type="array" db_ref_id="1">
<obj_property name="ElementShortName">di[7:0]</obj_property>
<obj_property name="ObjectShortName">di[7:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/atari800core_mcc_tb/atari/atarixl_simple_sdram1/atari800xl/cpu6502/do" type="array" db_ref_id="1">
<obj_property name="ElementShortName">do[7:0]</obj_property>
<obj_property name="ObjectShortName">do[7:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/atari800core_mcc_tb/atari/atarixl_simple_sdram1/atari800xl/cpu6502/a" type="array" db_ref_id="1">
<obj_property name="ElementShortName">a[15:0]</obj_property>
<obj_property name="ObjectShortName">a[15:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/atari800core_mcc_tb/atari/atarixl_simple_sdram1/atari800xl/cpu6502/throttle" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">throttle</obj_property>
<obj_property name="ObjectShortName">throttle</obj_property>
</wvobject>
<wvobject fp_name="/atari800core_mcc_tb/atari/atarixl_simple_sdram1/atari800xl/cpu6502/memory_ready" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">memory_ready</obj_property>
<obj_property name="ObjectShortName">memory_ready</obj_property>
</wvobject>
<wvobject fp_name="/atari800core_mcc_tb/atari/sdram_request" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">sdram_request</obj_property>
<obj_property name="ObjectShortName">sdram_request</obj_property>
</wvobject>
<wvobject fp_name="/atari800core_mcc_tb/atari/sdram_request_next" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">sdram_request_next</obj_property>
<obj_property name="ObjectShortName">sdram_request_next</obj_property>
</wvobject>
<wvobject fp_name="/atari800core_mcc_tb/atari/sdram_request_reg" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">sdram_request_reg</obj_property>
<obj_property name="ObjectShortName">sdram_request_reg</obj_property>
</wvobject>
<wvobject fp_name="/atari800core_mcc_tb/atari/sdram_request_complete_next" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">sdram_request_complete_next</obj_property>
<obj_property name="ObjectShortName">sdram_request_complete_next</obj_property>
</wvobject>
<wvobject fp_name="/atari800core_mcc_tb/atari/sdram_request_complete_reg" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">sdram_request_complete_reg</obj_property>
<obj_property name="ObjectShortName">sdram_request_complete_reg</obj_property>
</wvobject>
<wvobject fp_name="/atari800core_mcc_tb/atari/sdram_request_complete" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">sdram_request_complete</obj_property>
<obj_property name="ObjectShortName">sdram_request_complete</obj_property>
</wvobject>
<wvobject fp_name="/atari800core_mcc_tb/atari/sdram_rdy" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">sdram_rdy</obj_property>
<obj_property name="ObjectShortName">sdram_rdy</obj_property>
</wvobject>
<wvobject fp_name="/atari800core_mcc_tb/atari/atarixl_simple_sdram1/sdram_addr" type="array" db_ref_id="1">
<obj_property name="ElementShortName">sdram_addr[22:0]</obj_property>
<obj_property name="ObjectShortName">sdram_addr[22:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/atari800core_mcc_tb/atari/atarixl_simple_sdram1/atari800xl/mmu1/cpu_fetch" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">cpu_fetch</obj_property>
<obj_property name="ObjectShortName">cpu_fetch</obj_property>
</wvobject>
<wvobject fp_name="/atari800core_mcc_tb/atari/atarixl_simple_sdram1/atari800xl/mmu1/antic_fetch" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">antic_fetch</obj_property>
<obj_property name="ObjectShortName">antic_fetch</obj_property>
</wvobject>
<wvobject fp_name="/atari800core_mcc_tb/atari/sdram_controller/ap1_rden" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">ap1_rden</obj_property>
<obj_property name="ObjectShortName">ap1_rden</obj_property>
</wvobject>
<wvobject fp_name="/atari800core_mcc_tb/atari/sdram_controller/ap1_wren" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">ap1_wren</obj_property>
<obj_property name="ObjectShortName">ap1_wren</obj_property>
</wvobject>
<wvobject fp_name="/atari800core_mcc_tb/atari/ram_rd_active" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">ram_rd_active</obj_property>
<obj_property name="ObjectShortName">ram_rd_active</obj_property>
</wvobject>
<wvobject fp_name="/atari800core_mcc_tb/atari/ram_wr_active" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">ram_wr_active</obj_property>
<obj_property name="ObjectShortName">ram_wr_active</obj_property>
</wvobject>
<wvobject fp_name="/atari800core_mcc_tb/atari/seq_ph_reg" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">seq_ph_reg</obj_property>
<obj_property name="ObjectShortName">seq_ph_reg</obj_property>
</wvobject>
<wvobject fp_name="/atari800core_mcc_tb/atari/seq_reg" type="array" db_ref_id="1">
<obj_property name="ElementShortName">seq_reg[11:0]</obj_property>
<obj_property name="ObjectShortName">seq_reg[11:0]</obj_property>
</wvobject>
</wave_config>
mcc216/build.sh
mkdir build
cp atari800core_mcc.vhd build
cp pll.* build
cp sdram_ctrl_3_ports.v build
cp atari800core.sdc build
cd build
mcc216/pll.bsf
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2012 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.2"))
(symbol
(rect 0 0 248 184)
(text "pll" (rect 118 0 133 16)(font "Arial" (font_size 10)))
(text "inst" (rect 8 168 25 180)(font "Arial" ))
(port
(pt 0 64)
(input)
(text "inclk0" (rect 0 0 31 14)(font "Arial" (font_size 8)))
(text "inclk0" (rect 4 50 29 63)(font "Arial" (font_size 8)))
(line (pt 0 64)(pt 40 64))
)
(port
(pt 248 64)
(output)
(text "c0" (rect 0 0 14 14)(font "Arial" (font_size 8)))
(text "c0" (rect 232 50 242 63)(font "Arial" (font_size 8)))
)
(port
(pt 248 80)
(output)
(text "c1" (rect 0 0 14 14)(font "Arial" (font_size 8)))
(text "c1" (rect 232 66 240 79)(font "Arial" (font_size 8)))
)
(port
(pt 248 96)
(output)
(text "c2" (rect 0 0 14 14)(font "Arial" (font_size 8)))
(text "c2" (rect 232 82 242 95)(font "Arial" (font_size 8)))
)
(port
(pt 248 112)
(output)
(text "locked" (rect 0 0 36 14)(font "Arial" (font_size 8)))
(text "locked" (rect 213 98 242 111)(font "Arial" (font_size 8)))
)
(drawing
(text "Cyclone III" (rect 186 168 417 347)(font "Arial" ))
(text "inclk0 frequency: 5.000 MHz" (rect 50 59 218 129)(font "Arial" ))
(text "Operation Mode: Normal" (rect 50 72 199 155)(font "Arial" ))
(text "Clk " (rect 51 93 116 197)(font "Arial" ))
(text "Ratio" (rect 72 93 164 197)(font "Arial" ))
(text "Ph (dg)" (rect 98 93 225 197)(font "Arial" ))
(text "DC (%)" (rect 132 93 294 197)(font "Arial" ))
(text "c0" (rect 54 107 116 225)(font "Arial" ))
(text "23/2" (rect 74 107 164 225)(font "Arial" ))
(text "0.00" (rect 104 107 224 225)(font "Arial" ))
(text "50.00" (rect 136 107 293 225)(font "Arial" ))
(text "c1" (rect 54 121 115 253)(font "Arial" ))
(text "23/2" (rect 74 121 164 253)(font "Arial" ))
(text "0.00" (rect 104 121 224 253)(font "Arial" ))
(text "50.00" (rect 136 121 293 253)(font "Arial" ))
(text "c2" (rect 54 135 116 281)(font "Arial" ))
(text "23/2" (rect 74 135 164 281)(font "Arial" ))
(text "0.00" (rect 104 135 224 281)(font "Arial" ))
(text "50.00" (rect 136 135 293 281)(font "Arial" ))
(line (pt 0 0)(pt 249 0))
(line (pt 249 0)(pt 249 185))
(line (pt 0 185)(pt 249 185))
(line (pt 0 0)(pt 0 185))
(line (pt 48 91)(pt 164 91))
(line (pt 48 104)(pt 164 104))
(line (pt 48 118)(pt 164 118))
(line (pt 48 132)(pt 164 132))
(line (pt 48 146)(pt 164 146))
(line (pt 48 91)(pt 48 146))
(line (pt 69 91)(pt 69 146)(line_width 3))
(line (pt 95 91)(pt 95 146)(line_width 3))
(line (pt 129 91)(pt 129 146)(line_width 3))
(line (pt 163 91)(pt 163 146))
(line (pt 40 48)(pt 199 48))
(line (pt 199 48)(pt 199 167))
(line (pt 40 167)(pt 199 167))
(line (pt 40 48)(pt 40 167))
(line (pt 247 64)(pt 199 64))
(line (pt 247 80)(pt 199 80))
(line (pt 247 96)(pt 199 96))
(line (pt 247 112)(pt 199 112))
)
)
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2013 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.2"))
(symbol
(rect 0 0 216 152)
(text "pll" (rect 102 0 116 11)(font "Arial" (font_size 10)))
(text "inst" (rect 8 141 22 148)(font "Arial" ))
(port
(pt 0 64)
(input)
(text "inclk0" (rect 0 0 22 9)(font "Arial" (font_size 8)))
(text "inclk0" (rect 4 55 21 63)(font "Arial" (font_size 8)))
(line (pt 0 64)(pt 40 64))
)
(port
(pt 216 64)
(output)
(text "c0" (rect 0 0 9 9)(font "Arial" (font_size 8)))
(text "c0" (rect 204 55 210 63)(font "Arial" (font_size 8)))
)
(port
(pt 216 80)
(output)
(text "c1" (rect 0 0 9 9)(font "Arial" (font_size 8)))
(text "c1" (rect 204 71 210 79)(font "Arial" (font_size 8)))
)
(port
(pt 216 96)
(output)
(text "c2" (rect 0 0 9 9)(font "Arial" (font_size 8)))
(text "c2" (rect 204 87 211 95)(font "Arial" (font_size 8)))
)
(port
(pt 216 112)
(output)
(text "locked" (rect 0 0 24 9)(font "Arial" (font_size 8)))
(text "locked" (rect 191 103 211 111)(font "Arial" (font_size 8)))
)
(drawing
(text "Cyclone III" (rect 173 145 378 296)(font "Arial" ))
(text "inclk0 frequency: 5.000 MHz" (rect 50 63 187 132)(font "Arial" ))
(text "Operation Mode: Normal" (rect 50 71 175 148)(font "Arial" ))
(text "Clk " (rect 51 84 112 174)(font "Arial" ))
(text "Ratio" (rect 67 84 149 174)(font "Arial" ))
(text "Ph (dg)" (rect 88 84 198 174)(font "Arial" ))
(text "DC (%)" (rect 115 84 251 174)(font "Arial" ))
(text "c0" (rect 53 93 112 192)(font "Arial" ))
(text "69/4" (rect 68 93 149 192)(font "Arial" ))
(text "0.00" (rect 92 93 196 192)(font "Arial" ))
(text "50.00" (rect 117 93 250 192)(font "Arial" ))
(text "c1" (rect 53 102 112 210)(font "Arial" ))
(text "23/4" (rect 68 102 149 210)(font "Arial" ))
(text "0.00" (rect 92 102 196 210)(font "Arial" ))
(text "50.00" (rect 117 102 250 210)(font "Arial" ))
(text "c2" (rect 53 111 113 228)(font "Arial" ))
(text "69/4" (rect 68 111 149 228)(font "Arial" ))
(text "232.87" (rect 88 111 197 228)(font "Arial" ))
(text "50.00" (rect 117 111 250 228)(font "Arial" ))
(line (pt 0 0)(pt 217 0))
(line (pt 217 0)(pt 217 154))
(line (pt 0 154)(pt 217 154))
(line (pt 0 0)(pt 0 154))
(line (pt 48 82)(pt 138 82))
(line (pt 48 90)(pt 138 90))
(line (pt 48 99)(pt 138 99))
(line (pt 48 108)(pt 138 108))
(line (pt 48 117)(pt 138 117))
(line (pt 48 82)(pt 48 117))
(line (pt 64 82)(pt 64 117)(line_width 3))
(line (pt 85 82)(pt 85 117)(line_width 3))
(line (pt 112 82)(pt 112 117)(line_width 3))
(line (pt 137 82)(pt 137 117))
(line (pt 40 48)(pt 175 48))
(line (pt 175 48)(pt 175 136))
(line (pt 40 136)(pt 175 136))
(line (pt 40 48)(pt 40 136))
(line (pt 215 64)(pt 175 64))
(line (pt 215 80)(pt 175 80))
(line (pt 215 96)(pt 175 96))
(line (pt 215 112)(pt 175 112))
)
)
mcc216/pll.cmp
--Copyright (C) 1991-2012 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
component pll
PORT
(
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
c1 : OUT STD_LOGIC ;
c2 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC
);
end component;
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
component pll
PORT
(
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
c1 : OUT STD_LOGIC ;
c2 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC
);
end component;
mcc216/pll.ppf
<?xml version="1.0" encoding="UTF-8" ?>
<!DOCTYPE pinplan>
<pinplan intended_family="Cyclone III" variation_name="pll" megafunction_name="ALTPLL" specifies="all_ports">
<global>
<pin name="inclk0" direction="input" scope="external" source="clock" />
<pin name="c0" direction="output" scope="external" source="clock" />
<pin name="c1" direction="output" scope="external" source="clock" />
<pin name="c2" direction="output" scope="external" source="clock" />
<pin name="locked" direction="output" scope="external" />
</global>
</pinplan>
<?xml version="1.0" encoding="UTF-8" ?>
<!DOCTYPE pinplan>
<pinplan intended_family="Cyclone III" variation_name="pll" megafunction_name="ALTPLL" specifies="all_ports">
<global>
<pin name="inclk0" direction="input" scope="external" source="clock" />
<pin name="c0" direction="output" scope="external" source="clock" />
<pin name="c1" direction="output" scope="external" source="clock" />
<pin name="c2" direction="output" scope="external" source="clock" />
<pin name="locked" direction="output" scope="external" />
</global>
</pinplan>
mcc216/pll.qip
set_global_assignment -name IP_TOOL_NAME "ALTPLL"
set_global_assignment -name IP_TOOL_VERSION "12.1"
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.bsf"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.cmp"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"]
set_global_assignment -name IP_TOOL_NAME "ALTPLL"
set_global_assignment -name IP_TOOL_VERSION "13.0"
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.bsf"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.cmp"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"]
mcc216/pll.vhd
-- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: pll.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 12.1 Build 243 01/31/2013 SP 1.33 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2012 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY pll IS
PORT
(
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
c1 : OUT STD_LOGIC ;
c2 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC
);
END pll;
ARCHITECTURE SYN OF pll IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC ;
SIGNAL sub_wire4 : STD_LOGIC ;
SIGNAL sub_wire5 : STD_LOGIC ;
SIGNAL sub_wire6 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire7_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire7 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT altpll
GENERIC (
bandwidth_type : STRING;
clk0_divide_by : NATURAL;
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
clk1_divide_by : NATURAL;
clk1_duty_cycle : NATURAL;
clk1_multiply_by : NATURAL;
clk1_phase_shift : STRING;
clk2_divide_by : NATURAL;
clk2_duty_cycle : NATURAL;
clk2_multiply_by : NATURAL;
clk2_phase_shift : STRING;
compensate_clock : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
operation_mode : STRING;
pll_type : STRING;
port_activeclock : STRING;
port_areset : STRING;
port_clkbad0 : STRING;
port_clkbad1 : STRING;
port_clkloss : STRING;
port_clkswitch : STRING;
port_configupdate : STRING;
port_fbin : STRING;
port_inclk0 : STRING;
port_inclk1 : STRING;
port_locked : STRING;
port_pfdena : STRING;
port_phasecounterselect : STRING;
port_phasedone : STRING;
port_phasestep : STRING;
port_phaseupdown : STRING;
port_pllena : STRING;
port_scanaclr : STRING;
port_scanclk : STRING;
port_scanclkena : STRING;
port_scandata : STRING;
port_scandataout : STRING;
port_scandone : STRING;
port_scanread : STRING;
port_scanwrite : STRING;
port_clk0 : STRING;
port_clk1 : STRING;
port_clk2 : STRING;
port_clk3 : STRING;
port_clk4 : STRING;
port_clk5 : STRING;
port_clkena0 : STRING;
port_clkena1 : STRING;
port_clkena2 : STRING;
port_clkena3 : STRING;
port_clkena4 : STRING;
port_clkena5 : STRING;
port_extclk0 : STRING;
port_extclk1 : STRING;
port_extclk2 : STRING;
port_extclk3 : STRING;
self_reset_on_loss_lock : STRING;
width_clock : NATURAL
);
PORT (
clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
locked : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
sub_wire7_bv(0 DOWNTO 0) <= "0";
sub_wire7 <= To_stdlogicvector(sub_wire7_bv);
sub_wire4 <= sub_wire0(2);
sub_wire3 <= sub_wire0(0);
sub_wire1 <= sub_wire0(1);
c1 <= sub_wire1;
locked <= sub_wire2;
c0 <= sub_wire3;
c2 <= sub_wire4;
sub_wire5 <= inclk0;
sub_wire6 <= sub_wire7(0 DOWNTO 0) & sub_wire5;
altpll_component : altpll
GENERIC MAP (
bandwidth_type => "AUTO",
clk0_divide_by => 2,
clk0_duty_cycle => 50,
clk0_multiply_by => 23,
clk0_phase_shift => "0",
clk1_divide_by => 2,
clk1_duty_cycle => 50,
clk1_multiply_by => 23,
clk1_phase_shift => "0",
clk2_divide_by => 2,
clk2_duty_cycle => 50,
clk2_multiply_by => 23,
clk2_phase_shift => "0",
compensate_clock => "CLK0",
inclk0_input_frequency => 200000,
intended_device_family => "Cyclone III",
lpm_hint => "CBX_MODULE_PREFIX=pll",
lpm_type => "altpll",
operation_mode => "NORMAL",
pll_type => "AUTO",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_UNUSED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_UNUSED",
port_configupdate => "PORT_UNUSED",
port_fbin => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_USED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_UNUSED",
port_phasedone => "PORT_UNUSED",
port_phasestep => "PORT_UNUSED",
port_phaseupdown => "PORT_UNUSED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_UNUSED",
port_scanclkena => "PORT_UNUSED",
port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_USED",
port_clk2 => "PORT_USED",
port_clk3 => "PORT_UNUSED",
port_clk4 => "PORT_UNUSED",
port_clk5 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
port_extclk0 => "PORT_UNUSED",
port_extclk1 => "PORT_UNUSED",
port_extclk2 => "PORT_UNUSED",
port_extclk3 => "PORT_UNUSED",
self_reset_on_loss_lock => "OFF",
width_clock => 5
)
PORT MAP (
inclk => sub_wire6,
clk => sub_wire0,
locked => sub_wire2
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "1"
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "20"
-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "20"
-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "20"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "57.500000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "57.500000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "57.500000"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "1"
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "5.000"
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps"
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "230"
-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "230"
-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "230"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "28.70000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "28.70000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "100.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ns"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ns"
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK2 STRING "1"
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "2"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "23"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "2"
-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "23"
-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "2"
-- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "23"
-- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "200000"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
-- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
-- Retrieval info: CBX_MODULE_PREFIX: ON
-- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
... This diff was truncated because it exceeds the maximum size that can be displayed.

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