Revision 335
Added by markw over 10 years ago
| papilioduo/dac.vhd | ||
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library ieee;
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use ieee.std_logic_1164.all;
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entity dac is
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generic (
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msbi_g : integer := 15
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);
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port (
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clk_i : in std_logic;
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res_n_i : in std_logic;
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dac_i : in std_logic_vector(msbi_g downto 0);
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dac_o : out std_logic
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);
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end dac;
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library ieee;
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use ieee.numeric_std.all;
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architecture rtl of dac is
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signal DACout_q : std_logic;
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signal DeltaAdder_s,
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SigmaAdder_s,
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SigmaLatch_q,
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DeltaB_s : unsigned(msbi_g+2 downto 0);
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begin
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DeltaB_s(msbi_g+2 downto msbi_g+1) <= SigmaLatch_q(msbi_g+2) &
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SigmaLatch_q(msbi_g+2);
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DeltaB_s(msbi_g downto 0) <= (others => '0');
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DeltaAdder_s <= unsigned('0' & '0' & dac_i) + DeltaB_s;
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SigmaAdder_s <= DeltaAdder_s + SigmaLatch_q;
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seq: process (clk_i, res_n_i)
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begin
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if res_n_i = '0' then
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SigmaLatch_q <= to_unsigned(2**(msbi_g+1), SigmaLatch_q'length);
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DACout_q <= '0';
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elsif clk_i'event and clk_i = '1' then
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SigmaLatch_q <= SigmaAdder_s;
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DACout_q <= SigmaLatch_q(msbi_g+2);
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end if;
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end process seq;
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dac_o <= DACout_q;
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end rtl;
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| papilioduo/atari800core_papilioduo.vhd | ||
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ARCHITECTURE vhdl OF atari800core_papilioduo IS
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component hq_dac
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port (
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reset :in std_logic;
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clk :in std_logic;
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clk_ena : in std_logic;
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pcm_in : in std_logic_vector(19 downto 0);
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dac_out : out std_logic
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);
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end component;
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signal AUDIO_L_PCM : std_logic_vector(15 downto 0);
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signal AUDIO_R_PCM : std_logic_vector(15 downto 0);
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signal AUDIO_OUT : std_logic;
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signal VIDEO_VS : std_logic;
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signal VIDEO_HS : std_logic;
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| ... | ... | |
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LED3 <= '1';
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LED4 <= '0';
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u_DAC_L : entity work.dac
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port map (
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CLK_I => CLK,
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RES_N_I => RESET_N,
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DAC_I => AUDIO_L_PCM,
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DAC_O => AUDIO1_LEFT );
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dac : hq_dac
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port map
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(
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reset => not(reset_n),
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clk => clk,
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clk_ena => '1',
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pcm_in => AUDIO_L_PCM&"0000",
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dac_out => audio_out
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);
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u_DAC_R : entity work.dac
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port map (
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CLK_I => CLK,
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RES_N_I => RESET_N,
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DAC_I => AUDIO_R_PCM,
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DAC_O => AUDIO1_RIGHT );
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audio1_left <= audio_out;
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audio1_right <= audio_out;
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--u_DAC_L : entity work.dac
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--port map (
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-- CLK_I => CLK,
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-- RES_N_I => RESET_N,
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-- DAC_I => AUDIO_L_PCM,
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-- DAC_O => AUDIO1_LEFT );
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--
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--u_DAC_R : entity work.dac
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--port map (
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-- CLK_I => CLK,
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-- RES_N_I => RESET_N,
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-- DAC_I => AUDIO_R_PCM,
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-- DAC_O => AUDIO1_RIGHT );
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gen_fake_pll : if ext_clock=1 generate
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CLK <= EXT_CLK(1);
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PLL_LOCKED <= EXT_PLL_LOCKED(1);
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| papilioduo/build.pl | ||
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`cp -p ../../common/a8core/*.vhdl .`;
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`cp -p ../../common/components/*.vhd .`;
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`cp -p ../../common/components/*.vhdl .`;
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`cp -p ../../common/components/*.v .`;
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`cp -p ../../common/zpu/*.vhd .`;
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`cp -p ../../common/zpu/*.vhdl .`;
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`cp -p ../*.vhd .`;
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| papilioduo/papilioduo.prj | ||
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vhdl work "ps2_to_atari800.vhdl"
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vhdl work "pll_pal.vhd"
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vhdl work "pll_ntsc.vhd"
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vhdl work "dac.vhd"
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verilog work "hq_dac.v"
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vhdl work "atari800core_simple_sdram.vhd"
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vhdl work "atari800core_papilioduo.vhd"
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Switched DAC