/ - Diff - EclaireXL - 64kib

     library ieee;
     use ieee.std_logic_1164.all;
     entity dac is
       generic (
         msbi_g : integer := 15
       );
       port (
         clk_i   : in  std_logic;
         res_n_i : in  std_logic;
         dac_i   : in  std_logic_vector(msbi_g downto 0);
         dac_o   : out std_logic
       );
     end dac;
     library ieee;
     use ieee.numeric_std.all;
     architecture rtl of dac is
       signal DACout_q      : std_logic;
       signal DeltaAdder_s,
              SigmaAdder_s,
              SigmaLatch_q,
              DeltaB_s      : unsigned(msbi_g+2 downto 0);
     begin
       DeltaB_s(msbi_g+2 downto msbi_g+1) <= SigmaLatch_q(msbi_g+2) &
                                             SigmaLatch_q(msbi_g+2);
       DeltaB_s(msbi_g   downto        0) <= (others => '0');
       DeltaAdder_s <= unsigned('0' & '0' & dac_i) + DeltaB_s;
       SigmaAdder_s <= DeltaAdder_s + SigmaLatch_q;
       seq: process (clk_i, res_n_i)
       begin
         if res_n_i = '0' then
           SigmaLatch_q <= to_unsigned(2**(msbi_g+1), SigmaLatch_q'length);
           DACout_q     <= '0';
         elsif clk_i'event and clk_i = '1' then
           SigmaLatch_q <= SigmaAdder_s;
           DACout_q     <= SigmaLatch_q(msbi_g+2);
         end if;
       end process seq;
       dac_o <= DACout_q;
     end rtl;

     ARCHITECTURE vhdl OF atari800core_papilioduo IS
     component hq_dac
     port (
       reset :in std_logic;
       clk :in std_logic;
       clk_ena : in std_logic;
       pcm_in : in std_logic_vector(19 downto 0);
       dac_out : out std_logic
     );
     end component;
     	signal AUDIO_L_PCM : std_logic_vector(15 downto 0);
     	signal AUDIO_R_PCM : std_logic_vector(15 downto 0);
     	signal AUDIO_OUT : std_logic;
     	signal VIDEO_VS : std_logic;
     	signal VIDEO_HS : std_logic;
-...
     LED3 <= '1';
     LED4 <= '0';
     u_DAC_L : entity work.dac
     port map (
        CLK_I                      => CLK,
        RES_N_I                    => RESET_N,
        DAC_I                      => AUDIO_L_PCM,
        DAC_O                      => AUDIO1_LEFT );
     dac : hq_dac
     port map
+    (
       reset => not(reset_n),
       clk => clk,
       clk_ena => '1',
       pcm_in => AUDIO_L_PCM&"0000",
       dac_out => audio_out
     );
     u_DAC_R : entity work.dac
     port map (
        CLK_I                      => CLK,
        RES_N_I                    => RESET_N,
        DAC_I                      => AUDIO_R_PCM,
        DAC_O                      => AUDIO1_RIGHT );
     audio1_left <= audio_out;
     audio1_right <= audio_out;
     --u_DAC_L : entity work.dac
     --port map (
     --   CLK_I                      => CLK,
     --   RES_N_I                    => RESET_N,
     --   DAC_I                      => AUDIO_L_PCM,
     --   DAC_O                      => AUDIO1_LEFT );
     --
     --u_DAC_R : entity work.dac
     --port map (
     --   CLK_I                      => CLK,
     --   RES_N_I                    => RESET_N,
     --   DAC_I                      => AUDIO_R_PCM,
     --   DAC_O                      => AUDIO1_RIGHT );
     gen_fake_pll : if ext_clock=1 generate
     	CLK <= EXT_CLK(1);
     	PLL_LOCKED <= EXT_PLL_LOCKED(1);

papilioduo/build.pl
		`cp -p ../../common/a8core/*.vhdl .`;
		`cp -p ../../common/components/*.vhd .`;
		`cp -p ../../common/components/*.vhdl .`;
		`cp -p ../../common/components/*.v .`;
		`cp -p ../../common/zpu/*.vhd .`;
		`cp -p ../../common/zpu/*.vhdl .`;
		`cp -p ../*.vhd .`;

papilioduo/papilioduo.prj
		vhdl work "ps2_to_atari800.vhdl"
		vhdl work "pll_pal.vhd"
		vhdl work "pll_ntsc.vhd"
		vhdl work "dac.vhd"
		verilog work "hq_dac.v"
		vhdl work "atari800core_simple_sdram.vhd"
		vhdl work "atari800core_papilioduo.vhd"

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EclaireXL

Revision 335

Added by markw over 10 years ago