EclaireXL

SET busformat = BusFormatAngleBracketNotRipped

SET designentry = VHDL

SET device = xc6slx9

SET devicefamily = spartan6

SET flowvendor = Other

SET package = tqg144

SET speedgrade = -3

SET verilogsim = false

SET vhdlsim = true

##

## Core Generator Run Script, generator for Project Navigator create command

##

proc findRtfPath { relativePath } {

set xilenv ""

if { [info exists ::env(XILINX) ] } {

if { [info exists ::env(MYXILINX)] } {

set xilenv [join [list $::env(MYXILINX) $::env(XILINX)] $::xilinx::path_sep ]

} else {

set xilenv $::env(XILINX)

}

}

foreach path [ split $xilenv $::xilinx::path_sep ] {

set fullPath [ file join $path $relativePath ]

if { [ file exists $fullPath ] } {

return $fullPath

}

}

return ""

}

source [ findRtfPath "data/projnav/scripts/dpm_cgUtils.tcl" ]

set result [ run_cg_create "xilinx.com:ip:clk_wiz:3.6" "pll" "Clocking Wizard" "Clocking Wizard (xilinx.com:ip:clk_wiz:3.6) generated by Project Navigator" xc6slx9-3tqg144 VHDL ]

if { $result == 0 } {

puts "Core Generator create command completed successfully."

} elseif { $result == 1 } {

puts "Core Generator create command failed."

} elseif { $result == 3 || $result == 4 } {

# convert 'version check' result to real return range, bypassing any messages.

set result [ expr $result - 3 ]

} else {

puts "Core Generator create cancelled."

}

exit $result

# file: pll.ucf

#

# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.

#

# This file contains confidential and proprietary information

# of Xilinx, Inc. and is protected under U.S. and

# international copyright and other intellectual property

# laws.

#

# DISCLAIMER

# This disclaimer is not a license and does not grant any

# rights to the materials distributed herewith. Except as

# otherwise provided in a valid license issued to you by

# Xilinx, and to the maximum extent permitted by applicable

# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND

# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES

# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING

# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-

# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and

# (2) Xilinx shall not be liable (whether in contract or tort,

# including negligence, or under any other theory of

# liability) for any loss or damage of any kind or nature

# related to, arising under or in connection with these

# materials, including for any direct, or any indirect,

# special, incidental, or consequential loss or damage

# (including loss of data, profits, goodwill, or any type of

# loss or damage suffered as a result of any action brought

# by a third party) even if such damage or loss was

# reasonably foreseeable or Xilinx had been advised of the

# possibility of the same.

#

# CRITICAL APPLICATIONS

# Xilinx products are not designed or intended to be fail-

# safe, or for use in any application requiring fail-safe

# performance, such as life-support or safety devices or

# systems, Class III medical devices, nuclear facilities,

# applications related to the deployment of airbags, or any

# other applications that could lead to death, personal

# injury, or severe property or environmental damage

# (individually and collectively, "Critical

# Applications"). Customer assumes the sole risk and

# liability of any use of Xilinx products in Critical

# Applications, subject only to applicable laws and

# regulations governing limitations on product liability.

#

# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS

# PART OF THIS FILE AT ALL TIMES.

#

# Input clock periods. These duplicate the values entered for the

# input clocks. You can use these to time your system

#----------------------------------------------------------------

NET "CLK_IN1" TNM_NET = "CLK_IN1";

TIMESPEC "TS_CLK_IN1" = PERIOD "CLK_IN1" 20.000 ns HIGH 50% INPUT_JITTER 200.0ps;

# FALSE PATH constraints

<?xml version="1.0" encoding="UTF-8"?>

<symbol version="7" name="pll">

<symboltype>BLOCK</symboltype>

<timestamp>2014-7-23T19:14:8</timestamp>

<pin polarity="Input" x="0" y="80" name="clk_in1" />

<pin polarity="Output" x="608" y="80" name="clk_out1" />

<pin polarity="Output" x="608" y="176" name="clk_out2" />

<pin polarity="Output" x="608" y="976" name="locked" />

<graph>

<text style="fontsize:40;fontname:Arial" x="32" y="32">pll</text>

<rect width="544" x="32" y="32" height="1056" />

<line x2="32" y1="80" y2="80" x1="0" />

<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="80" type="pin clk_in1" />

<line x2="576" y1="80" y2="80" x1="608" />

<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="572" y="80" type="pin clk_out1" />

<line x2="576" y1="176" y2="176" x1="608" />

<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="572" y="176" type="pin clk_out2" />

<line x2="576" y1="976" y2="976" x1="608" />

<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="572" y="976" type="pin locked" />

</graph>

</symbol>

<?xml version="1.0" encoding="UTF-8" standalone="no" ?>

<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">

<header>

<!-- ISE source project file created by Project Navigator. -->

<!-- -->

<!-- This file contains project source information including a list of -->

<!-- project source files, project and process properties. This file, -->

<!-- along with the project source files, is sufficient to open and -->

<!-- implement in ISE Project Navigator. -->

<!-- -->

<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->

</header>

<version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>

<files>

<file xil_pn:name="pll.ucf" xil_pn:type="FILE_UCF">

<association xil_pn:name="Implementation" xil_pn:seqID="0"/>

</file>

<file xil_pn:name="pll.vhd" xil_pn:type="FILE_VHDL">

<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>

<association xil_pn:name="Implementation" xil_pn:seqID="1"/>

<association xil_pn:name="PostMapSimulation" xil_pn:seqID="3"/>

<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="3"/>

<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="3"/>

</file>

</files>

<properties>

<property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>

<property xil_pn:name="Device" xil_pn:value="xc6slx9" xil_pn:valueState="non-default"/>

<property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/>

<property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="non-default"/>

<property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>

<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|pll|xilinx" xil_pn:valueState="non-default"/>

<property xil_pn:name="Implementation Top File" xil_pn:value="pll.vhd" xil_pn:valueState="non-default"/>

<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/pll" xil_pn:valueState="non-default"/>

<property xil_pn:name="Package" xil_pn:value="tqg144" xil_pn:valueState="default"/>

<property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>

<property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>

<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>

<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>

<property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="default"/>

<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>

<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>

<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>

<!-- -->

<!-- The following properties are for internal use only. These should not be modified.-->

<!-- -->

<property xil_pn:name="PROP_DesignName" xil_pn:value="pll" xil_pn:valueState="non-default"/>

<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>

<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2014-07-23T21:14:11" xil_pn:valueState="non-default"/>

<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="81FEB3840ACE4C7C9F4657A3E975FFC2" xil_pn:valueState="non-default"/>

<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>

<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>

</properties>

<bindings>

<binding xil_pn:location="/pll" xil_pn:name="pll.ucf"/>

</bindings>

<libraries/>

<autoManagedFiles>

<!-- The following files are identified by `include statements in verilog -->

<!-- source files and are automatically managed by Project Navigator. -->

<!-- -->

<!-- Do not hand-edit this section, as it will be overwritten when the -->

<!-- project is analyzed based on files automatically identified as -->

<!-- include files. -->

</autoManagedFiles>

</project>

<?xml version="1.0" encoding="UTF-8"?>

<!-- IMPORTANT: This is an internal file that has been generated

by the Xilinx ISE software. Any direct editing or

changes made to this file may result in unpredictable

behavior or data corruption. It is strongly advised that

users do not edit the contents of this file. -->

<messages>

<msg type="info" file="sim" num="172" delta="old" >Generating IP...

</msg>

<msg type="warning" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">A core named &apos;pll&apos; already exists in the project. Output products for this core may be overwritten.</arg>

</msg>

<msg type="warning" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">A core named &apos;pll&apos; already exists in the project. Output products for this core may be overwritten.</arg>

</msg>

<msg type="warning" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">Component clk_wiz_v3_6 does not have a valid model name for VHDL synthesis</arg>

</msg>

<msg type="info" file="sim" num="949" delta="old" >Finished generation of ASY schematic symbol.

</msg>

<msg type="info" file="sim" num="948" delta="old" >Finished FLIST file generation.

</msg>

</messages>

<?xml version="1.0" encoding="UTF-8"?>

<!-- IMPORTANT: This is an internal file that has been generated -->

<!-- by the Xilinx ISE software. Any direct editing or -->

<!-- changes made to this file may result in unpredictable -->

<!-- behavior or data corruption. It is strongly advised that -->

<!-- users do not edit the contents of this file. -->

<!-- -->

<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->

<messages>

<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;D:/Projects/Aeon Lite/cores/Atari_800/src/pll/pll.vhd&quot; into library work</arg>

</msg>

</messages>

# file: pll.ucf

#

# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.

#

# This file contains confidential and proprietary information

# of Xilinx, Inc. and is protected under U.S. and

# international copyright and other intellectual property

# laws.

#

# DISCLAIMER

# This disclaimer is not a license and does not grant any

# rights to the materials distributed herewith. Except as

# otherwise provided in a valid license issued to you by

# Xilinx, and to the maximum extent permitted by applicable

# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND

# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES

# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING

# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-

# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and

# (2) Xilinx shall not be liable (whether in contract or tort,

# including negligence, or under any other theory of

# liability) for any loss or damage of any kind or nature

# related to, arising under or in connection with these

# materials, including for any direct, or any indirect,

# special, incidental, or consequential loss or damage

# (including loss of data, profits, goodwill, or any type of

# loss or damage suffered as a result of any action brought

# by a third party) even if such damage or loss was

# reasonably foreseeable or Xilinx had been advised of the

# possibility of the same.

#

# CRITICAL APPLICATIONS

# Xilinx products are not designed or intended to be fail-

# safe, or for use in any application requiring fail-safe

# performance, such as life-support or safety devices or

# systems, Class III medical devices, nuclear facilities,

# applications related to the deployment of airbags, or any

# other applications that could lead to death, personal

# injury, or severe property or environmental damage

# (individually and collectively, "Critical

# Applications"). Customer assumes the sole risk and

# liability of any use of Xilinx products in Critical

# Applications, subject only to applicable laws and

# regulations governing limitations on product liability.

#

# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS

# PART OF THIS FILE AT ALL TIMES.

#

# Input clock periods. These duplicate the values entered for the

# input clocks. You can use these to time your system

#----------------------------------------------------------------

NET "CLK_IN1" TNM_NET = "CLK_IN1";

TIMESPEC "TS_CLK_IN1" = PERIOD "CLK_IN1" 20.000 ns HIGH 50% INPUT_JITTER 200.0ps;

# FALSE PATH constraints

# file: pll.xdc

#

# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.

#

# This file contains confidential and proprietary information

# of Xilinx, Inc. and is protected under U.S. and

# international copyright and other intellectual property

# laws.

#

# DISCLAIMER

# This disclaimer is not a license and does not grant any

# rights to the materials distributed herewith. Except as

# otherwise provided in a valid license issued to you by

# Xilinx, and to the maximum extent permitted by applicable

# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND

# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES

# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING

# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-

# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and

# (2) Xilinx shall not be liable (whether in contract or tort,

# including negligence, or under any other theory of

# liability) for any loss or damage of any kind or nature

# related to, arising under or in connection with these

# materials, including for any direct, or any indirect,

# special, incidental, or consequential loss or damage

# (including loss of data, profits, goodwill, or any type of

# loss or damage suffered as a result of any action brought

# by a third party) even if such damage or loss was

# reasonably foreseeable or Xilinx had been advised of the

# possibility of the same.

#

# CRITICAL APPLICATIONS

# Xilinx products are not designed or intended to be fail-

# safe, or for use in any application requiring fail-safe

# performance, such as life-support or safety devices or

# systems, Class III medical devices, nuclear facilities,

# applications related to the deployment of airbags, or any

# other applications that could lead to death, personal

# injury, or severe property or environmental damage

# (individually and collectively, "Critical

# Applications"). Customer assumes the sole risk and

# liability of any use of Xilinx products in Critical

# Applications, subject only to applicable laws and

# regulations governing limitations on product liability.

#

# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS

# PART OF THIS FILE AT ALL TIMES.

#

# Input clock periods. These duplicate the values entered for the

# input clocks. You can use these to time your system

#----------------------------------------------------------------

create_clock -name CLK_IN1 -period 20.000 [get_ports CLK_IN1]

set_propagated_clock CLK_IN1

set_input_jitter CLK_IN1 0.2

# Derived clock periods. These are commented out because they are

# automatically propogated by the tools

# However, if you'd like to use them for module level testing, you

# can copy them into your module level timing checks

#-----------------------------------------------------------------

#-----------------------------------------------------------------

#-----------------------------------------------------------------

# Output products list for <pll>

_xmsgs\pn_parser.xmsgs

pll.asy

pll.gise

pll.sym

pll.ucf

pll.vhd

pll.vho

pll.xco

pll.xdc

pll.xise

pll\clk_wiz_v3_6_readme.txt

pll\doc\clk_wiz_v3_6_readme.txt

pll\doc\clk_wiz_v3_6_vinfo.html

pll\doc\pg065_clk_wiz.pdf

pll\example_design\pll_exdes.ucf

pll\example_design\pll_exdes.vhd

pll\example_design\pll_exdes.xdc

pll\implement\implement.bat

pll\implement\implement.sh

pll\implement\planAhead_ise.bat

pll\implement\planAhead_ise.sh

pll\implement\planAhead_ise.tcl

pll\implement\planAhead_rdn.bat

pll\implement\planAhead_rdn.sh

pll\implement\planAhead_rdn.tcl

pll\implement\xst.prj

pll\implement\xst.scr

pll\simulation\functional\simcmds.tcl

pll\simulation\functional\simulate_isim.bat

pll\simulation\functional\simulate_isim.sh

pll\simulation\functional\simulate_mti.bat

pll\simulation\functional\simulate_mti.do

pll\simulation\functional\simulate_mti.sh

pll\simulation\functional\simulate_ncsim.sh

pll\simulation\functional\simulate_vcs.sh

pll\simulation\functional\wave.do

pll\simulation\functional\wave.sv

pll\simulation\pll_tb.vhd

pll\simulation\timing\pll_tb.vhd

pll\simulation\timing\sdf_cmd_file

pll\simulation\timing\simcmds.tcl

pll\simulation\timing\simulate_isim.sh

pll\simulation\timing\simulate_mti.bat

pll\simulation\timing\simulate_mti.do

pll\simulation\timing\simulate_mti.sh

pll\simulation\timing\simulate_ncsim.sh

pll\simulation\timing\simulate_vcs.sh

pll\simulation\timing\ucli_commands.key

pll\simulation\timing\vcs_session.tcl

pll\simulation\timing\wave.do

pll_flist.txt

pll_xmdf.tcl

-- file: pll.vhd

--

-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.

--

-- This file contains confidential and proprietary information

-- of Xilinx, Inc. and is protected under U.S. and

-- international copyright and other intellectual property

-- laws.

--

-- DISCLAIMER

-- This disclaimer is not a license and does not grant any

-- rights to the materials distributed herewith. Except as

-- otherwise provided in a valid license issued to you by

-- Xilinx, and to the maximum extent permitted by applicable

-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND

-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES

-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING

-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-

-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and

-- (2) Xilinx shall not be liable (whether in contract or tort,

-- including negligence, or under any other theory of

-- liability) for any loss or damage of any kind or nature

-- related to, arising under or in connection with these

-- materials, including for any direct, or any indirect,

-- special, incidental, or consequential loss or damage

-- (including loss of data, profits, goodwill, or any type of

-- loss or damage suffered as a result of any action brought

-- by a third party) even if such damage or loss was

-- reasonably foreseeable or Xilinx had been advised of the

-- possibility of the same.

--

-- CRITICAL APPLICATIONS

-- Xilinx products are not designed or intended to be fail-

-- safe, or for use in any application requiring fail-safe

-- performance, such as life-support or safety devices or

-- systems, Class III medical devices, nuclear facilities,

-- applications related to the deployment of airbags, or any

-- other applications that could lead to death, personal

-- injury, or severe property or environmental damage

-- (individually and collectively, "Critical

-- Applications"). Customer assumes the sole risk and

-- liability of any use of Xilinx products in Critical

-- Applications, subject only to applicable laws and

-- regulations governing limitations on product liability.

--

-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS

-- PART OF THIS FILE AT ALL TIMES.

--

------------------------------------------------------------------------------

-- User entered comments

------------------------------------------------------------------------------

-- None

--

------------------------------------------------------------------------------

-- "Output Output Phase Duty Pk-to-Pk Phase"

-- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"

------------------------------------------------------------------------------

-- CLK_OUT1____28.676______0.000______50.0______292.034____257.452

-- CLK_OUT2____57.353______0.000______50.0______239.345____257.452

--

------------------------------------------------------------------------------

-- "Input Clock Freq (MHz) Input Jitter (UI)"

------------------------------------------------------------------------------

-- __primary______________50____________0.010

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

use ieee.std_logic_arith.all;

use ieee.numeric_std.all;

library unisim;

use unisim.vcomponents.all;

entity pll is

port

(-- Clock in ports

CLKIN : in std_logic;

-- Clock out ports

CLKOUT : out std_logic;

CLKOUT2 : out std_logic;

-- Status and control signals

LOCKED : out std_logic

);

end pll;

architecture xilinx of pll is

attribute CORE_GENERATION_INFO : string;

attribute CORE_GENERATION_INFO of xilinx : architecture is "pll,clk_wiz_v3_6,{component_name=pll,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=PLL_BASE,num_out_clk=2,clkin1_period=20.000,clkin2_period=20.000,use_power_down=false,use_reset=false,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}";

-- Input clock buffering / unused connectors

signal clkin1 : std_logic;

-- Output clock buffering / unused connectors

signal clkfbout : std_logic;

signal clkfbout_buf : std_logic;

signal clkout0 : std_logic;

signal clkout1 : std_logic;

signal clkout2_unused : std_logic;

signal clkout3_unused : std_logic;

signal clkout4_unused : std_logic;

signal clkout5_unused : std_logic;

-- Unused status signals

begin

-- Input buffering

--------------------------------------

clkin1_buf : IBUFG

port map

(O => clkin1,

I => CLKIN);

-- Clocking primitive

--------------------------------------

-- Instantiation of the PLL primitive

-- * Unused inputs are tied off

-- * Unused outputs are labeled unused

pll_base_inst : PLL_BASE

generic map

(BANDWIDTH => "OPTIMIZED",

CLK_FEEDBACK => "CLKFBOUT",

COMPENSATION => "SYSTEM_SYNCHRONOUS",

DIVCLK_DIVIDE => 2,

CLKFBOUT_MULT => 39,

CLKFBOUT_PHASE => 0.000,

CLKOUT0_DIVIDE => 34,

CLKOUT0_PHASE => 0.000,

CLKOUT0_DUTY_CYCLE => 0.500,

CLKOUT1_DIVIDE => 17,

CLKOUT1_PHASE => 0.000,

CLKOUT1_DUTY_CYCLE => 0.500,

CLKIN_PERIOD => 20.000,

REF_JITTER => 0.010)

port map

-- Output clocks

(CLKFBOUT => clkfbout,

CLKOUT0 => clkout0,

CLKOUT1 => clkout1,

CLKOUT2 => clkout2_unused,

CLKOUT3 => clkout3_unused,

CLKOUT4 => clkout4_unused,

CLKOUT5 => clkout5_unused,

-- Status and control signals

LOCKED => LOCKED,

RST => '0',

-- Input clock control

CLKFBIN => clkfbout_buf,

CLKIN => clkin1);

-- Output buffering

-------------------------------------

clkf_buf : BUFG

port map

(O => clkfbout_buf,

I => clkfbout);

clkout1_buf : BUFG

port map

(O => CLKOUT,

I => clkout0);

clkout2_buf : BUFG

port map

(O => CLKOUT2,

I => clkout1);

end xilinx;

<?xml version="1.0" encoding="UTF-8" standalone="no" ?>

<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">

<!-- -->

<!-- For tool use only. Do not edit. -->

<!-- -->

<!-- ProjectNavigator created generated project file. -->

<!-- For use in tracking generated file and other information -->

<!-- allowing preservation of process status. -->

<!-- -->

<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->

<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>

<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="pll.xise"/>

<files xmlns="http://www.xilinx.com/XMLSchema">

<file xil_pn:fileType="FILE_ASY" xil_pn:name="pll.asy" xil_pn:origination="imported"/>

<file xil_pn:fileType="FILE_VHO" xil_pn:name="pll.vho" xil_pn:origination="imported"/>

</files>

<transforms xmlns="http://www.xilinx.com/XMLSchema"/>

</generated_project>

##

## Core Generator Run Script, generator for Project Navigator edit command

##

proc findRtfPath { relativePath } {

set xilenv ""

if { [info exists ::env(XILINX) ] } {

if { [info exists ::env(MYXILINX)] } {

set xilenv [join [list $::env(MYXILINX) $::env(XILINX)] $::xilinx::path_sep ]

} else {

set xilenv $::env(XILINX)

}

}

foreach path [ split $xilenv $::xilinx::path_sep ] {

set fullPath [ file join $path $relativePath ]

if { [ file exists $fullPath ] } {

return $fullPath

}

}

return ""

}

source [ findRtfPath "data/projnav/scripts/dpm_cgUtils.tcl" ]

set result [ run_cg_edit "pll" xc6slx9-3tqg144 VHDL ]

if { $result == 0 } {

puts "Core Generator edit command completed successfully."

} elseif { $result == 1 } {

puts "Core Generator edit command failed."

} elseif { $result == 3 || $result == 4 } {

# convert 'version check' result to real return range, bypassing any messages.

set result [ expr $result - 3 ]

} else {

puts "Core Generator edit cancelled."

}

exit $result

##############################################################

#

# Xilinx Core Generator version 14.7

# Date: Wed Jul 23 19:13:47 2014

#

##############################################################

#

# This file contains the customisation parameters for a

# Xilinx CORE Generator IP GUI. It is strongly recommended

# that you do not manually alter this file as it may cause

# unexpected and unsupported behavior.

#

##############################################################

#

# Generated from component: xilinx.com:ip:clk_wiz:3.6

#

##############################################################

#

# BEGIN Project Options

SET addpads = false

SET asysymbol = true

SET busformat = BusFormatAngleBracketNotRipped

SET createndf = false

SET designentry = VHDL

SET device = xc6slx9

SET devicefamily = spartan6

SET flowvendor = Other

SET formalverification = false

SET foundationsym = false

SET implementationfiletype = Ngc

SET package = tqg144

SET removerpms = false

SET simulationfiles = Behavioral

SET speedgrade = -3

SET verilogsim = false

SET vhdlsim = true

# END Project Options

# BEGIN Select

SELECT Clocking_Wizard xilinx.com:ip:clk_wiz:3.6

# END Select

# BEGIN Parameters

CSET calc_done=DONE

CSET clk_in_sel_port=CLK_IN_SEL

CSET clk_out1_port=CLKOUT

CSET clk_out1_use_fine_ps_gui=false

CSET clk_out2_port=CLKOUT2

CSET clk_out2_use_fine_ps_gui=false

CSET clk_out3_port=CLK_OUT3

CSET clk_out3_use_fine_ps_gui=false

CSET clk_out4_port=CLK_OUT4

CSET clk_out4_use_fine_ps_gui=false

CSET clk_out5_port=CLK_OUT5

CSET clk_out5_use_fine_ps_gui=false

CSET clk_out6_port=CLK_OUT6

CSET clk_out6_use_fine_ps_gui=false

CSET clk_out7_port=CLK_OUT7

CSET clk_out7_use_fine_ps_gui=false

CSET clk_valid_port=CLK_VALID

CSET clkfb_in_n_port=CLKFB_IN_N

CSET clkfb_in_p_port=CLKFB_IN_P

CSET clkfb_in_port=CLKFB_IN

CSET clkfb_in_signaling=SINGLE

CSET clkfb_out_n_port=CLKFB_OUT_N

CSET clkfb_out_p_port=CLKFB_OUT_P

CSET clkfb_out_port=CLKFB_OUT

CSET clkfb_stopped_port=CLKFB_STOPPED

CSET clkin1_jitter_ps=200.0

CSET clkin1_ui_jitter=0.010

CSET clkin2_jitter_ps=100.0

CSET clkin2_ui_jitter=0.010

CSET clkout1_drives=BUFG

CSET clkout1_requested_duty_cycle=50.000

CSET clkout1_requested_out_freq=28.64

CSET clkout1_requested_phase=0.000

CSET clkout2_drives=BUFG

CSET clkout2_requested_duty_cycle=50.000

CSET clkout2_requested_out_freq=57.28

CSET clkout2_requested_phase=0.000

CSET clkout2_used=true

CSET clkout3_drives=BUFG

CSET clkout3_requested_duty_cycle=50.000

CSET clkout3_requested_out_freq=100.000

CSET clkout3_requested_phase=0.000

CSET clkout3_used=false

CSET clkout4_drives=BUFG

CSET clkout4_requested_duty_cycle=50.000

CSET clkout4_requested_out_freq=100.000

CSET clkout4_requested_phase=0.000

CSET clkout4_used=false

CSET clkout5_drives=BUFG

CSET clkout5_requested_duty_cycle=50.000

CSET clkout5_requested_out_freq=100.000

CSET clkout5_requested_phase=0.000

CSET clkout5_used=false

CSET clkout6_drives=BUFG

CSET clkout6_requested_duty_cycle=50.000

CSET clkout6_requested_out_freq=100.000

CSET clkout6_requested_phase=0.000

CSET clkout6_used=false

CSET clkout7_drives=BUFG

CSET clkout7_requested_duty_cycle=50.000

CSET clkout7_requested_out_freq=100.000

CSET clkout7_requested_phase=0.000

CSET clkout7_used=false

CSET clock_mgr_type=AUTO

CSET component_name=pll

CSET daddr_port=DADDR

CSET dclk_port=DCLK

CSET dcm_clk_feedback=1X

CSET dcm_clk_out1_port=CLKFX

CSET dcm_clk_out2_port=CLK0

CSET dcm_clk_out3_port=CLK0

CSET dcm_clk_out4_port=CLK0

CSET dcm_clk_out5_port=CLK0

CSET dcm_clk_out6_port=CLK0

CSET dcm_clkdv_divide=2.0

CSET dcm_clkfx_divide=25

CSET dcm_clkfx_multiply=14

CSET dcm_clkgen_clk_out1_port=CLKFX

CSET dcm_clkgen_clk_out2_port=CLKFX

CSET dcm_clkgen_clk_out3_port=CLKFX

CSET dcm_clkgen_clkfx_divide=1

CSET dcm_clkgen_clkfx_md_max=0.000

CSET dcm_clkgen_clkfx_multiply=4

CSET dcm_clkgen_clkfxdv_divide=2

CSET dcm_clkgen_clkin_period=10.000

CSET dcm_clkgen_notes=None

CSET dcm_clkgen_spread_spectrum=NONE

CSET dcm_clkgen_startup_wait=false

CSET dcm_clkin_divide_by_2=false

CSET dcm_clkin_period=20.000

CSET dcm_clkout_phase_shift=NONE

CSET dcm_deskew_adjust=SYSTEM_SYNCHRONOUS

CSET dcm_notes=None

CSET dcm_phase_shift=0

CSET dcm_pll_cascade=NONE

CSET dcm_startup_wait=false

CSET den_port=DEN

CSET din_port=DIN

CSET dout_port=DOUT

CSET drdy_port=DRDY

CSET dwe_port=DWE

CSET feedback_source=FDBK_AUTO

CSET in_freq_units=Units_MHz

CSET in_jitter_units=Units_UI

CSET input_clk_stopped_port=INPUT_CLK_STOPPED

CSET jitter_options=UI

CSET jitter_sel=No_Jitter

CSET locked_port=LOCKED

CSET mmcm_bandwidth=OPTIMIZED

CSET mmcm_clkfbout_mult_f=4.000

CSET mmcm_clkfbout_phase=0.000

CSET mmcm_clkfbout_use_fine_ps=false

CSET mmcm_clkin1_period=10.000

CSET mmcm_clkin2_period=10.000

CSET mmcm_clkout0_divide_f=4.000

CSET mmcm_clkout0_duty_cycle=0.500

CSET mmcm_clkout0_phase=0.000

CSET mmcm_clkout0_use_fine_ps=false

CSET mmcm_clkout1_divide=1

CSET mmcm_clkout1_duty_cycle=0.500

CSET mmcm_clkout1_phase=0.000

CSET mmcm_clkout1_use_fine_ps=false

CSET mmcm_clkout2_divide=1

CSET mmcm_clkout2_duty_cycle=0.500

CSET mmcm_clkout2_phase=0.000

CSET mmcm_clkout2_use_fine_ps=false

CSET mmcm_clkout3_divide=1

CSET mmcm_clkout3_duty_cycle=0.500

CSET mmcm_clkout3_phase=0.000

CSET mmcm_clkout3_use_fine_ps=false

CSET mmcm_clkout4_cascade=false

CSET mmcm_clkout4_divide=1

CSET mmcm_clkout4_duty_cycle=0.500

CSET mmcm_clkout4_phase=0.000

CSET mmcm_clkout4_use_fine_ps=false

CSET mmcm_clkout5_divide=1

CSET mmcm_clkout5_duty_cycle=0.500

CSET mmcm_clkout5_phase=0.000

CSET mmcm_clkout5_use_fine_ps=false

CSET mmcm_clkout6_divide=1

CSET mmcm_clkout6_duty_cycle=0.500

CSET mmcm_clkout6_phase=0.000

CSET mmcm_clkout6_use_fine_ps=false

CSET mmcm_clock_hold=false

CSET mmcm_compensation=ZHOLD

CSET mmcm_divclk_divide=1

CSET mmcm_notes=None

CSET mmcm_ref_jitter1=0.010

CSET mmcm_ref_jitter2=0.010

CSET mmcm_startup_wait=false

CSET num_out_clks=2

CSET override_dcm=false

CSET override_dcm_clkgen=false

CSET override_mmcm=false

CSET override_pll=false

CSET platform=nt64

CSET pll_bandwidth=OPTIMIZED

CSET pll_clk_feedback=CLKFBOUT

CSET pll_clkfbout_mult=39

CSET pll_clkfbout_phase=0.000

CSET pll_clkin_period=20.000

CSET pll_clkout0_divide=34

CSET pll_clkout0_duty_cycle=0.500

CSET pll_clkout0_phase=0.000

CSET pll_clkout1_divide=17

CSET pll_clkout1_duty_cycle=0.500

CSET pll_clkout1_phase=0.000

CSET pll_clkout2_divide=1

CSET pll_clkout2_duty_cycle=0.500

CSET pll_clkout2_phase=0.000

CSET pll_clkout3_divide=1

CSET pll_clkout3_duty_cycle=0.500

CSET pll_clkout3_phase=0.000

CSET pll_clkout4_divide=1

CSET pll_clkout4_duty_cycle=0.500

CSET pll_clkout4_phase=0.000

CSET pll_clkout5_divide=1

CSET pll_clkout5_duty_cycle=0.500

CSET pll_clkout5_phase=0.000

CSET pll_compensation=SYSTEM_SYNCHRONOUS

CSET pll_divclk_divide=2

CSET pll_notes=None

CSET pll_ref_jitter=0.010

CSET power_down_port=POWER_DOWN

CSET prim_in_freq=50

CSET prim_in_jitter=0.010

CSET prim_source=Single_ended_clock_capable_pin

CSET primary_port=CLKIN

CSET primitive=MMCM

CSET primtype_sel=PLL_BASE

CSET psclk_port=PSCLK

CSET psdone_port=PSDONE

CSET psen_port=PSEN

CSET psincdec_port=PSINCDEC

CSET relative_inclk=REL_PRIMARY

CSET reset_port=RESET

CSET secondary_in_freq=100.000

CSET secondary_in_jitter=0.010

CSET secondary_port=CLK_IN2

CSET secondary_source=Single_ended_clock_capable_pin

CSET ss_mod_freq=250

CSET ss_mode=CENTER_HIGH

CSET status_port=STATUS

CSET summary_strings=empty

CSET use_clk_valid=false

CSET use_clkfb_stopped=false

CSET use_dyn_phase_shift=false

CSET use_dyn_reconfig=false

CSET use_freeze=false

CSET use_freq_synth=true

CSET use_inclk_stopped=false

CSET use_inclk_switchover=false

CSET use_locked=true

CSET use_max_i_jitter=false

CSET use_min_o_jitter=false

CSET use_min_power=false

CSET use_phase_alignment=true

CSET use_power_down=false

CSET use_reset=false

CSET use_spread_spectrum=false

CSET use_spread_spectrum_1=false

CSET use_status=false

# END Parameters

# BEGIN Extra information

MISC pkg_timestamp=2012-05-10T12:44:55Z

# END Extra information

GENERATE

# CRC: 51445c78

Version 4

SymbolType BLOCK

TEXT 32 32 LEFT 4 pll

RECTANGLE Normal 32 32 576 1088

LINE Normal 0 80 32 80

PIN 0 80 LEFT 36

PINATTR PinName clk_in1

PINATTR Polarity IN

LINE Normal 608 80 576 80

PIN 608 80 RIGHT 36

PINATTR PinName clk_out1

PINATTR Polarity OUT

LINE Normal 608 176 576 176

PIN 608 176 RIGHT 36

PINATTR PinName clk_out2

PINATTR Polarity OUT

LINE Normal 608 976 576 976

PIN 608 976 RIGHT 36

PINATTR PinName locked

PINATTR Polarity OUT

--

-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.

--

-- This file contains confidential and proprietary information

-- of Xilinx, Inc. and is protected under U.S. and

-- international copyright and other intellectual property

-- laws.

--

-- DISCLAIMER

-- This disclaimer is not a license and does not grant any

-- rights to the materials distributed herewith. Except as

-- otherwise provided in a valid license issued to you by

-- Xilinx, and to the maximum extent permitted by applicable

-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND

-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES

-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING

-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-

-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and

-- (2) Xilinx shall not be liable (whether in contract or tort,

-- including negligence, or under any other theory of

-- liability) for any loss or damage of any kind or nature

-- related to, arising under or in connection with these

-- materials, including for any direct, or any indirect,

-- special, incidental, or consequential loss or damage

-- (including loss of data, profits, goodwill, or any type of

-- loss or damage suffered as a result of any action brought

-- by a third party) even if such damage or loss was

-- reasonably foreseeable or Xilinx had been advised of the

-- possibility of the same.

--

-- CRITICAL APPLICATIONS

-- Xilinx products are not designed or intended to be fail-

-- safe, or for use in any application requiring fail-safe

-- performance, such as life-support or safety devices or

-- systems, Class III medical devices, nuclear facilities,

-- applications related to the deployment of airbags, or any

-- other applications that could lead to death, personal

-- injury, or severe property or environmental damage

-- (individually and collectively, "Critical

-- Applications"). Customer assumes the sole risk and

-- liability of any use of Xilinx products in Critical

-- Applications, subject only to applicable laws and

-- regulations governing limitations on product liability.

--

-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS

-- PART OF THIS FILE AT ALL TIMES.

--

------------------------------------------------------------------------------

-- User entered comments

------------------------------------------------------------------------------

-- None

--

------------------------------------------------------------------------------

-- "Output Output Phase Duty Pk-to-Pk Phase"

-- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"

------------------------------------------------------------------------------

-- CLK_OUT1____28.676______0.000______50.0______292.034____257.452

-- CLK_OUT2____57.353______0.000______50.0______239.345____257.452

--

------------------------------------------------------------------------------

-- "Input Clock Freq (MHz) Input Jitter (UI)"

------------------------------------------------------------------------------

-- __primary______________50____________0.010

-- The following code must appear in the VHDL architecture header:

------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG

component pll

port

(-- Clock in ports

CLKIN : in std_logic;

-- Clock out ports

CLKOUT : out std_logic;

CLKOUT2 : out std_logic;

-- Status and control signals

LOCKED : out std_logic

);

end component;

-- COMP_TAG_END ------ End COMPONENT Declaration ------------

-- The following code must appear in the VHDL architecture

-- body. Substitute your own instance name and net names.

------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG

your_instance_name : pll

port map

(-- Clock in ports

CLKIN => CLKIN,

-- Clock out ports

CLKOUT => CLKOUT,

CLKOUT2 => CLKOUT2,

-- Status and control signals

LOCKED => LOCKED);

-- INST_TAG_END ------ End INSTANTIATION Template ------------

# The package naming convention is <core_name>_xmdf

package provide pll_xmdf 1.0

# This includes some utilities that support common XMDF operations

package require utilities_xmdf

# Define a namespace for this package. The name of the name space

# is <core_name>_xmdf

namespace eval ::pll_xmdf {

# Use this to define any statics

}

# Function called by client to rebuild the params and port arrays

# Optional when the use context does not require the param or ports

# arrays to be available.

proc ::pll_xmdf::xmdfInit { instance } {

# Variable containg name of library into which module is compiled

# Recommendation: <module_name>

# Required

utilities_xmdf::xmdfSetData $instance Module Attributes Name pll

}

# ::pll_xmdf::xmdfInit

# Function called by client to fill in all the xmdf* data variables

# based on the current settings of the parameters

proc ::pll_xmdf::xmdfApplyParams { instance } {

set fcount 0

# Array containing libraries that are assumed to exist

# Examples include unisim and xilinxcorelib

# Optional

# In this example, we assume that the unisim library will

# be magically

# available to the simulation and synthesis tool

utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library

utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim

incr fcount

utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path pll/clk_wiz_readme.txt

utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore

incr fcount

utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path pll/doc/clk_wiz_ds709.pdf

utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore

incr fcount

utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path pll/doc/clk_wiz_gsg521.pdf

utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore

incr fcount

utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path pll/implement/implement.bat

utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore

incr fcount

utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path pll/implement/implement.sh

utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore

incr fcount

utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path pll/implement/xst.prj

utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore

incr fcount

utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path pll/implement/xst.scr

utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore

incr fcount

utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path pll/simulation/pll_tb.vhd

utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore

incr fcount

utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path pll/simulation/functional/simcmds.tcl

utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore

incr fcount

utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path pll/simulation/functional/simulate_isim.sh

utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore

incr fcount

utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path pll/simulation/functional/simulate_mti.do

utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore

incr fcount

utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path pll/simulation/functional/simulate_ncsim.sh

utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore

incr fcount

utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path pll/simulation/functional/wave.do

utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore

incr fcount

utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path pll/simulation/functional/wave.sv

utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore

incr fcount

utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path pll.asy

utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy

incr fcount

utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path pll.ejp

utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView

incr fcount

utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path pll.ucf

utilities_xmdf::xmdfSetData $instance FileSet $fcount type ucf

incr fcount

utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path pll.vhd

utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl

incr fcount

utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path pll.vho

utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl_template

incr fcount

utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path pll.xco

utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip

incr fcount

utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path pll_xmdf.tcl

utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView

incr fcount

utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module pll

incr fcount

}

# ::gen_comp_name_xmdf::xmdfApplyParams

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<PRE><FONT face="Arial, Helvetica, sans-serif" size="-1">

CHANGE LOG for LogiCORE Clocking Wizard V3.6

Release Date: June 19, 2013

--------------------------------------------------------------------------------

Table of Contents

1. INTRODUCTION

2. DEVICE SUPPORT

3. NEW FEATURE HISTORY

4. RESOLVED ISSUES

5. KNOWN ISSUES & LIMITATIONS

6. TECHNICAL SUPPORT & FEEDBACK

7. CORE RELEASE HISTORY

8. LEGAL DISCLAIMER

--------------------------------------------------------------------------------

1. INTRODUCTION

For installation instructions for this release, please go to:

<A HREF="http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm">www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm</A>

For system requirements:

<A HREF="http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm">www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm</A>

This file contains release notes for the Xilinx LogiCORE IP Clocking Wizard v3.6

solution. For the latest core updates, see the product page at:

<A HREF="http://www.xilinx.com/products/design_resources/conn_central/solution_kits/wizards/">www.xilinx.com/products/design_resources/conn_central/solution_kits/wizards/</A>

................................................................................

2. DEVICE SUPPORT

2.1 ISE

The following device families are supported by the core for this release.

All 7 Series devices

Zynq-7000 devices

Zynq-7000

Defense Grade Zynq-7000Q (XQ)

All Virtex-6 devices

All Spartan-6 devices

................................................................................

3. NEW FEATURE HISTORY

3.1 ISE

- Spread Spectrum support for 7 series MMCME2

- ISE 14.2 software support

................................................................................

4. RESOLVED ISSUES

4.1 ISE

Resolved issue with example design becoming core top in planAhead

Resolved issue with Virtex6 MMCM instantiation for VHDL project

Please refer to AR 50719 - <A HREF="http://www.xilinx.com/support/answers/50719.htm">www.xilinx.com/support/answers/50719.htm</A>

................................................................................

5. KNOWN ISSUES & LIMITATIONS

5.1 ISE

The most recent information, including known issues, workarounds, and

resolutions for this version is provided in the IP Release Notes Guide

located at

<A HREF="http://www.xilinx.com/support/documentation/user_guides/xtp025.pdf">www.xilinx.com/support/documentation/user_guides/xtp025.pdf</A>

................................................................................

6. TECHNICAL SUPPORT & FEEDBACK

To obtain technical support, create a WebCase at <A HREF="http://www.xilinx.com/support.">www.xilinx.com/support.</A>

Questions are routed to a team with expertise using this product.

Xilinx provides technical support for use of this product when used

according to the guidelines described in the core documentation, and

cannot guarantee timing, functionality, or support of this product for

designs that do not follow specified guidelines.

................................................................................

7. CORE RELEASE HISTORY

Date By Version Description

================================================================================

06/19/2013 Xilinx, Inc. 3.6(Rev3) ISE 14.6 support

10/16/2012 Xilinx, Inc. 3.6(Rev2) ISE 14.3 support

07/25/2012 Xilinx, Inc. 3.6 ISE 14.2 support

04/24/2012 Xilinx, Inc. 3.5 ISE 14.1 support

01/18/2012 Xilinx, Inc. 3.3 ISE 13.4 support

06/22/2011 Xilinx, Inc. 3.2 ISE 13.2 support

03/01/2011 Xilinx, Inc. 3.1 ISE 13.1 support

12/14/2010 Xilinx, Inc. 1.8 ISE 12.4 support

09/21/2010 Xilinx, Inc. 1.7 ISE 12.3 support

07/23/2010 Xilinx, Inc. 1.6 ISE 12.2 support

04/19/2010 Xilinx, Inc. 1.5 ISE 12.1 support

12/02/2009 Xilinx, Inc. 1.4 ISE 11.4 support

09/16/2009 Xilinx, Inc. 1.3 ISE 11.3 support

06/24/2009 Xilinx, Inc. 1.2 ISE 11.2 support

04/24/2009 Xilinx, Inc. 1.1 Initial release; 11.1 support

================================================================================

................................................................................

8. LEGAL DISCLAIMER

(c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.

This file contains confidential and proprietary information

of Xilinx, Inc. and is protected under U.S. and

international copyright and other intellectual property

laws.

DISCLAIMER

This disclaimer is not a license and does not grant any

rights to the materials distributed herewith. Except as

otherwise provided in a valid license issued to you by

Xilinx, and to the maximum extent permitted by applicable

law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND

WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES

AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING

BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-

INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and

(2) Xilinx shall not be liable (whether in contract or tort,

including negligence, or under any other theory of

liability) for any loss or damage of any kind or nature

related to, arising under or in connection with these

materials, including for any direct, or any indirect,

special, incidental, or consequential loss or damage

(including loss of data, profits, goodwill, or any type of

loss or damage suffered as a result of any action brought

by a third party) even if such damage or loss was

reasonably foreseeable or Xilinx had been advised of the

possibility of the same.

CRITICAL APPLICATIONS

Xilinx products are not designed or intended to be fail-

safe, or for use in any application requiring fail-safe

performance, such as life-support or safety devices or

systems, Class III medical devices, nuclear facilities,

applications related to the deployment of airbags, or any

other applications that could lead to death, personal

injury, or severe property or environmental damage

(individually and collectively, "Critical

Applications"). Customer assumes the sole risk and

liability of any use of Xilinx products in Critical

Applications, subject only to applicable laws and

regulations governing limitations on product liability.

THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS

PART OF THIS FILE AT ALL TIMES.

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CHANGE LOG for LogiCORE Clocking Wizard V3.6

Release Date: June 19, 2013

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Table of Contents

1. INTRODUCTION

2. DEVICE SUPPORT

3. NEW FEATURE HISTORY

4. RESOLVED ISSUES

5. KNOWN ISSUES & LIMITATIONS

6. TECHNICAL SUPPORT & FEEDBACK

7. CORE RELEASE HISTORY

8. LEGAL DISCLAIMER

--------------------------------------------------------------------------------

1. INTRODUCTION

For installation instructions for this release, please go to:

http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm

For system requirements:

http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm

This file contains release notes for the Xilinx LogiCORE IP Clocking Wizard v3.6

solution. For the latest core updates, see the product page at:

http://www.xilinx.com/products/design_resources/conn_central/solution_kits/wizards/

................................................................................

2. DEVICE SUPPORT

2.1 ISE