repo2/common/components/spi_master.vhd @ 321
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--
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-- FileName: spi_master.vhd
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-- Dependencies: none
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-- Design Software: Quartus II Version 9.0 Build 132 SJ Full Version
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--
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-- HDL CODE IS PROVIDED "AS IS." DIGI-KEY EXPRESSLY DISCLAIMS ANY
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-- WARRANTY OF ANY KIND, WHETHER EXPRESS OR IMPLIED, INCLUDING BUT NOT
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-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
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-- PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL DIGI-KEY
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-- BE LIABLE FOR ANY INCIDENTAL, SPECIAL, INDIRECT OR CONSEQUENTIAL
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-- DAMAGES, LOST PROFITS OR LOST DATA, HARM TO YOUR EQUIPMENT, COST OF
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-- PROCUREMENT OF SUBSTITUTE GOODS, TECHNOLOGY OR SERVICES, ANY CLAIMS
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-- BY THIRD PARTIES (INCLUDING BUT NOT LIMITED TO ANY DEFENSE THEREOF),
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-- ANY CLAIMS FOR INDEMNITY OR CONTRIBUTION, OR OTHER SIMILAR COSTS.
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--
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-- Version History
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-- Version 1.0 7/23/2010 Scott Larson
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-- Initial Public Release
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-- Version 1.1 4/11/2013 Scott Larson
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-- Corrected ModelSim simulation error (explicitly reset clk_toggles signal)
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--
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--------------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_arith.all;
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USE ieee.std_logic_unsigned.all;
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ENTITY spi_master IS
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GENERIC(
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slaves : INTEGER := 4; --number of spi slaves
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d_width : INTEGER := 2); --data bus width
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PORT(
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clock : IN STD_LOGIC; --system clock
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reset_n : IN STD_LOGIC; --asynchronous reset
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enable : IN STD_LOGIC; --initiate transaction
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cpol : IN STD_LOGIC; --spi clock polarity
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cpha : IN STD_LOGIC; --spi clock phase
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cont : IN STD_LOGIC; --continuous mode command
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clk_div : IN INTEGER; --system clock cycles per 1/2 period of sclk
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addr : IN INTEGER; --address of slave
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tx_data : IN STD_LOGIC_VECTOR(d_width-1 DOWNTO 0); --data to transmit
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miso : IN STD_LOGIC; --master in, slave out
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sclk : BUFFER STD_LOGIC; --spi clock
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ss_n : BUFFER STD_LOGIC_VECTOR(slaves-1 DOWNTO 0); --slave select
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mosi : OUT STD_LOGIC; --master out, slave in
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busy : OUT STD_LOGIC; --busy / data ready signal
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rx_data : OUT STD_LOGIC_VECTOR(d_width-1 DOWNTO 0)); --data received
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END spi_master;
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ARCHITECTURE logic OF spi_master IS
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TYPE machine IS(ready, execute); --state machine data type
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SIGNAL state : machine; --current state
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SIGNAL slave : INTEGER; --slave selected for current transaction
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SIGNAL clk_ratio : INTEGER; --current clk_div
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SIGNAL count : INTEGER; --counter to trigger sclk from system clock
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SIGNAL clk_toggles : INTEGER RANGE 0 TO d_width*2 + 1; --count spi clock toggles
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SIGNAL assert_data : STD_LOGIC; --'1' is tx sclk toggle, '0' is rx sclk toggle
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SIGNAL continue : STD_LOGIC; --flag to continue transaction
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SIGNAL rx_buffer : STD_LOGIC_VECTOR(d_width-1 DOWNTO 0); --receive data buffer
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SIGNAL tx_buffer : STD_LOGIC_VECTOR(d_width-1 DOWNTO 0); --transmit data buffer
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SIGNAL last_bit_rx : INTEGER RANGE 0 TO d_width*2; --last rx data bit location
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BEGIN
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PROCESS(clock, reset_n)
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BEGIN
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IF(reset_n = '0') THEN --reset system
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busy <= '1'; --set busy signal
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ss_n <= (OTHERS => '1'); --deassert all slave select lines
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mosi <= 'Z'; --set master out to high impedance
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rx_data <= (OTHERS => '0'); --clear receive data port
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state <= ready; --go to ready state when reset is exited
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ELSIF(clock'EVENT AND clock = '1') THEN
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CASE state IS --state machine
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WHEN ready =>
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busy <= '0'; --clock out not busy signal
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ss_n <= (OTHERS => '1'); --set all slave select outputs high
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mosi <= 'Z'; --set mosi output high impedance
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continue <= '0'; --clear continue flag
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--user input to initiate transaction
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IF(enable = '1') THEN
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busy <= '1'; --set busy signal
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IF(addr < slaves) THEN --check for valid slave address
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slave <= addr; --clock in current slave selection if valid
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ELSE
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slave <= 0; --set to first slave if not valid
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END IF;
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IF(clk_div = 0) THEN --check for valid spi speed
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clk_ratio <= 1; --set to maximum speed if zero
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count <= 1; --initiate system-to-spi clock counter
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ELSE
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clk_ratio <= clk_div; --set to input selection if valid
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count <= clk_div; --initiate system-to-spi clock counter
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END IF;
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sclk <= cpol; --set spi clock polarity
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assert_data <= NOT cpha; --set spi clock phase
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tx_buffer <= tx_data; --clock in data for transmit into buffer
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clk_toggles <= 0; --initiate clock toggle counter
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last_bit_rx <= d_width*2 + conv_integer(cpha) - 1; --set last rx data bit
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state <= execute; --proceed to execute state
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ELSE
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state <= ready; --remain in ready state
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END IF;
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WHEN execute =>
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busy <= '1'; --set busy signal
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ss_n(slave) <= '0'; --set proper slave select output
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--system clock to sclk ratio is met
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IF(count = clk_ratio) THEN
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count <= 1; --reset system-to-spi clock counter
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assert_data <= NOT assert_data; --switch transmit/receive indicator
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IF(clk_toggles = d_width*2 + 1) THEN
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clk_toggles <= 0; --reset spi clock toggles counter
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ELSE
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clk_toggles <= clk_toggles + 1; --increment spi clock toggles counter
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END IF;
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--spi clock toggle needed
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IF(clk_toggles <= d_width*2 AND ss_n(slave) = '0') THEN
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sclk <= NOT sclk; --toggle spi clock
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END IF;
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--receive spi clock toggle
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IF(assert_data = '0' AND clk_toggles < last_bit_rx + 1 AND ss_n(slave) = '0') THEN
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rx_buffer <= rx_buffer(d_width-2 DOWNTO 0) & miso; --shift in received bit
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END IF;
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--transmit spi clock toggle
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IF(assert_data = '1' AND clk_toggles < last_bit_rx) THEN
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mosi <= tx_buffer(d_width-1); --clock out data bit
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tx_buffer <= tx_buffer(d_width-2 DOWNTO 0) & '0'; --shift data transmit buffer
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END IF;
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--last data receive, but continue
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IF(clk_toggles = last_bit_rx AND cont = '1') THEN
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tx_buffer <= tx_data; --reload transmit buffer
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clk_toggles <= last_bit_rx - d_width*2 + 1; --reset spi clock toggle counter
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continue <= '1'; --set continue flag
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END IF;
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--normal end of transaction, but continue
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IF(continue = '1') THEN
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continue <= '0'; --clear continue flag
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busy <= '0'; --clock out signal that first receive data is ready
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rx_data <= rx_buffer; --clock out received data to output port
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END IF;
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--end of transaction
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IF((clk_toggles = d_width*2 + 1) AND cont = '0') THEN
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busy <= '0'; --clock out not busy signal
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ss_n <= (OTHERS => '1'); --set all slave selects high
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mosi <= 'Z'; --set mosi output high impedance
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rx_data <= rx_buffer; --clock out received data to output port
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state <= ready; --return to ready state
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ELSE --not end of transaction
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state <= execute; --remain in execute state
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END IF;
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ELSE --system clock to sclk ratio not met
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count <= count + 1; --increment counter
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state <= execute; --remain in execute state
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END IF;
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END CASE;
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END IF;
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END PROCESS;
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END logic;
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