repo2/common/components/scandouble_ram_infer.vhdl @ 321
| 1 | markw | ---------------------------------------------------------------------------
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-- (c) 2013 mark watson
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-- I am happy for anyone to use this for non-commercial use.
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-- If my vhdl files are used commercially or otherwise sold,
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-- please contact me for explicit permission at scrameta (gmail).
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-- This applies for source and binary form and derived works.
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---------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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ENTITY scandouble_ram_infer IS
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PORT
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(
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clock: IN std_logic;
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data: IN std_logic_vector (7 DOWNTO 0);
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address: IN integer RANGE 0 to 1824;
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we: IN std_logic;
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q: OUT std_logic_vector (7 DOWNTO 0)
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);
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END scandouble_ram_infer;
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ARCHITECTURE rtl OF scandouble_ram_infer IS
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TYPE mem IS ARRAY(0 TO 1824) OF std_logic_vector(7 DOWNTO 0); -- TODO need 455 but this leads to glitches in the hblank
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SIGNAL ram_block : mem;
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BEGIN
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PROCESS (clock)
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BEGIN
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IF (clock'event AND clock = '1') THEN
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IF (we = '1') THEN
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ram_block(address) <= data;
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END IF;
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q <= ram_block(address);
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END IF;
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END PROCESS;
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END rtl;
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