Revision 319
Added by markw over 10 years ago
| common/a8core/internalromram.vhd | ||
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PORT MAP(clock => clock,
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address => ram_addr,
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data => ram_data_in(7 downto 0),
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we => RAM_WR_ENABLE,
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we => RAM_WR_ENABLE and ram_request,
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q => ram_data
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);
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ram_request_complete <= ram_request_reg;
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Also available in: Unified diff
Fix write through problem