EclaireXL

# (C) 2001-2014 Altera Corporation. All rights reserved.

# Your use of Altera Corporation's design tools, logic functions and

# other software and tools, and its AMPP partner logic functions, and

# any output files any of the foregoing (including device programming

# or simulation files), and any associated documentation or information

# are expressly subject to the terms and conditions of the Altera

# Program License Subscription Agreement, Altera MegaCore Function

# License Agreement, or other applicable license agreement, including,

# without limitation, that your use is for the sole purpose of

# programming logic devices manufactured by Altera and sold by Altera

# or its authorized distributors. Please refer to the applicable

# agreement for further details.

# ACDS 14.0 200 linux 2014.12.14.13:40:56

# ----------------------------------------

# ncsim - auto-generated simulation script

# ----------------------------------------

# initialize variables

TOP_LEVEL_NAME="pll_pal"

QSYS_SIMDIR="./../"

QUARTUS_INSTALL_DIR="/home/markw/fpga/altera/14.0/quartus/"

SKIP_FILE_COPY=0

SKIP_DEV_COM=0

SKIP_COM=0

SKIP_ELAB=0

SKIP_SIM=0

USER_DEFINED_ELAB_OPTIONS=""

USER_DEFINED_SIM_OPTIONS="-input \"@run 100; exit\""

# ----------------------------------------

# overwrite variables - DO NOT MODIFY!

# This block evaluates each command line argument, typically used for

# overwriting variables. An example usage:

# sh <simulator>_setup.sh SKIP_ELAB=1 SKIP_SIM=1

for expression in "$@"; do

eval $expression

if [ $? -ne 0 ]; then

echo "Error: This command line argument, \"$expression\", is/has an invalid expression." >&2

exit $?

fi

done

# ----------------------------------------

# initialize simulation properties - DO NOT MODIFY!

ELAB_OPTIONS=""

SIM_OPTIONS=""

if [[ `ncsim -version` != *"ncsim(64)"* ]]; then

:

else

:

fi

# ----------------------------------------

# create compilation libraries

mkdir -p ./libraries/work/

mkdir -p ./libraries/altera/

mkdir -p ./libraries/lpm/

mkdir -p ./libraries/sgate/

mkdir -p ./libraries/altera_mf/

mkdir -p ./libraries/altera_lnsim/

mkdir -p ./libraries/cyclonev/

# ----------------------------------------

# copy RAM/ROM files to simulation directory

# ----------------------------------------

# compile device library files

if [ $SKIP_DEV_COM -eq 0 ]; then

ncvhdl -v93 "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_syn_attributes.vhd" -work altera

ncvhdl -v93 "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_standard_functions.vhd" -work altera

ncvhdl -v93 "$QUARTUS_INSTALL_DIR/eda/sim_lib/alt_dspbuilder_package.vhd" -work altera

ncvhdl -v93 "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_europa_support_lib.vhd" -work altera

ncvhdl -v93 "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives_components.vhd" -work altera

ncvhdl -v93 "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.vhd" -work altera

ncvhdl -v93 "$QUARTUS_INSTALL_DIR/eda/sim_lib/220pack.vhd" -work lpm

ncvhdl -v93 "$QUARTUS_INSTALL_DIR/eda/sim_lib/220model.vhd" -work lpm

ncvhdl -v93 "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate_pack.vhd" -work sgate

ncvhdl -v93 "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.vhd" -work sgate

ncvhdl -v93 "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf_components.vhd" -work altera_mf

ncvhdl -v93 "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.vhd" -work altera_mf

ncvlog -sv "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim.sv" -work altera_lnsim

ncvhdl -v93 "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim_components.vhd" -work altera_lnsim

ncvlog "$QUARTUS_INSTALL_DIR/eda/sim_lib/cadence/cyclonev_atoms_ncrypt.v" -work cyclonev

ncvhdl -v93 "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_atoms.vhd" -work cyclonev

ncvhdl -v93 "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_components.vhd" -work cyclonev

fi

# ----------------------------------------

# compile design files in correct order

if [ $SKIP_COM -eq 0 ]; then

ncvhdl -v93 "$QSYS_SIMDIR/pll_pal.vho"

fi

# ----------------------------------------

# elaborate top level design

if [ $SKIP_ELAB -eq 0 ]; then

ncelab -access +w+r+c -namemap_mixgen -relax $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS $TOP_LEVEL_NAME

fi

# ----------------------------------------

# simulate

if [ $SKIP_SIM -eq 0 ]; then

eval ncsim -licqueue $SIM_OPTIONS $USER_DEFINED_SIM_OPTIONS $TOP_LEVEL_NAME

fi

WORK > DEFAULT

DEFAULT: ./libraries/work/

work: ./libraries/work/

altera: ./libraries/altera/

lpm: ./libraries/lpm/

sgate: ./libraries/sgate/

altera_mf: ./libraries/altera_mf/

altera_lnsim: ./libraries/altera_lnsim/

cyclonev: ./libraries/cyclonev/

LIBRARY_SCAN = TRUE

component pll_pal is

port (

refclk : in std_logic := 'X'; -- clk

rst : in std_logic := 'X'; -- reset

outclk_0 : out std_logic; -- clk

locked : out std_logic -- export

);

end component pll_pal;

pot_from_signed.vhdl

sio_device.vhdl

-p xc6slx9-tqg144

ZPU_SD_CMD => open,

<WVObjectSize size="48" />

<wvobject fp_name="/antic_tb/antic1/dma_fetch_reg" type="logic" db_ref_id="1">

<obj_property name="ElementShortName">dma_fetch_reg</obj_property>

<obj_property name="ObjectShortName">dma_fetch_reg</obj_property>

</wvobject>

<wvobject fp_name="/antic_tb/antic1/dma_cache_ready_reg" type="logic" db_ref_id="1">

<obj_property name="ElementShortName">dma_cache_ready_reg</obj_property>

<obj_property name="ObjectShortName">dma_cache_ready_reg</obj_property>

</wvobject>

<wvobject fp_name="/antic_tb/antic1/load_display_shift_from_memory" type="logic" db_ref_id="1">

<obj_property name="ElementShortName">load_display_shift_from_memory</obj_property>

<obj_property name="ObjectShortName">load_display_shift_from_memory</obj_property>

</wvobject>

<wvobject fp_name="/antic_tb/antic1/dma_cache_next" type="array" db_ref_id="1">

<obj_property name="ElementShortName">dma_cache_next[7:0]</obj_property>

<obj_property name="ObjectShortName">dma_cache_next[7:0]</obj_property>

<obj_property name="Radix">HEXRADIX</obj_property>

</wvobject>

<wvobject fp_name="/antic_tb/antic1/dma_cache_reg" type="array" db_ref_id="1">

<obj_property name="ElementShortName">dma_cache_reg[7:0]</obj_property>

<obj_property name="ObjectShortName">dma_cache_reg[7:0]</obj_property>

<obj_property name="Radix">HEXRADIX</obj_property>

</wvobject>

<wvobject fp_name="/antic_tb/antic1/dma_fetch_destination_reg" type="array" db_ref_id="1">

<obj_property name="ElementShortName">dma_fetch_destination_reg[2:0]</obj_property>

<obj_property name="ObjectShortName">dma_fetch_destination_reg[2:0]</obj_property>

</wvobject>

<wvobject fp_name="/antic_tb/antic1/dma_fetch_destination_next" type="array" db_ref_id="1">

<obj_property name="ElementShortName">dma_fetch_destination_next[2:0]</obj_property>

<obj_property name="ObjectShortName">dma_fetch_destination_next[2:0]</obj_property>

</wvobject>

<wvobject fp_name="/antic_tb/antic1/antic_dma_clock1/playfield_start" type="logic" db_ref_id="1">

<obj_property name="ElementShortName">playfield_start</obj_property>

<obj_property name="ObjectShortName">playfield_start</obj_property>

</wvobject>

<wvobject fp_name="/antic_tb/antic1/antic_dma_clock1/dma_shiftreg_reg" type="array" db_ref_id="1">

<obj_property name="ElementShortName">dma_shiftreg_reg[7:0]</obj_property>

<obj_property name="ObjectShortName">dma_shiftreg_reg[7:0]</obj_property>

</wvobject>

<wvobject fp_name="/antic_tb/antic1/antic_dma_clock1/enable_dma" type="logic" db_ref_id="1">

<obj_property name="ElementShortName">enable_dma</obj_property>

<obj_property name="ObjectShortName">enable_dma</obj_property>

</wvobject>

<wvobject fp_name="/antic_tb/antic1/playfield_dma_start_shiftreg_next" type="array" db_ref_id="1">

<obj_property name="ElementShortName">playfield_dma_start_shiftreg_next[4:0]</obj_property>

<obj_property name="ObjectShortName">playfield_dma_start_shiftreg_next[4:0]</obj_property>

</wvobject>

<wvobject fp_name="/antic_tb/antic1/playfield_dma_start_shiftreg_reg" type="array" db_ref_id="1">

<obj_property name="ElementShortName">playfield_dma_start_shiftreg_reg[4:0]</obj_property>

<obj_property name="ObjectShortName">playfield_dma_start_shiftreg_reg[4:0]</obj_property>

</wvobject>

cpu_data_in <= x"62";

fetch_data(0) := x"42";

# `rm -rf $dir`;

# mkdir $dir;

# `cp atari5200core_mcc.vhd $dir`;

# `cp *pll*.* $dir`;

# `cp sdram_ctrl_3_ports.v $dir`;

# `cp zpu_rom.vhdl $dir`;

# `cp atari5200core.sdc $dir`;

# `mkdir $dir/common`;

# `mkdir $dir/common/a8core`;

# `mkdir $dir/common/components`;

# `mkdir $dir/common/zpu`;

# `mkdir $dir/svideo`;

# `cp ../common/a8core/* ./$dir/common/a8core`;

# `cp ../common/components/* ./$dir/common/components`;

# mkdir "./$dir/common/components/usbhostslave";

# `cp ../common/components/usbhostslave/trunk/RTL/*/*.v ./$dir/common/components/usbhostslave`;

# `cp ../common/zpu/* ./$dir/common/zpu`;

# `cp ./svideo/* ./$dir/svideo`;

# `../makeqsf ../atari5200core.qsf ./svideo ./common/a8core ./common/components ./common/zpu ./common/components/usbhostslave`;

# `quartus_sh --flow compile atari5200core > build.log 2> build.err`;

<output_filename>output_files/atari5200core.rbf</output_filename>

<sof_filename>output_files/atari5200core.sof<compress_bitstream>1</compress_bitstream></sof_filename>

--Copyright (C) 1991-2014 Altera Corporation. All rights reserved.

--Your use of Altera Corporation's design tools, logic functions

--and other software and tools, and its AMPP partner logic

--functions, and any output files from any of the foregoing

--(including device programming or simulation files), and any

--associated documentation or information are expressly subject

--to the terms and conditions of the Altera Program License

--Subscription Agreement, the Altera Quartus II License Agreement,

--the Altera MegaCore Function License Agreement, or other

--applicable license agreement, including, without limitation,

--that your use is for the sole purpose of programming logic

--devices manufactured by Altera and sold by Altera or its

--authorized distributors. Please refer to the applicable

--agreement for further details.

component altiobuf

PORT

(

datain : IN STD_LOGIC_VECTOR (3 DOWNTO 0);

oe : IN STD_LOGIC_VECTOR (3 DOWNTO 0);

oe_b : IN STD_LOGIC_VECTOR (3 DOWNTO 0);

dataio : INOUT STD_LOGIC_VECTOR (3 DOWNTO 0);

dataio_b : INOUT STD_LOGIC_VECTOR (3 DOWNTO 0);

dataout : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)

);

end component;

set_global_assignment -name IP_TOOL_NAME "ALTIOBUF"

set_global_assignment -name IP_TOOL_VERSION "14.0"

set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}"

set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altiobuf.vhd"]

set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altiobuf.cmp"]

-- megafunction wizard: %ALTIOBUF%

-- GENERATION: STANDARD

-- VERSION: WM1.0

-- MODULE: altiobuf_bidir

-- ============================================================

-- File Name: altiobuf.vhd

-- Megafunction Name(s):

-- altiobuf_bidir

--

-- Simulation Library Files(s):

-- altera_mf

-- ============================================================

-- ************************************************************

-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!

--

-- 14.0.0 Build 200 06/17/2014 SJ Web Edition

-- ************************************************************

--Copyright (C) 1991-2014 Altera Corporation. All rights reserved.

--Your use of Altera Corporation's design tools, logic functions

--and other software and tools, and its AMPP partner logic

--functions, and any output files from any of the foregoing

--(including device programming or simulation files), and any

--associated documentation or information are expressly subject

--to the terms and conditions of the Altera Program License

--Subscription Agreement, the Altera Quartus II License Agreement,

--the Altera MegaCore Function License Agreement, or other

--applicable license agreement, including, without limitation,

--that your use is for the sole purpose of programming logic

--devices manufactured by Altera and sold by Altera or its

--authorized distributors. Please refer to the applicable

--agreement for further details.

--altiobuf_bidir CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Cyclone V" ENABLE_BUS_HOLD="FALSE" NUMBER_OF_CHANNELS=4 OPEN_DRAIN_OUTPUT="FALSE" USE_DIFFERENTIAL_MODE="TRUE" USE_DYNAMIC_TERMINATION_CONTROL="FALSE" USE_TERMINATION_CONTROL="FALSE" datain dataio dataio_b dataout oe oe_b

--VERSION_BEGIN 14.0 cbx_altiobuf_bidir 2014:06:05:09:45:41:SJ cbx_mgl 2014:06:05:10:17:12:SJ cbx_stratixiii 2014:06:05:09:45:41:SJ cbx_stratixv 2014:06:05:09:45:41:SJ VERSION_END

LIBRARY cyclonev;

USE cyclonev.all;

--synthesis_resources = cyclonev_io_ibuf 4 cyclonev_io_obuf 8 cyclonev_pseudo_diff_out 4

LIBRARY ieee;

USE ieee.std_logic_1164.all;

ENTITY altiobuf_iobuf_bidir_lup IS

PORT

(

datain : IN STD_LOGIC_VECTOR (3 DOWNTO 0);

dataio : INOUT STD_LOGIC_VECTOR (3 DOWNTO 0);

dataio_b : INOUT STD_LOGIC_VECTOR (3 DOWNTO 0);

dataout : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);

oe : IN STD_LOGIC_VECTOR (3 DOWNTO 0);

oe_b : IN STD_LOGIC_VECTOR (3 DOWNTO 0) := (OTHERS => '1')

);

END altiobuf_iobuf_bidir_lup;

ARCHITECTURE RTL OF altiobuf_iobuf_bidir_lup IS

SIGNAL wire_ibufa_i : STD_LOGIC_VECTOR (3 DOWNTO 0);

SIGNAL wire_ibufa_ibar : STD_LOGIC_VECTOR (3 DOWNTO 0);

SIGNAL wire_ibufa_o : STD_LOGIC_VECTOR (3 DOWNTO 0);

SIGNAL wire_obuf_ba_o : STD_LOGIC_VECTOR (3 DOWNTO 0);

SIGNAL wire_obuf_ba_oe : STD_LOGIC_VECTOR (3 DOWNTO 0);

SIGNAL wire_obufa_o : STD_LOGIC_VECTOR (3 DOWNTO 0);

SIGNAL wire_obufa_oe : STD_LOGIC_VECTOR (3 DOWNTO 0);

SIGNAL wire_pseudo_diffa_w_lg_oebout3w : STD_LOGIC_VECTOR (3 DOWNTO 0);

SIGNAL wire_pseudo_diffa_w_lg_oeout2w : STD_LOGIC_VECTOR (3 DOWNTO 0);

SIGNAL wire_pseudo_diffa_i : STD_LOGIC_VECTOR (3 DOWNTO 0);

SIGNAL wire_pseudo_diffa_o : STD_LOGIC_VECTOR (3 DOWNTO 0);

SIGNAL wire_pseudo_diffa_obar : STD_LOGIC_VECTOR (3 DOWNTO 0);

SIGNAL wire_pseudo_diffa_oebout : STD_LOGIC_VECTOR (3 DOWNTO 0);

SIGNAL wire_pseudo_diffa_oein : STD_LOGIC_VECTOR (3 DOWNTO 0);

SIGNAL wire_pseudo_diffa_oeout : STD_LOGIC_VECTOR (3 DOWNTO 0);

SIGNAL wire_w_lg_oe1w : STD_LOGIC_VECTOR (3 DOWNTO 0);

COMPONENT cyclonev_io_ibuf

GENERIC

(

bus_hold : STRING := "false";

differential_mode : STRING := "false";

simulate_z_as : STRING := "z";

lpm_type : STRING := "cyclonev_io_ibuf"

);

PORT

(

dynamicterminationcontrol : IN STD_LOGIC := '0';

i : IN STD_LOGIC := '0';

ibar : IN STD_LOGIC := '0';

o : OUT STD_LOGIC

);

END COMPONENT;

COMPONENT cyclonev_io_obuf

GENERIC

(

bus_hold : STRING := "false";

open_drain_output : STRING := "false";

shift_series_termination_control : STRING := "false";

lpm_type : STRING := "cyclonev_io_obuf"

);

PORT

(

dynamicterminationcontrol : IN STD_LOGIC := '0';

i : IN STD_LOGIC := '0';

o : OUT STD_LOGIC;

obar : OUT STD_LOGIC;

oe : IN STD_LOGIC := '1';

parallelterminationcontrol : IN STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0');

seriesterminationcontrol : IN STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0')

);

END COMPONENT;

COMPONENT cyclonev_pseudo_diff_out

PORT

(

dtc : OUT STD_LOGIC;

dtcbar : OUT STD_LOGIC;

dtcin : IN STD_LOGIC := '0';

i : IN STD_LOGIC := '0';

o : OUT STD_LOGIC;

obar : OUT STD_LOGIC;

oebout : OUT STD_LOGIC;

oein : IN STD_LOGIC := '0';

oeout : OUT STD_LOGIC

);

END COMPONENT;

BEGIN

loop0 : FOR i IN 0 TO 3 GENERATE

wire_w_lg_oe1w(i) <= NOT oe(i);

END GENERATE loop0;

dataio <= wire_obufa_o;

dataio_b <= wire_obuf_ba_o;

dataout <= wire_ibufa_o;

wire_ibufa_i <= dataio;

wire_ibufa_ibar <= dataio_b;

loop1 : FOR i IN 0 TO 3 GENERATE

ibufa : cyclonev_io_ibuf

GENERIC MAP (

bus_hold => "false",

differential_mode => "true"

)

PORT MAP (

i => wire_ibufa_i(i),

ibar => wire_ibufa_ibar(i),

o => wire_ibufa_o(i)

);

END GENERATE loop1;

wire_obuf_ba_oe <= wire_pseudo_diffa_w_lg_oebout3w;

loop2 : FOR i IN 0 TO 3 GENERATE

obuf_ba : cyclonev_io_obuf

GENERIC MAP (

bus_hold => "false",

open_drain_output => "false"

)

PORT MAP (

i => wire_pseudo_diffa_obar(i),

o => wire_obuf_ba_o(i),

oe => wire_obuf_ba_oe(i)

);

END GENERATE loop2;

wire_obufa_oe <= wire_pseudo_diffa_w_lg_oeout2w;

loop3 : FOR i IN 0 TO 3 GENERATE

obufa : cyclonev_io_obuf

GENERIC MAP (

bus_hold => "false",

open_drain_output => "false"

)

PORT MAP (

i => wire_pseudo_diffa_o(i),

o => wire_obufa_o(i),

oe => wire_obufa_oe(i)

);

END GENERATE loop3;

loop4 : FOR i IN 0 TO 3 GENERATE

wire_pseudo_diffa_w_lg_oebout3w(i) <= NOT wire_pseudo_diffa_oebout(i);

END GENERATE loop4;

loop5 : FOR i IN 0 TO 3 GENERATE

wire_pseudo_diffa_w_lg_oeout2w(i) <= NOT wire_pseudo_diffa_oeout(i);

END GENERATE loop5;

wire_pseudo_diffa_i <= datain;

wire_pseudo_diffa_oein <= wire_w_lg_oe1w;

loop6 : FOR i IN 0 TO 3 GENERATE

pseudo_diffa : cyclonev_pseudo_diff_out

PORT MAP (

i => wire_pseudo_diffa_i(i),

o => wire_pseudo_diffa_o(i),

obar => wire_pseudo_diffa_obar(i),

oebout => wire_pseudo_diffa_oebout(i),

oein => wire_pseudo_diffa_oein(i),

oeout => wire_pseudo_diffa_oeout(i)

);

END GENERATE loop6;

END RTL; --altiobuf_iobuf_bidir_lup

--VALID FILE

LIBRARY ieee;

USE ieee.std_logic_1164.all;

ENTITY altiobuf IS

PORT

(

datain : IN STD_LOGIC_VECTOR (3 DOWNTO 0);

oe : IN STD_LOGIC_VECTOR (3 DOWNTO 0);

oe_b : IN STD_LOGIC_VECTOR (3 DOWNTO 0);

dataio : INOUT STD_LOGIC_VECTOR (3 DOWNTO 0);

dataio_b : INOUT STD_LOGIC_VECTOR (3 DOWNTO 0);

dataout : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)

);

END altiobuf;

ARCHITECTURE RTL OF altiobuf IS

SIGNAL sub_wire0 : STD_LOGIC_VECTOR (3 DOWNTO 0);

COMPONENT altiobuf_iobuf_bidir_lup

PORT (

datain : IN STD_LOGIC_VECTOR (3 DOWNTO 0);

oe : IN STD_LOGIC_VECTOR (3 DOWNTO 0);

oe_b : IN STD_LOGIC_VECTOR (3 DOWNTO 0);

dataout : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);

dataio : INOUT STD_LOGIC_VECTOR (3 DOWNTO 0);

dataio_b : INOUT STD_LOGIC_VECTOR (3 DOWNTO 0)

);

END COMPONENT;

BEGIN

dataout <= sub_wire0(3 DOWNTO 0);

altiobuf_iobuf_bidir_lup_component : altiobuf_iobuf_bidir_lup

PORT MAP (

datain => datain,

oe => oe,

oe_b => oe_b,

dataout => sub_wire0,

dataio => dataio,

dataio_b => dataio_b

);

END RTL;

-- ============================================================

-- CNX file retrieval info

-- ============================================================

-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"

-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"

-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all

-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"

-- Retrieval info: CONSTANT: enable_bus_hold STRING "FALSE"

-- Retrieval info: CONSTANT: left_shift_series_termination_control STRING "FALSE"

-- Retrieval info: CONSTANT: number_of_channels NUMERIC "4"

-- Retrieval info: CONSTANT: open_drain_output STRING "FALSE"

-- Retrieval info: CONSTANT: use_differential_mode STRING "TRUE"

-- Retrieval info: CONSTANT: use_dynamic_termination_control STRING "FALSE"

-- Retrieval info: CONSTANT: use_termination_control STRING "FALSE"

-- Retrieval info: USED_PORT: datain 0 0 4 0 INPUT NODEFVAL "datain[3..0]"

-- Retrieval info: USED_PORT: dataio 0 0 4 0 BIDIR NODEFVAL "dataio[3..0]"

-- Retrieval info: USED_PORT: dataio_b 0 0 4 0 BIDIR NODEFVAL "dataio_b[3..0]"

-- Retrieval info: USED_PORT: dataout 0 0 4 0 OUTPUT NODEFVAL "dataout[3..0]"

-- Retrieval info: USED_PORT: oe 0 0 4 0 INPUT NODEFVAL "oe[3..0]"

-- Retrieval info: USED_PORT: oe_b 0 0 4 0 INPUT NODEFVAL "oe_b[3..0]"

-- Retrieval info: CONNECT: @datain 0 0 4 0 datain 0 0 4 0

-- Retrieval info: CONNECT: @oe 0 0 4 0 oe 0 0 4 0

-- Retrieval info: CONNECT: @oe_b 0 0 4 0 oe_b 0 0 4 0

-- Retrieval info: CONNECT: dataio 0 0 4 0 @dataio 0 0 4 0

-- Retrieval info: CONNECT: dataio_b 0 0 4 0 @dataio_b 0 0 4 0

-- Retrieval info: CONNECT: dataout 0 0 4 0 @dataout 0 0 4 0

-- Retrieval info: GEN_FILE: TYPE_NORMAL altiobuf.vhd TRUE

-- Retrieval info: GEN_FILE: TYPE_NORMAL altiobuf.inc FALSE

-- Retrieval info: GEN_FILE: TYPE_NORMAL altiobuf.cmp TRUE

-- Retrieval info: GEN_FILE: TYPE_NORMAL altiobuf.bsf FALSE

-- Retrieval info: GEN_FILE: TYPE_NORMAL altiobuf_inst.vhd FALSE

-- Retrieval info: LIB_FILE: altera_mf

--Copyright (C) 1991-2014 Altera Corporation. All rights reserved.

--Your use of Altera Corporation's design tools, logic functions

--and other software and tools, and its AMPP partner logic

--functions, and any output files from any of the foregoing

--(including device programming or simulation files), and any

--associated documentation or information are expressly subject

--to the terms and conditions of the Altera Program License

--Subscription Agreement, the Altera Quartus II License Agreement,

--the Altera MegaCore Function License Agreement, or other

--applicable license agreement, including, without limitation,

--that your use is for the sole purpose of programming logic

--devices manufactured by Altera and sold by Altera or its

--authorized distributors. Please refer to the applicable

--agreement for further details.

component altiobufo

PORT

(

datain : IN STD_LOGIC_VECTOR (0 DOWNTO 0);

oe : IN STD_LOGIC_VECTOR (0 DOWNTO 0);

oe_b : IN STD_LOGIC_VECTOR (0 DOWNTO 0);

dataout : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);

dataout_b : OUT STD_LOGIC_VECTOR (0 DOWNTO 0)

);

end component;

set_global_assignment -name IP_TOOL_NAME "ALTIOBUF"

set_global_assignment -name IP_TOOL_VERSION "14.0"

set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}"

set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altiobufo.vhd"]

set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altiobufo.cmp"]

-- megafunction wizard: %ALTIOBUF%

-- GENERATION: STANDARD

-- VERSION: WM1.0

-- MODULE: altiobuf_out

-- ============================================================

-- File Name: altiobufo.vhd

-- Megafunction Name(s):

-- altiobuf_out

--

-- Simulation Library Files(s):

-- cyclonev

-- ============================================================

-- ************************************************************

-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!

--

-- 14.0.0 Build 200 06/17/2014 SJ Web Edition

-- ************************************************************

--Copyright (C) 1991-2014 Altera Corporation. All rights reserved.

--Your use of Altera Corporation's design tools, logic functions

--and other software and tools, and its AMPP partner logic

--functions, and any output files from any of the foregoing

--(including device programming or simulation files), and any

--associated documentation or information are expressly subject

--to the terms and conditions of the Altera Program License

--Subscription Agreement, the Altera Quartus II License Agreement,

--the Altera MegaCore Function License Agreement, or other

--applicable license agreement, including, without limitation,

--that your use is for the sole purpose of programming logic

--devices manufactured by Altera and sold by Altera or its

--authorized distributors. Please refer to the applicable

--agreement for further details.

--altiobuf_out CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Cyclone V" ENABLE_BUS_HOLD="FALSE" LEFT_SHIFT_SERIES_TERMINATION_CONTROL="FALSE" NUMBER_OF_CHANNELS=1 OPEN_DRAIN_OUTPUT="FALSE" PSEUDO_DIFFERENTIAL_MODE="TRUE" USE_DIFFERENTIAL_MODE="TRUE" USE_OE="TRUE" USE_TERMINATION_CONTROL="FALSE" datain dataout dataout_b oe oe_b

--VERSION_BEGIN 14.0 cbx_altiobuf_out 2014:06:05:09:45:41:SJ cbx_mgl 2014:06:05:10:17:12:SJ cbx_stratixiii 2014:06:05:09:45:41:SJ cbx_stratixv 2014:06:05:09:45:41:SJ VERSION_END

LIBRARY cyclonev;

USE cyclonev.all;

--synthesis_resources = cyclonev_io_obuf 2 cyclonev_pseudo_diff_out 1

LIBRARY ieee;

USE ieee.std_logic_1164.all;

ENTITY altiobufo_iobuf_out_h5u IS

PORT

(

datain : IN STD_LOGIC_VECTOR (0 DOWNTO 0);

dataout : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);

dataout_b : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);

oe : IN STD_LOGIC_VECTOR (0 DOWNTO 0) := (OTHERS => '1');

oe_b : IN STD_LOGIC_VECTOR (0 DOWNTO 0) := (OTHERS => '1')

);

END altiobufo_iobuf_out_h5u;

ARCHITECTURE RTL OF altiobufo_iobuf_out_h5u IS

SIGNAL wire_obuf_ba_o : STD_LOGIC;

SIGNAL wire_obuf_ba_oe : STD_LOGIC_VECTOR (0 DOWNTO 0);

SIGNAL wire_pseudo_diffa_w_lg_oebout3w : STD_LOGIC_VECTOR (0 DOWNTO 0);

SIGNAL wire_obufa_o : STD_LOGIC;

SIGNAL wire_obufa_oe : STD_LOGIC_VECTOR (0 DOWNTO 0);

SIGNAL wire_pseudo_diffa_w_lg_oeout2w : STD_LOGIC_VECTOR (0 DOWNTO 0);

SIGNAL wire_pseudo_diffa_o : STD_LOGIC;

SIGNAL wire_pseudo_diffa_obar : STD_LOGIC;

SIGNAL wire_pseudo_diffa_oebout : STD_LOGIC;

SIGNAL wire_pseudo_diffa_oein : STD_LOGIC_VECTOR (0 DOWNTO 0);

SIGNAL wire_w_lg_oe_w1w : STD_LOGIC_VECTOR (0 DOWNTO 0);

SIGNAL wire_pseudo_diffa_oeout : STD_LOGIC;

SIGNAL oe_w : STD_LOGIC_VECTOR (0 DOWNTO 0);

COMPONENT cyclonev_io_obuf

GENERIC

(

bus_hold : STRING := "false";

open_drain_output : STRING := "false";

shift_series_termination_control : STRING := "false";

lpm_type : STRING := "cyclonev_io_obuf"

);

PORT

(

dynamicterminationcontrol : IN STD_LOGIC := '0';

i : IN STD_LOGIC := '0';

o : OUT STD_LOGIC;

obar : OUT STD_LOGIC;

oe : IN STD_LOGIC := '1';

parallelterminationcontrol : IN STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0');

seriesterminationcontrol : IN STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0')

);

END COMPONENT;

COMPONENT cyclonev_pseudo_diff_out

PORT

(

dtc : OUT STD_LOGIC;

dtcbar : OUT STD_LOGIC;

dtcin : IN STD_LOGIC := '0';

i : IN STD_LOGIC := '0';

o : OUT STD_LOGIC;

obar : OUT STD_LOGIC;

oebout : OUT STD_LOGIC;

oein : IN STD_LOGIC := '0';

oeout : OUT STD_LOGIC

);

END COMPONENT;

BEGIN

dataout(0) <= wire_obufa_o;

dataout_b(0) <= wire_obuf_ba_o;

oe_w <= oe;

wire_obuf_ba_oe <= wire_pseudo_diffa_w_lg_oebout3w;

wire_pseudo_diffa_w_lg_oebout3w(0) <= NOT wire_pseudo_diffa_oebout;

obuf_ba : cyclonev_io_obuf

GENERIC MAP (

bus_hold => "false",

open_drain_output => "false"

)

PORT MAP (

i => wire_pseudo_diffa_obar,

o => wire_obuf_ba_o,

oe => wire_obuf_ba_oe(0)

);

wire_obufa_oe <= wire_pseudo_diffa_w_lg_oeout2w;

wire_pseudo_diffa_w_lg_oeout2w(0) <= NOT wire_pseudo_diffa_oeout;

obufa : cyclonev_io_obuf

GENERIC MAP (

bus_hold => "false",

open_drain_output => "false"

)

PORT MAP (

i => wire_pseudo_diffa_o,

o => wire_obufa_o,

oe => wire_obufa_oe(0)

);

wire_pseudo_diffa_oein <= wire_w_lg_oe_w1w;

wire_w_lg_oe_w1w(0) <= NOT oe_w(0);

pseudo_diffa : cyclonev_pseudo_diff_out

PORT MAP (

i => datain(0),

o => wire_pseudo_diffa_o,

obar => wire_pseudo_diffa_obar,

oebout => wire_pseudo_diffa_oebout,

oein => wire_pseudo_diffa_oein(0),

oeout => wire_pseudo_diffa_oeout

);

END RTL; --altiobufo_iobuf_out_h5u

--VALID FILE

LIBRARY ieee;

USE ieee.std_logic_1164.all;

ENTITY altiobufo IS

PORT

(

datain : IN STD_LOGIC_VECTOR (0 DOWNTO 0);

oe : IN STD_LOGIC_VECTOR (0 DOWNTO 0);

oe_b : IN STD_LOGIC_VECTOR (0 DOWNTO 0);

dataout : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);

dataout_b : OUT STD_LOGIC_VECTOR (0 DOWNTO 0)

);

END altiobufo;

ARCHITECTURE RTL OF altiobufo IS

SIGNAL sub_wire0 : STD_LOGIC_VECTOR (0 DOWNTO 0);

SIGNAL sub_wire1 : STD_LOGIC_VECTOR (0 DOWNTO 0);

COMPONENT altiobufo_iobuf_out_h5u

PORT (

datain : IN STD_LOGIC_VECTOR (0 DOWNTO 0);

oe : IN STD_LOGIC_VECTOR (0 DOWNTO 0);

oe_b : IN STD_LOGIC_VECTOR (0 DOWNTO 0);

dataout : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);

dataout_b : OUT STD_LOGIC_VECTOR (0 DOWNTO 0)

);

END COMPONENT;

BEGIN

dataout <= sub_wire0(0 DOWNTO 0);

dataout_b <= sub_wire1(0 DOWNTO 0);

altiobufo_iobuf_out_h5u_component : altiobufo_iobuf_out_h5u

PORT MAP (

datain => datain,

oe => oe,

oe_b => oe_b,

dataout => sub_wire0,

dataout_b => sub_wire1

);

END RTL;

-- ============================================================

-- CNX file retrieval info

-- ============================================================

-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"

-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"

-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all

-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"

-- Retrieval info: CONSTANT: enable_bus_hold STRING "FALSE"

-- Retrieval info: CONSTANT: left_shift_series_termination_control STRING "FALSE"

-- Retrieval info: CONSTANT: number_of_channels NUMERIC "1"

-- Retrieval info: CONSTANT: open_drain_output STRING "FALSE"

-- Retrieval info: CONSTANT: pseudo_differential_mode STRING "TRUE"

-- Retrieval info: CONSTANT: use_differential_mode STRING "TRUE"

-- Retrieval info: CONSTANT: use_oe STRING "TRUE"

-- Retrieval info: CONSTANT: use_termination_control STRING "FALSE"

-- Retrieval info: USED_PORT: datain 0 0 1 0 INPUT NODEFVAL "datain[0..0]"

-- Retrieval info: USED_PORT: dataout 0 0 1 0 OUTPUT NODEFVAL "dataout[0..0]"

-- Retrieval info: USED_PORT: dataout_b 0 0 1 0 OUTPUT NODEFVAL "dataout_b[0..0]"

-- Retrieval info: USED_PORT: oe 0 0 1 0 INPUT NODEFVAL "oe[0..0]"

-- Retrieval info: USED_PORT: oe_b 0 0 1 0 INPUT NODEFVAL "oe_b[0..0]"

-- Retrieval info: CONNECT: @datain 0 0 1 0 datain 0 0 1 0

-- Retrieval info: CONNECT: @oe 0 0 1 0 oe 0 0 1 0

-- Retrieval info: CONNECT: @oe_b 0 0 1 0 oe_b 0 0 1 0

-- Retrieval info: CONNECT: dataout 0 0 1 0 @dataout 0 0 1 0

-- Retrieval info: CONNECT: dataout_b 0 0 1 0 @dataout_b 0 0 1 0

-- Retrieval info: GEN_FILE: TYPE_NORMAL altiobufo.vhd TRUE

-- Retrieval info: GEN_FILE: TYPE_NORMAL altiobufo.inc FALSE

-- Retrieval info: GEN_FILE: TYPE_NORMAL altiobufo.cmp TRUE

-- Retrieval info: GEN_FILE: TYPE_NORMAL altiobufo.bsf FALSE

-- Retrieval info: GEN_FILE: TYPE_NORMAL altiobufo_inst.vhd FALSE

-- Retrieval info: LIB_FILE: cyclonev

<html>

<body>

<h1 align="center">Cylone V SoC FPGA Board Configuration</h1>

<br />

<br />

<h2 align="left">Pin Assignments:</h2>

<ul>

<a href="#CLOCK"><li>CLOCK</li></a>

<br />

<a href="#LED"><li>LED</li></a>

<br />

<a href="#KEY"><li>KEY</li></a>

<br />

<a href="#SW"><li>SW</li></a>

<br />

<a href="#Si5338"><li>Si5338</li></a>

<br />

<a href="#Temperature"><li>Temperature</li></a>

<br />

<a href="#VGA"><li>VGA</li></a>

<br />

<a href="#Audio"><li>Audio</li></a>

<br />

<a href="#I2C for Audio "><li>I2C for Audio </li></a>

<br />

<a href="#SDRAM"><li>SDRAM</li></a>

<br />

<a href="#HSMC"><li>HSMC</li></a>

<br />

</ul>

<br />

<br />

<br />

<h2 align="left">Pin Assignment Table:</h2>

<h2><a name="CLOCK"></a></h2><table border="3">

<caption align="left">CLOCK</caption>

<br />

<br />

<tr>

<th align="left" bgcolor="Khaki">Name</th>

<th align="left" bgcolor="Khaki">Location</th>

<th align="left" bgcolor="Khaki">Direction</th>

<th align="left" bgcolor="Khaki">Standard</th>

</tr>

<tr>

<td align="left">OSC_50_B3B</td>

<td align="left">AF14</td>

<td align="left">input </td>

<td align="left">1.5 V</td>

</tr>

<tr>

<td align="left">OSC_50_B4A</td>

<td align="left">AA16</td>

<td align="left">input </td>

<td align="left">1.5 V</td>

</tr>

<tr>

<td align="left">OSC_50_B5B</td>

<td align="left">Y26</td>

<td align="left">input </td>

<td align="left">2.5 V</td>

</tr>

<tr>

<td align="left">OSC_50_B8A</td>

<td align="left">K14</td>

<td align="left">input </td>

<td align="left">2.5 V</td>

</tr>

</table>

<h2><a name="LED"></a></h2><table border="3">

<caption align="left">LED</caption>

<br />

<br />

<tr>

<th align="left" bgcolor="Khaki">Name</th>

<th align="left" bgcolor="Khaki">Location</th>

<th align="left" bgcolor="Khaki">Direction</th>

<th align="left" bgcolor="Khaki">Standard</th>

</tr>

<tr>

<td align="left">LED[0]</td>

<td align="left">AF10</td>

<td align="left">output</td>

<td align="left">3.3-V LVTTL</td>

</tr>

<tr>

<td align="left">LED[1]</td>

<td align="left">AD10</td>

<td align="left">output</td>

<td align="left">3.3-V LVTTL</td>

</tr>

<tr>

<td align="left">LED[2]</td>

<td align="left">AE11</td>

<td align="left">output</td>

<td align="left">3.3-V LVTTL</td>

</tr>

<tr>

<td align="left">LED[3]</td>

<td align="left">AD7</td>

<td align="left">output</td>

<td align="left">3.3-V LVTTL</td>

</tr>

</table>

<h2><a name="KEY"></a></h2><table border="3">

<caption align="left">KEY</caption>

<br />

<br />

<tr>

<th align="left" bgcolor="Khaki">Name</th>

<th align="left" bgcolor="Khaki">Location</th>

<th align="left" bgcolor="Khaki">Direction</th>

<th align="left" bgcolor="Khaki">Standard</th>

</tr>

<tr>

<td align="left">KEY[0]</td>

<td align="left">AE9</td>

<td align="left">input </td>

<td align="left">3.3-V LVTTL</td>

</tr>

<tr>

<td align="left">KEY[1]</td>

<td align="left">AE12</td>

<td align="left">input </td>

<td align="left">3.3-V LVTTL</td>

</tr>

<tr>

<td align="left">KEY[2]</td>

<td align="left">AD9</td>

<td align="left">input </td>

<td align="left">3.3-V LVTTL</td>

</tr>

<tr>

<td align="left">KEY[3]</td>

<td align="left">AD11</td>

<td align="left">input </td>

<td align="left">3.3-V LVTTL</td>

</tr>

<tr>

<td align="left">RESET_n</td>

<td align="left">AD27</td>

<td align="left">input </td>

<td align="left">3.3-V LVTTL</td>

</tr>

</table>

<h2><a name="SW"></a></h2><table border="3">

<caption align="left">SW</caption>

<br />

<br />

<tr>

<th align="left" bgcolor="Khaki">Name</th>

<th align="left" bgcolor="Khaki">Location</th>

<th align="left" bgcolor="Khaki">Direction</th>

<th align="left" bgcolor="Khaki">Standard</th>

</tr>

<tr>

<td align="left">SW[0]</td>

<td align="left">W25</td>

<td align="left">input </td>

<td align="left">2.5 V</td>

</tr>

<tr>

<td align="left">SW[1]</td>

<td align="left">V25</td>

<td align="left">input </td>

<td align="left">2.5 V</td>

</tr>

<tr>

<td align="left">SW[2]</td>

<td align="left">AC28</td>

<td align="left">input </td>

<td align="left">2.5 V</td>

</tr>

<tr>

<td align="left">SW[3]</td>

<td align="left">AC29</td>

<td align="left">input </td>

<td align="left">2.5 V</td>

</tr>

</table>

<h2><a name="Si5338"></a></h2><table border="3">

<caption align="left">Si5338</caption>

<br />

<br />

<tr>

<th align="left" bgcolor="Khaki">Name</th>

<th align="left" bgcolor="Khaki">Location</th>

<th align="left" bgcolor="Khaki">Direction</th>

<th align="left" bgcolor="Khaki">Standard</th>

</tr>

<tr>

<td align="left">SI5338_SCL</td>

<td align="left">AE26</td>

<td align="left">output</td>

<td align="left">3.3-V LVTTL</td>

</tr>

<tr>

<td align="left">SI5338_SDA</td>

<td align="left">AJ29</td>

<td align="left">inout </td>

<td align="left">3.3-V LVTTL</td>

</tr>

</table>

<h2><a name="Temperature"></a></h2><table border="3">

<caption align="left">Temperature</caption>

<br />

<br />

<tr>

<th align="left" bgcolor="Khaki">Name</th>

<th align="left" bgcolor="Khaki">Location</th>

<th align="left" bgcolor="Khaki">Direction</th>

<th align="left" bgcolor="Khaki">Standard</th>

</tr>

<tr>

<td align="left">TEMP_CS_n</td>

<td align="left">AF8</td>

<td align="left">output</td>

<td align="left">3.3-V LVTTL</td>

</tr>

<tr>

<td align="left">TEMP_DIN</td>

<td align="left">AG7</td>

<td align="left">output</td>

<td align="left">3.3-V LVTTL</td>

</tr>

<tr>

<td align="left">TEMP_DOUT</td>

<td align="left">AG1</td>

<td align="left">input </td>

<td align="left">3.3-V LVTTL</td>

</tr>

<tr>

<td align="left">TEMP_SCLK</td>

<td align="left">AF9</td>

<td align="left">output</td>

<td align="left">3.3-V LVTTL</td>

</tr>

</table>

<h2><a name="VGA"></a></h2><table border="3">

<caption align="left">VGA</caption>

<br />

<br />

<tr>

<th align="left" bgcolor="Khaki">Name</th>

<th align="left" bgcolor="Khaki">Location</th>

<th align="left" bgcolor="Khaki">Direction</th>

<th align="left" bgcolor="Khaki">Standard</th>

</tr>

<tr>

<td align="left">VGA_HS</td>

<td align="left">AD12</td>

<td align="left">output</td>

<td align="left">3.3-V LVTTL</td>

</tr>

<tr>

<td align="left">VGA_VS</td>

<td align="left">AC12</td>

<td align="left">output</td>

<td align="left">3.3-V LVTTL</td>

</tr>

<tr>

<td align="left">VGA_SYNC_n</td>

<td align="left">AG2</td>

<td align="left">output</td>

<td align="left">3.3-V LVTTL</td>

</tr>

<tr>

<td align="left">VGA_CLK</td>

<td align="left">W20</td>

<td align="left">output</td>

<td align="left">3.3-V LVTTL</td>

</tr>

<tr>

<td align="left">VGA_BLANK_n</td>

<td align="left">AH3</td>

<td align="left">output</td>

<td align="left">3.3-V LVTTL</td>

</tr>

<tr>

<td align="left">VGA_R[0]</td>

<td align="left">AG5</td>

<td align="left">output</td>

<td align="left">3.3-V LVTTL</td>

</tr>

<tr>

<td align="left">VGA_R[1]</td>

<td align="left">AA12</td>

<td align="left">output</td>

<td align="left">3.3-V LVTTL</td>

</tr>

<tr>

<td align="left">VGA_R[2]</td>

<td align="left">AB12</td>

<td align="left">output</td>

<td align="left">3.3-V LVTTL</td>

</tr>

<tr>

<td align="left">VGA_R[3]</td>

<td align="left">AF6</td>

<td align="left">output</td>

<td align="left">3.3-V LVTTL</td>

</tr>

<tr>

<td align="left">VGA_R[4]</td>

<td align="left">AG6</td>

<td align="left">output</td>

<td align="left">3.3-V LVTTL</td>

</tr>

<tr>

<td align="left">VGA_R[5]</td>

<td align="left">AJ2</td>

<td align="left">output</td>

<td align="left">3.3-V LVTTL</td>

</tr>

<tr>

<td align="left">VGA_R[6]</td>

<td align="left">AH5</td>

<td align="left">output</td>

<td align="left">3.3-V LVTTL</td>

</tr>

<tr>

<td align="left">VGA_R[7]</td>

<td align="left">AJ1</td>

<td align="left">output</td>

<td align="left">3.3-V LVTTL</td>

</tr>

<tr>

<td align="left">VGA_G[0]</td>

<td align="left">Y21</td>

<td align="left">output</td>

<td align="left">3.3-V LVTTL</td>

</tr>

<tr>

<td align="left">VGA_G[1]</td>

<td align="left">AA25</td>

<td align="left">output</td>

<td align="left">3.3-V LVTTL</td>

</tr>

<tr>

<td align="left">VGA_G[2]</td>

<td align="left">AB26</td>

<td align="left">output</td>

<td align="left">3.3-V LVTTL</td>

</tr>

<tr>

<td align="left">VGA_G[3]</td>

<td align="left">AB22</td>

<td align="left">output</td>

<td align="left">3.3-V LVTTL</td>

</tr>

<tr>

<td align="left">VGA_G[4]</td>

<td align="left">AB23</td>

<td align="left">output</td>

<td align="left">3.3-V LVTTL</td>

</tr>

<tr>

<td align="left">VGA_G[5]</td>

<td align="left">AA24</td>

<td align="left">output</td>

<td align="left">3.3-V LVTTL</td>

</tr>

<tr>

<td align="left">VGA_G[6]</td>

<td align="left">AB25</td>

<td align="left">output</td>

<td align="left">3.3-V LVTTL</td>

</tr>

<tr>

<td align="left">VGA_G[7]</td>

<td align="left">AE27</td>

<td align="left">output</td>

<td align="left">3.3-V LVTTL</td>

</tr>

<tr>

<td align="left">VGA_B[0]</td>

<td align="left">AE28</td>

<td align="left">output</td>

<td align="left">3.3-V LVTTL</td>

</tr>

<tr>

<td align="left">VGA_B[1]</td>

<td align="left">Y23</td>

<td align="left">output</td>

<td align="left">3.3-V LVTTL</td>

</tr>

<tr>

<td align="left">VGA_B[2]</td>

<td align="left">Y24</td>

<td align="left">output</td>

<td align="left">3.3-V LVTTL</td>

</tr>

<tr>

<td align="left">VGA_B[3]</td>

<td align="left">AG28</td>

<td align="left">output</td>

<td align="left">3.3-V LVTTL</td>

</tr>

<tr>

<td align="left">VGA_B[4]</td>

<td align="left">AF28</td>

<td align="left">output</td>

<td align="left">3.3-V LVTTL</td>

</tr>

<tr>

<td align="left">VGA_B[5]</td>

<td align="left">V23</td>

<td align="left">output</td>

<td align="left">3.3-V LVTTL</td>

</tr>

<tr>

<td align="left">VGA_B[6]</td>

<td align="left">W24</td>

<td align="left">output</td>

<td align="left">3.3-V LVTTL</td>

</tr>

<tr>

<td align="left">VGA_B[7]</td>

<td align="left">AF29</td>

<td align="left">output</td>

<td align="left">3.3-V LVTTL</td>

</tr>

</table>

<h2><a name="Audio"></a></h2><table border="3">

<caption align="left">Audio</caption>

<br />

<br />

<tr>

<th align="left" bgcolor="Khaki">Name</th>

<th align="left" bgcolor="Khaki">Location</th>

<th align="left" bgcolor="Khaki">Direction</th>

<th align="left" bgcolor="Khaki">Standard</th>

</tr>

<tr>

<td align="left">AUD_ADCLRCK</td>

<td align="left">AG30</td>

<td align="left">inout </td>

<td align="left">3.3-V LVTTL</td>

</tr>

<tr>

<td align="left">AUD_ADCDAT</td>

<td align="left">AC27</td>

<td align="left">input </td>

<td align="left">3.3-V LVTTL</td>

</tr>

<tr>

<td align="left">AUD_DACLRCK</td>

<td align="left">AH4</td>

<td align="left">inout </td>

<td align="left">3.3-V LVTTL</td>

</tr>

<tr>

<td align="left">AUD_DACDAT</td>

<td align="left">AG3</td>

<td align="left">output</td>

<td align="left">3.3-V LVTTL</td>

</tr>

<tr>

<td align="left">AUD_XCK</td>

<td align="left">AC9</td>

<td align="left">output</td>

<td align="left">3.3-V LVTTL</td>

</tr>

<tr>

<td align="left">AUD_BCLK</td>

<td align="left">AE7</td>

<td align="left">inout </td>

<td align="left">3.3-V LVTTL</td>

</tr>

<tr>

<td align="left">AUD_MUTE</td>

<td align="left">AD26</td>

<td align="left">output</td>

<td align="left">3.3-V LVTTL</td>

</tr>

</table>

<h2><a name="I2C for Audio "></a></h2><table border="3">

<caption align="left">I2C for Audio </caption>

<br />

<br />

<tr>

<th align="left" bgcolor="Khaki">Name</th>

<th align="left" bgcolor="Khaki">Location</th>

<th align="left" bgcolor="Khaki">Direction</th>

<th align="left" bgcolor="Khaki">Standard</th>

</tr>

<tr>

<td align="left">AUD_I2C_SCLK</td>

<td align="left">AH30</td>

<td align="left">output</td>

<td align="left">3.3-V LVTTL</td>

</tr>

<tr>

<td align="left">AUD_I2C_SDAT</td>

<td align="left">AF30</td>

<td align="left">inout </td>

<td align="left">3.3-V LVTTL</td>

</tr>

</table>

<h2><a name="SDRAM"></a></h2><table border="3">

<caption align="left">SDRAM</caption>

<br />

<br />

<tr>

<th align="left" bgcolor="Khaki">Name</th>

<th align="left" bgcolor="Khaki">Location</th>

<th align="left" bgcolor="Khaki">Direction</th>