Revision 28
Added by markw over 11 years ago
| unmerged/zpu_firmware/mcc216/x | ||
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HelloTinyROM.elf: file format elf32-zpu
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Disassembly of section .fixed_vectors:
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00000000 <_start>:
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0: 0b nop
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1: 0b nop
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2: 0b nop
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3: 89 im 9
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4: ad im 45
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5: 04 poppc
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6: 0b nop
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7: 0b nop
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8: 0b nop
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9: 0b nop
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a: 0b nop
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b: 0b nop
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c: 0b nop
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d: 0b nop
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e: 0b nop
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f: 0b nop
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10: 0b nop
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11: 0b nop
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12: 0b nop
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13: 0b nop
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14: 0b nop
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15: 0b nop
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16: 0b nop
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17: 0b nop
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18: 0b nop
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19: 0b nop
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1a: 0b nop
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1b: 0b nop
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1c: 0b nop
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1d: 0b nop
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1e: 0b nop
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1f: 0b nop
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20: 0b nop
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21: 0b nop
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22: 0b nop
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23: 0b nop
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...
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00000040 <_loadh>:
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40: 71 loadsp 4
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41: fd im -3
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42: 06 and
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43: 08 load
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44: 72 loadsp 8
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45: 83 im 3
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46: 06 and
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47: 09 not
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48: 81 im 1
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49: 05 add
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4a: 82 im 2
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4b: 05 add
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4c: 83 im 3
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4d: 2b ashiftleft
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4e: 2a lshiftright
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4f: 83 im 3
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50: ff im -1
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51: ff im -1
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52: 06 and
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53: 52 storesp 8
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54: 04 poppc
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...
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00000060 <_storeh>:
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60: 71 loadsp 4
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61: fd im -3
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62: 06 and
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63: 08 load
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64: 83 im 3
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65: ff im -1
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66: ff im -1
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67: 73 loadsp 12
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68: 83 im 3
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69: 06 and
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6a: 09 not
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6b: 81 im 1
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6c: 05 add
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6d: 82 im 2
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6e: 05 add
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6f: 83 im 3
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70: 2b ashiftleft
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71: 2b ashiftleft
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72: 09 not
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73: 06 and
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74: 73 loadsp 12
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75: 83 im 3
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76: ff im -1
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77: ff im -1
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78: 0b nop
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79: 0b nop
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7a: 0b nop
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7b: 0b nop
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7c: 83 im 3
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7d: a7 im 39
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7e: 04 poppc
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...
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00000080 <_lessthan>:
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80: 72 loadsp 8
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81: 09 not
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82: 81 im 1
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83: 05 add
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84: 72 loadsp 8
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85: 05 add
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86: 73 loadsp 12
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87: 73 loadsp 12
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88: 09 not
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89: 06 and
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8a: 09 not
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8b: 06 and
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8c: 73 loadsp 12
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8d: 09 not
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8e: 73 loadsp 12
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8f: 06 and
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90: 07 or
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91: 0a flip
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92: 81 im 1
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93: 06 and
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94: 53 storesp 12
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95: 51 storesp 4
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96: 04 poppc
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...
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000000a0 <_lessthanorequal>:
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a0: 72 loadsp 8
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a1: 72 loadsp 8
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a2: 24 lessthan
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a3: 73 loadsp 12
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a4: 73 loadsp 12
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a5: 2e eq
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a6: 07 or
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a7: 53 storesp 12
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a8: 51 storesp 4
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a9: 04 poppc
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...
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000000c0 <_ulessthan>:
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c0: 71 loadsp 4
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c1: 73 loadsp 12
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c2: 71 loadsp 4
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c3: 09 not
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c4: 71 loadsp 4
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c5: 06 and
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c6: 81 im 1
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c7: 06 and
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c8: 30 neg
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c9: 72 loadsp 8
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ca: 0a flip
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cb: 10 addsp 0
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cc: 0a flip
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cd: 72 loadsp 8
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ce: 0a flip
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cf: 10 addsp 0
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d0: 0a flip
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d1: 31 sub
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d2: 05 add
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d3: 0a flip
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d4: 81 im 1
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d5: 06 and
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d6: 51 storesp 4
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d7: 51 storesp 4
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d8: 53 storesp 12
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d9: 51 storesp 4
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da: 04 poppc
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db: 00 breakpoint
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dc: 00 breakpoint
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dd: 00 breakpoint
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...
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000000e0 <_ulessthanorequal>:
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e0: 72 loadsp 8
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e1: 72 loadsp 8
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e2: 26 ulessthan
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e3: 73 loadsp 12
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e4: 73 loadsp 12
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e5: 2e eq
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e6: 07 or
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e7: 53 storesp 12
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e8: 51 storesp 4
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e9: 04 poppc
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...
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00000100 <_swap>:
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...
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00000120 <_slowmult>:
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120: 0b nop
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121: 0b nop
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122: 0b nop
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123: 88 im 8
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124: bc im 60
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125: 04 poppc
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...
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00000140 <_lshiftright>:
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140: 72 loadsp 8
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141: 0a flip
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142: 72 loadsp 8
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143: 2b ashiftleft
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144: 0a flip
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145: 53 storesp 12
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146: 51 storesp 4
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147: 04 poppc
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...
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00000160 <_ashiftleft>:
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160: 72 loadsp 8
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161: 72 loadsp 8
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162: 9f im 31
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163: 06 and
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164: 09 not
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165: 81 im 1
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166: 05 add
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167: 0b nop
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168: 0b nop
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169: 0b nop
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16a: 88 im 8
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16b: 9f im 31
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16c: 05 add
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16d: 04 poppc
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...
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00000180 <_ashiftright>:
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180: 72 loadsp 8
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181: 72 loadsp 8
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182: 2a lshiftright
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183: ff im -1
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184: 73 loadsp 12
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185: 9f im 31
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186: 06 and
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187: 2a lshiftright
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188: 09 not
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189: 74 loadsp 16
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18a: 09 not
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18b: 0a flip
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18c: 81 im 1
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18d: 06 and
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18e: ff im -1
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18f: 05 add
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190: 06 and
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191: 07 or
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192: 53 storesp 12
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193: 51 storesp 4
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194: 04 poppc
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...
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000001a0 <_call>:
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1a0: 71 loadsp 4
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1a1: 71 loadsp 4
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1a2: 53 storesp 12
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1a3: 51 storesp 4
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1a4: 02 pushsp
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1a5: 0d popsp
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1a6: 04 poppc
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000001a7 <_storehtail>:
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1a7: 06 and
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1a8: 73 loadsp 12
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1a9: 83 im 3
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1aa: 06 and
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1ab: 09 not
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1ac: 81 im 1
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1ad: 05 add
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1ae: 82 im 2
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1af: 05 add
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1b0: 83 im 3
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1b1: 2b ashiftleft
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1b2: 0b nop
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1b3: 2b ashiftleft
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1b4: 07 or
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1b5: 72 loadsp 8
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1b6: fc im -4
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1b7: 06 and
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1b8: 0c store
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1b9: 51 storesp 4
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1ba: 51 storesp 4
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1bb: 04 poppc
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1bc: 00 breakpoint
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1bd: 00 breakpoint
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...
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000001c0 <_eq>:
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1c0: 72 loadsp 8
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1c1: 09 not
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1c2: 81 im 1
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1c3: 05 add
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1c4: 72 loadsp 8
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1c5: 05 add
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1c6: 09 not
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1c7: 70 loadsp 0
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1c8: 81 im 1
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1c9: 05 add
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1ca: 09 not
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1cb: 06 and
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1cc: 0a flip
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1cd: 81 im 1
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1ce: 06 and
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1cf: 53 storesp 12
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1d0: 51 storesp 4
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1d1: 04 poppc
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...
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000001e0 <_neq>:
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1e0: 72 loadsp 8
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1e1: 09 not
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1e2: 81 im 1
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1e3: 05 add
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1e4: 72 loadsp 8
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1e5: 05 add
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1e6: 09 not
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1e7: 70 loadsp 0
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1e8: 81 im 1
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1e9: 05 add
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1ea: 09 not
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1eb: 06 and
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1ec: 0a flip
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1ed: 09 not
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1ee: 81 im 1
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1ef: 06 and
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1f0: 53 storesp 12
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1f1: 51 storesp 4
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1f2: 04 poppc
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...
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00000200 <_neg>:
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200: 71 loadsp 4
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201: 09 not
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202: 81 im 1
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203: 05 add
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204: 52 storesp 8
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205: 04 poppc
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...
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00000220 <_sub>:
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220: 72 loadsp 8
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221: 72 loadsp 8
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222: 09 not
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223: 81 im 1
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224: 05 add
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225: 05 add
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226: 53 storesp 12
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227: 51 storesp 4
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228: 04 poppc
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...
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00000240 <_xor>:
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240: 72 loadsp 8
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241: 09 not
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242: 72 loadsp 8
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243: 06 and
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244: 73 loadsp 12
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245: 73 loadsp 12
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246: 09 not
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247: 06 and
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248: 07 or
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249: 53 storesp 12
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24a: 51 storesp 4
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24b: 04 poppc
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...
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00000260 <_loadb>:
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260: 71 loadsp 4
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261: fc im -4
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262: 06 and
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263: 08 load
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264: 72 loadsp 8
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265: 83 im 3
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266: 06 and
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267: 09 not
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268: 81 im 1
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269: 05 add
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26a: 83 im 3
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26b: 05 add
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26c: 10 addsp 0
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26d: 10 addsp 0
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26e: 10 addsp 0
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26f: 2a lshiftright
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270: 81 im 1
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271: ff im -1
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272: 06 and
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273: 52 storesp 8
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274: 04 poppc
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...
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00000280 <_storeb>:
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280: 71 loadsp 4
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281: fc im -4
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282: 06 and
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283: 08 load
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284: 0b nop
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285: 0b nop
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286: 80 im 0
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287: f4 im -12
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288: a4 im 36
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289: 73 loadsp 12
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||
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28a: 83 im 3
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28b: 06 and
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28c: 10 addsp 0
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28d: 10 addsp 0
|
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28e: 05 add
|
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28f: 08 load
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||
|
290: 06 and
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||
|
291: 0b nop
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||
|
292: 0b nop
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||
|
293: 0b nop
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||
|
294: 88 im 8
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||
|
295: a2 im 34
|
||
|
296: 04 poppc
|
||
|
...
|
||
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||
|
000002a0 <_div>:
|
||
|
2a0: 0b nop
|
||
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2a1: 0b nop
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||
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2a2: 0b nop
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||
|
2a3: 88 im 8
|
||
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2a4: ff im -1
|
||
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2a5: 04 poppc
|
||
|
...
|
||
|
|
||
|
000002c0 <_mod>:
|
||
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2c0: 0b nop
|
||
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2c1: 0b nop
|
||
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2c2: 0b nop
|
||
|
2c3: 88 im 8
|
||
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2c4: d8 im -40
|
||
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2c5: 04 poppc
|
||
|
...
|
||
|
|
||
|
000002e0 <_eqbranch>:
|
||
|
2e0: 72 loadsp 8
|
||
|
2e1: 09 not
|
||
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2e2: 70 loadsp 0
|
||
|
2e3: 81 im 1
|
||
|
2e4: 05 add
|
||
|
2e5: 09 not
|
||
|
2e6: 06 and
|
||
|
2e7: 0a flip
|
||
|
2e8: 81 im 1
|
||
|
2e9: 06 and
|
||
|
2ea: ff im -1
|
||
|
2eb: 05 add
|
||
|
2ec: 70 loadsp 0
|
||
|
2ed: 54 storesp 16
|
||
|
2ee: 71 loadsp 4
|
||
|
2ef: 06 and
|
||
|
2f0: 73 loadsp 12
|
||
|
2f1: 09 not
|
||
|
2f2: 72 loadsp 8
|
||
|
2f3: 74 loadsp 16
|
||
|
2f4: 05 add
|
||
|
2f5: ff im -1
|
||
|
2f6: 05 add
|
||
|
2f7: 06 and
|
||
|
2f8: 07 or
|
||
|
2f9: 51 storesp 4
|
||
|
2fa: 51 storesp 4
|
||
|
2fb: 51 storesp 4
|
||
|
2fc: 04 poppc
|
||
|
2fd: 00 breakpoint
|
||
|
...
|
||
|
|
||
|
00000300 <_neqbranch>:
|
||
|
300: 72 loadsp 8
|
||
|
301: 09 not
|
||
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302: 70 loadsp 0
|
||
|
303: 81 im 1
|
||
|
304: 05 add
|
||
|
305: 09 not
|
||
|
306: 06 and
|
||
|
307: 0a flip
|
||
|
308: 09 not
|
||
|
309: 81 im 1
|
||
|
30a: 06 and
|
||
|
30b: ff im -1
|
||
|
30c: 05 add
|
||
|
30d: 70 loadsp 0
|
||
|
30e: 54 storesp 16
|
||
|
30f: 71 loadsp 4
|
||
|
310: 06 and
|
||
|
311: 73 loadsp 12
|
||
|
312: 09 not
|
||
|
313: 72 loadsp 8
|
||
|
314: 74 loadsp 16
|
||
|
315: 05 add
|
||
|
316: ff im -1
|
||
|
317: 05 add
|
||
|
318: 06 and
|
||
|
319: 07 or
|
||
|
31a: 51 storesp 4
|
||
|
31b: 51 storesp 4
|
||
|
31c: 51 storesp 4
|
||
|
31d: 04 poppc
|
||
|
...
|
||
|
|
||
|
00000320 <_poppcrel>:
|
||
|
320: 05 add
|
||
|
321: ff im -1
|
||
|
322: 05 add
|
||
|
323: 04 poppc
|
||
|
...
|
||
|
|
||
|
00000340 <_config>:
|
||
|
340: 81 im 1
|
||
|
341: 0b nop
|
||
|
342: 80 im 0
|
||
|
343: f9 im -7
|
||
|
344: f0 im -16
|
||
|
345: 0c store
|
||
|
346: 51 storesp 4
|
||
|
347: 04 poppc
|
||
|
...
|
||
|
|
||
|
0000035e <_pushpc>:
|
||
|
35e: 71 loadsp 4
|
||
|
35f: 81 im 1
|
||
|
360: 05 add
|
||
|
361: 52 storesp 8
|
||
|
362: 04 poppc
|
||
|
...
|
||
|
|
||
|
0000037e <_syscall_emulate>:
|
||
|
...
|
||
|
|
||
|
0000039e <_pushspadd>:
|
||
|
39e: 02 pushsp
|
||
|
39f: 84 im 4
|
||
|
3a0: 05 add
|
||
|
3a1: 72 loadsp 8
|
||
|
3a2: 10 addsp 0
|
||
|
3a3: 10 addsp 0
|
||
|
3a4: 05 add
|
||
|
3a5: 52 storesp 8
|
||
|
3a6: 04 poppc
|
||
|
...
|
||
|
|
||
|
000003be <_halfmult>:
|
||
|
...
|
||
|
|
||
|
000003de <_callpcrel>:
|
||
|
3de: 71 loadsp 4
|
||
|
3df: 71 loadsp 4
|
||
|
3e0: 05 add
|
||
|
3e1: ff im -1
|
||
|
3e2: 05 add
|
||
|
3e3: 71 loadsp 4
|
||
|
3e4: 53 storesp 12
|
||
|
3e5: 51 storesp 4
|
||
|
3e6: 02 pushsp
|
||
|
3e7: 0d popsp
|
||
|
3e8: 04 poppc
|
||
|
...
|
||
|
Disassembly of section .text:
|
||
|
|
||
|
00000400 <_ashiftleftBegin>:
|
||
|
400: 10 addsp 0
|
||
|
401: 10 addsp 0
|
||
|
402: 10 addsp 0
|
||
|
403: 10 addsp 0
|
||
|
404: 10 addsp 0
|
||
|
405: 10 addsp 0
|
||
|
406: 10 addsp 0
|
||
|
407: 10 addsp 0
|
||
|
408: 10 addsp 0
|
||
|
409: 10 addsp 0
|
||
|
40a: 10 addsp 0
|
||
|
40b: 10 addsp 0
|
||
|
40c: 10 addsp 0
|
||
|
40d: 10 addsp 0
|
||
|
40e: 10 addsp 0
|
||
|
40f: 10 addsp 0
|
||
|
410: 10 addsp 0
|
||
|
411: 10 addsp 0
|
||
|
412: 10 addsp 0
|
||
|
413: 10 addsp 0
|
||
|
414: 10 addsp 0
|
||
|
415: 10 addsp 0
|
||
|
416: 10 addsp 0
|
||
|
417: 10 addsp 0
|
||
|
418: 10 addsp 0
|
||
|
419: 10 addsp 0
|
||
|
41a: 10 addsp 0
|
||
|
41b: 10 addsp 0
|
||
|
41c: 10 addsp 0
|
||
|
41d: 10 addsp 0
|
||
|
41e: 10 addsp 0
|
||
|
|
||
|
0000041f <_ashiftleftEnd>:
|
||
|
41f: 53 storesp 12
|
||
|
420: 51 storesp 4
|
||
|
421: 04 poppc
|
||
|
|
||
|
00000422 <_storebtail>:
|
||
|
422: 73 loadsp 12
|
||
|
423: 81 im 1
|
||
|
424: ff im -1
|
||
|
425: 06 and
|
||
|
426: 73 loadsp 12
|
||
|
427: 83 im 3
|
||
|
428: 06 and
|
||
|
429: 09 not
|
||
|
42a: 81 im 1
|
||
|
42b: 05 add
|
||
|
42c: 83 im 3
|
||
|
42d: 05 add
|
||
|
42e: 10 addsp 0
|
||
|
42f: 10 addsp 0
|
||
|
430: 10 addsp 0
|
||
|
431: 2b ashiftleft
|
||
|
432: 07 or
|
||
|
433: 72 loadsp 8
|
||
|
434: fc im -4
|
||
|
435: 06 and
|
||
|
436: 0c store
|
||
|
437: 51 storesp 4
|
||
|
438: 51 storesp 4
|
||
|
439: 04 poppc
|
||
|
|
||
|
0000043a <_syscall>:
|
||
|
43a: 3c syscall
|
||
|
43b: 04 poppc
|
||
|
|
||
|
0000043c <_slowmultImpl>:
|
||
|
43c: 72 loadsp 8
|
||
|
43d: 72 loadsp 8
|
||
|
43e: 80 im 0
|
||
|
43f: 72 loadsp 8
|
||
|
440: 81 im 1
|
||
|
441: 06 and
|
||
|
442: ff im -1
|
||
|
443: 05 add
|
||
|
444: 09 not
|
||
|
445: 72 loadsp 8
|
||
|
446: 06 and
|
||
|
447: 05 add
|
||
|
448: 71 loadsp 4
|
||
|
449: 10 addsp 0
|
||
|
44a: 52 storesp 8
|
||
|
44b: 72 loadsp 8
|
||
|
44c: 0a flip
|
||
|
44d: 10 addsp 0
|
||
|
44e: 0a flip
|
||
|
44f: 53 storesp 12
|
||
|
450: 72 loadsp 8
|
||
|
451: ed im -19
|
||
|
452: 38 neqbranch
|
||
|
453: 51 storesp 4
|
||
|
454: 51 storesp 4
|
||
|
455: 53 storesp 12
|
||
|
456: 51 storesp 4
|
||
|
457: 04 poppc
|
||
|
|
||
|
00000458 <___mod>:
|
||
|
458: 83 im 3
|
||
|
459: e0 im -32
|
||
|
45a: 80 im 0
|
||
|
45b: 08 load
|
||
|
45c: 83 im 3
|
||
|
45d: e0 im -32
|
||
|
45e: 84 im 4
|
||
|
45f: 08 load
|
||
|
460: 83 im 3
|
||
|
461: e0 im -32
|
||
|
462: 88 im 8
|
||
|
463: 08 load
|
||
|
464: 75 loadsp 20
|
||
|
465: 75 loadsp 20
|
||
|
466: 80 im 0
|
||
|
467: ee im -18
|
||
|
468: d4 im -44
|
||
|
469: 2d call
|
||
|
46a: 50 storesp 0
|
||
|
46b: 50 storesp 0
|
||
|
46c: 83 im 3
|
||
|
46d: e0 im -32
|
||
|
46e: 80 im 0
|
||
|
46f: 08 load
|
||
|
470: 56 storesp 24
|
||
|
471: 83 im 3
|
||
|
472: e0 im -32
|
||
|
473: 88 im 8
|
||
|
474: 0c store
|
||
|
475: 83 im 3
|
||
|
476: e0 im -32
|
||
|
477: 84 im 4
|
||
|
478: 0c store
|
||
|
479: 83 im 3
|
||
|
47a: e0 im -32
|
||
|
47b: 80 im 0
|
||
|
47c: 0c store
|
||
|
47d: 51 storesp 4
|
||
|
47e: 04 poppc
|
||
|
|
||
|
0000047f <___div>:
|
||
|
47f: 83 im 3
|
||
|
480: e0 im -32
|
||
|
481: 80 im 0
|
||
|
482: 08 load
|
||
|
483: 83 im 3
|
||
|
484: e0 im -32
|
||
|
485: 84 im 4
|
||
|
486: 08 load
|
||
|
487: 83 im 3
|
||
|
488: e0 im -32
|
||
|
489: 88 im 8
|
||
|
48a: 08 load
|
||
|
48b: 75 loadsp 20
|
||
|
48c: 75 loadsp 20
|
||
|
48d: 80 im 0
|
||
|
48e: ec im -20
|
||
|
48f: e8 im -24
|
||
|
490: 2d call
|
||
|
491: 50 storesp 0
|
||
|
492: 50 storesp 0
|
||
|
493: 83 im 3
|
||
|
494: e0 im -32
|
||
|
495: 80 im 0
|
||
|
496: 08 load
|
||
|
497: 56 storesp 24
|
||
|
498: 83 im 3
|
||
|
499: e0 im -32
|
||
|
49a: 88 im 8
|
||
|
49b: 0c store
|
||
|
49c: 83 im 3
|
||
|
49d: e0 im -32
|
||
|
49e: 84 im 4
|
||
|
49f: 0c store
|
||
|
4a0: 83 im 3
|
||
|
4a1: e0 im -32
|
||
|
4a2: 80 im 0
|
||
|
4a3: 0c store
|
||
|
4a4: 51 storesp 4
|
||
|
4a5: 04 poppc
|
||
|
...
|
||
|
|
||
|
000004a8 <_boot>:
|
||
|
4a8: 80 im 0
|
||
|
4a9: 04 poppc
|
||
|
|
||
|
000004aa <_break>:
|
||
|
4aa: 89 im 9
|
||
|
4ab: aa im 42
|
||
|
4ac: 04 poppc
|
||
|
|
||
|
000004ad <_premain>:
|
||
|
4ad: 89 im 9
|
||
|
4ae: aa im 42
|
||
|
4af: 0b nop
|
||
|
4b0: bf im 63
|
||
|
4b1: fb im -5
|
||
|
4b2: 04 poppc
|
||
|
|
||
|
000004b3 <wait_us>:
|
||
|
#define XEX_SECTOR_SIZE 128
|
||
|
|
||
|
void
|
||
|
wait_us(int unsigned num)
|
||
|
{
|
||
|
4b3: fd im -3
|
||
|
4b4: 3d pushspadd
|
||
|
4b5: 0d popsp
|
||
|
|
||
|
000004b6 <.LM2>:
|
||
|
// 57.5MHz
|
||
|
int unsigned cycles = num*57 + num/2;
|
||
|
4b6: 75 loadsp 20
|
||
|
4b7: b9 im 57
|
||
|
4b8: 29 mult
|
||
|
4b9: 76 loadsp 24
|
||
|
4ba: 81 im 1
|
||
|
4bb: 2a lshiftright
|
||
|
4bc: 05 add
|
||
|
|
||
|
000004bd <.LM3>:
|
||
|
*zpu_pause = cycles;
|
||
|
4bd: 80 im 0
|
||
|
4be: fc im -4
|
||
|
4bf: c0 im -64
|
||
|
4c0: 08 load
|
||
|
4c1: 54 storesp 16
|
||
|
4c2: 73 loadsp 12
|
||
|
4c3: 0c store
|
||
|
4c4: 85 im 5
|
||
|
4c5: 3d pushspadd
|
||
|
4c6: 0d popsp
|
||
|
4c7: 04 poppc
|
||
|
|
||
|
000004c8 <clearAtariSectorBuffer>:
|
||
|
}
|
||
|
|
||
|
void openfile(const char * filename);
|
||
|
void sdcard();
|
||
|
void mmcReadCached(u32 sector);
|
||
|
u32 n_actual_mmc_sector;
|
||
|
extern unsigned char mmc_sector_buffer[512];
|
||
|
unsigned char atari_sector_buffer[256];
|
||
|
unsigned char get_checksum(unsigned char* buffer, u16 len);
|
||
|
|
||
|
#define TWOBYTESTOWORD(ptr,val) (*((u08*)(ptr)) = val&0xff);(*(1+(u08*)(ptr)) = (val>>8)&0xff);
|
||
|
|
||
|
void USART_Send_cmpl_and_atari_sector_buffer_and_check_sum(unsigned short len);
|
||
|
void clearAtariSectorBuffer()
|
||
|
{
|
||
|
4c8: 80 im 0
|
||
|
4c9: 3d pushspadd
|
||
|
4ca: 0d popsp
|
||
|
|
||
|
000004cb <.LM5>:
|
||
|
int i=256;
|
||
|
while (--i)
|
||
|
atari_sector_buffer[i] = 0;
|
||
|
4cb: 81 im 1
|
||
|
4cc: ff im -1
|
||
|
4cd: 51 storesp 4
|
||
|
|
||
|
000004ce <.L5>:
|
||
|
4ce: 80 im 0
|
||
|
4cf: 0b nop
|
||
|
4d0: 83 im 3
|
||
|
4d1: e0 im -32
|
||
|
4d2: c8 im -56
|
||
|
4d3: 12 addsp 8
|
||
|
4d4: 34 storeb
|
||
|
4d5: ff im -1
|
||
|
4d6: 11 addsp 4
|
||
|
4d7: 51 storesp 4
|
||
|
4d8: 70 loadsp 0
|
||
|
4d9: f4 im -12
|
||
|
4da: 38 neqbranch
|
||
|
4db: 82 im 2
|
||
|
4dc: 3d pushspadd
|
||
|
4dd: 0d popsp
|
||
|
4de: 04 poppc
|
||
|
|
||
|
000004df <filesize>:
|
||
|
}
|
||
|
|
||
|
int
|
||
|
filesize(char const * filename)
|
||
|
{
|
||
|
4df: fa im -6
|
||
|
4e0: 3d pushspadd
|
||
|
4e1: 0d popsp
|
||
|
4e2: 78 loadsp 32
|
||
|
|
||
|
000004e3 <.LM7>:
|
||
|
char const * tmp;
|
||
|
char const * tmp2;
|
||
|
if (FR_OK != pf_opendir(&dir,"/"))
|
||
|
4e3: 0b nop
|
||
|
4e4: 0b nop
|
||
|
4e5: 80 im 0
|
||
|
4e6: f4 im -12
|
||
|
4e7: fc im -4
|
||
|
4e8: 53 storesp 12
|
||
|
4e9: 83 im 3
|
||
|
4ea: e2 im -30
|
||
|
4eb: f4 im -12
|
||
|
4ec: 52 storesp 8
|
||
|
4ed: 56 storesp 24
|
||
|
4ee: 80 im 0
|
||
|
4ef: cc im -52
|
||
|
4f0: a8 im 40
|
||
|
4f1: 3f callpcrel
|
||
|
|
||
|
000004f2 <.LM8>:
|
||
|
{
|
||
|
return 0;
|
||
|
4f2: 80 im 0
|
||
|
4f3: 53 storesp 12
|
||
|
|
||
|
000004f4 <.LM9>:
|
||
|
4f4: 83 im 3
|
||
|
4f5: e0 im -32
|
||
|
4f6: 80 im 0
|
||
|
4f7: 08 load
|
||
|
4f8: 73 loadsp 12
|
||
|
4f9: 2e eq
|
||
|
4fa: 8a im 10
|
||
|
4fb: 38 neqbranch
|
||
|
|
||
|
000004fc <.LM10>:
|
||
|
}
|
||
|
|
||
|
while (FR_OK == pf_readdir(&dir,&filinfo) && filinfo.fname[0]!='\0')
|
||
|
{
|
||
|
if (filinfo.fattrib & AM_SYS)
|
||
|
{
|
||
|
continue;
|
||
|
}
|
||
|
if (filinfo.fattrib & AM_HID)
|
||
|
{
|
||
|
continue;
|
||
|
}
|
||
|
if (filinfo.fattrib & AM_DIR)
|
||
|
{
|
||
|
continue;
|
||
|
}
|
||
|
|
||
|
tmp = filename;
|
||
|
tmp2 = filinfo.fname;
|
||
|
while (1)
|
||
|
{
|
||
|
if (*tmp == *tmp2)
|
||
|
{
|
||
|
if (*tmp == '\0')
|
||
|
{
|
||
|
return filinfo.fsize;
|
||
|
}
|
||
|
++tmp;
|
||
|
++tmp2;
|
||
|
}
|
||
|
else
|
||
|
break;
|
||
|
}
|
||
|
}
|
||
|
return 0;
|
||
|
}
|
||
|
4fc: 72 loadsp 8
|
||
|
4fd: 83 im 3
|
||
|
4fe: e0 im -32
|
||
|
4ff: 80 im 0
|
||
|
500: 0c store
|
||
|
501: 88 im 8
|
||
|
502: 3d pushspadd
|
||
|
503: 0d popsp
|
||
|
504: 04 poppc
|
||
|
|
||
|
00000505 <.L26>:
|
||
|
505: 83 im 3
|
||
|
506: e0 im -32
|
||
|
507: 94 im 20
|
||
|
508: 52 storesp 8
|
||
|
509: 83 im 3
|
||
|
50a: e2 im -30
|
||
|
50b: f4 im -12
|
||
|
50c: 51 storesp 4
|
||
|
50d: 80 im 0
|
||
|
50e: cd im -51
|
||
|
50f: 9c im 28
|
||
|
510: 3f callpcrel
|
||
|
511: 83 im 3
|
||
|
512: e0 im -32
|
||
|
513: 80 im 0
|
||
|
514: 08 load
|
||
|
515: 80 im 0
|
||
|
516: d5 im -43
|
||
|
517: 38 neqbranch
|
||
|
518: 83 im 3
|
||
|
519: e0 im -32
|
||
|
51a: 9d im 29
|
||
|
51b: 33 loadb
|
||
|
51c: 53 storesp 12
|
||
|
51d: 72 loadsp 8
|
||
|
51e: 80 im 0
|
||
|
51f: 2e eq
|
||
|
520: 80 im 0
|
||
|
521: ca im -54
|
||
|
522: 38 neqbranch
|
||
|
|
||
|
00000523 <.LM12>:
|
||
|
523: 83 im 3
|
||
|
524: e0 im -32
|
||
|
525: 9c im 28
|
||
|
526: 33 loadb
|
||
|
527: 70 loadsp 0
|
||
|
528: 82 im 2
|
||
|
529: 2a lshiftright
|
||
|
52a: 70 loadsp 0
|
||
|
52b: 81 im 1
|
||
|
52c: 06 and
|
||
|
52d: 51 storesp 4
|
||
|
52e: 54 storesp 16
|
||
|
52f: 54 storesp 16
|
||
|
530: 72 loadsp 8
|
||
|
531: d3 im -45
|
||
|
532: 38 neqbranch
|
||
|
|
||
|
00000533 <.LM13>:
|
||
|
533: 73 loadsp 12
|
||
|
534: 81 im 1
|
||
|
535: 2a lshiftright
|
||
|
536: 70 loadsp 0
|
||
|
537: 81 im 1
|
||
|
538: 06 and
|
||
|
539: 51 storesp 4
|
||
|
53a: 53 storesp 12
|
||
|
53b: 72 loadsp 8
|
||
|
53c: c8 im -56
|
||
|
53d: 38 neqbranch
|
||
|
|
||
|
0000053e <.LM14>:
|
||
|
53e: 73 loadsp 12
|
||
|
53f: 84 im 4
|
||
|
540: 2a lshiftright
|
||
|
541: 70 loadsp 0
|
||
|
542: 81 im 1
|
||
|
543: 06 and
|
||
|
544: 51 storesp 4
|
||
|
545: 53 storesp 12
|
||
|
546: 72 loadsp 8
|
||
|
547: ff im -1
|
||
|
548: bc im 60
|
||
|
549: 38 neqbranch
|
||
|
|
||
|
0000054a <.LM15>:
|
||
|
54a: 75 loadsp 20
|
||
|
|
||
|
0000054b <.LM16>:
|
||
|
54b: 83 im 3
|
||
|
54c: e0 im -32
|
||
|
54d: 9d im 29
|
||
|
54e: 56 storesp 24
|
||
|
54f: 54 storesp 16
|
||
|
|
||
|
00000550 <.L16>:
|
||
|
550: 73 loadsp 12
|
||
|
551: 33 loadb
|
||
|
552: 75 loadsp 20
|
||
|
553: 33 loadb
|
||
|
554: 58 storesp 32
|
||
|
555: 53 storesp 12
|
||
|
556: 72 loadsp 8
|
||
|
557: 77 loadsp 28
|
||
|
558: 2e eq
|
||
|
559: 09 not
|
||
|
55a: 81 im 1
|
||
|
55b: 06 and
|
||
|
55c: ff im -1
|
||
|
55d: a7 im 39
|
||
|
55e: 38 neqbranch
|
||
|
|
||
|
0000055f <.LM18>:
|
||
|
55f: 72 loadsp 8
|
||
|
560: 80 im 0
|
||
|
561: 2e eq
|
||
|
562: 93 im 19
|
||
|
563: 38 neqbranch
|
||
|
|
||
|
00000564 <.LM19>:
|
||
|
564: 81 im 1
|
||
|
565: 14 addsp 16
|
||
|
|
||
|
00000566 <.LM20>:
|
||
|
566: 81 im 1
|
||
|
567: 16 addsp 24
|
||
|
568: 56 storesp 24
|
||
|
569: 54 storesp 16
|
||
|
56a: e5 im -27
|
||
|
56b: 39 poppcrel
|
||
|
|
||
|
0000056c <.L12>:
|
||
|
56c: 80 im 0
|
||
|
|
||
|
0000056d <.LM22>:
|
||
|
56d: 0b nop
|
||
|
56e: 83 im 3
|
||
|
56f: e0 im -32
|
||
|
570: 80 im 0
|
||
|
571: 0c store
|
||
|
572: 88 im 8
|
||
|
573: 3d pushspadd
|
||
|
574: 0d popsp
|
||
|
575: 04 poppc
|
||
|
|
||
|
00000576 <.L22>:
|
||
|
576: 83 im 3
|
||
|
577: e0 im -32
|
||
|
578: 94 im 20
|
||
|
579: 08 load
|
||
|
|
||
|
0000057a <.LM24>:
|
||
|
57a: 83 im 3
|
||
|
57b: e0 im -32
|
||
|
57c: 80 im 0
|
||
|
57d: 0c store
|
||
|
57e: 88 im 8
|
||
|
57f: 3d pushspadd
|
||
|
580: 0d popsp
|
||
|
581: 04 poppc
|
||
|
|
||
|
00000582 <clear_ram>:
|
||
|
|
||
|
int
|
||
|
selectfile(char * filename)
|
||
|
{
|
||
|
int fileno;
|
||
|
int skip;
|
||
|
int plotted = 0;
|
||
|
wait_us(200000);
|
||
|
for(;;)
|
||
|
{
|
||
|
int i = 0;
|
||
|
int go = 0;
|
||
|
fileno = 0;
|
||
|
topofscreen();
|
||
|
for (i=0; i!=(24*40); ++i)
|
||
|
{
|
||
|
*(unsigned char volatile *)(i+0x10000+40000) = 0x00;
|
||
|
}
|
||
|
if (FR_OK != pf_opendir(&dir,"/"))
|
||
|
{
|
||
|
debug("opendir failed\n");
|
||
|
while(1);
|
||
|
}
|
||
|
|
||
|
plotted = 0;
|
||
|
skip = 0;
|
||
|
if (selfileno>20)
|
||
|
{
|
||
|
skip = selfileno-20;
|
||
|
skip&=0xfffffffe;
|
||
|
}
|
||
|
if (selfileno<0)
|
||
|
{
|
||
|
selfileno = 0;
|
||
|
}
|
||
|
while (FR_OK == pf_readdir(&dir,&filinfo) && filinfo.fname[0]!='\0')
|
||
|
{
|
||
|
if (filinfo.fattrib & AM_SYS)
|
||
|
{
|
||
|
continue;
|
||
|
}
|
||
|
if (filinfo.fattrib & AM_HID)
|
||
|
{
|
||
|
continue;
|
||
|
}
|
||
|
if (filinfo.fattrib & AM_DIR)
|
||
|
{
|
||
|
debug("DIR ");
|
||
|
}
|
||
|
if (selfileno == fileno)
|
||
|
{
|
||
|
for (i=0;i!=15;++i)
|
||
|
{
|
||
|
filename[i] = filinfo.fname[i];
|
||
|
if (0==filinfo.fname[i]) break;
|
||
|
filinfo.fname[i]+=128;
|
||
|
}
|
||
|
}
|
||
|
if (--skip<0)
|
||
|
{
|
||
|
debug(filinfo.fname);
|
||
|
++plotted;
|
||
|
if (plotted&1)
|
||
|
{
|
||
|
setxpos(20);
|
||
|
}
|
||
|
else
|
||
|
{
|
||
|
debug("\n");
|
||
|
}
|
||
|
if (plotted==40)
|
||
|
{
|
||
|
break;
|
||
|
}
|
||
|
}
|
||
|
fileno++;
|
||
|
}
|
||
|
debug("\n");
|
||
|
setypos(21);
|
||
|
opendrive = 0;
|
||
|
openfile(filename);
|
||
|
for (;;)
|
||
|
{
|
||
|
unsigned char porta = *atari_porta;
|
||
|
if (0==(porta&0x2)) // down
|
||
|
{
|
||
|
selfileno+=2;
|
||
|
break;
|
||
|
}
|
||
|
else if (0==(porta&0x1)) // up
|
||
|
{
|
||
|
selfileno-=2;
|
||
|
break;
|
||
|
}
|
||
|
else if (0==(porta&0x8)) // right
|
||
|
{
|
||
|
selfileno|=1;
|
||
|
break;
|
||
|
}
|
||
|
else if (0==(porta&0x4)) // left
|
||
|
{
|
||
|
selfileno&=0xfffffffe;
|
||
|
break;
|
||
|
}
|
||
|
else if (0==(*atari_trig0)) // fire
|
||
|
{
|
||
|
go = 1;
|
||
|
while(0==(*atari_trig0));
|
||
|
break;
|
||
|
}
|
||
|
topofscreen();
|
||
|
//plotnextnumber(porta);
|
||
|
*atari_colbk = *atari_random;
|
||
|
//wait_us(200);
|
||
|
}
|
||
|
if (go == 1)
|
||
|
{
|
||
|
wait_us(200000);
|
||
|
return validfile; // TODO, another way to quit without selecting...
|
||
|
}
|
||
|
wait_us(80000);
|
||
|
}
|
||
|
return 0;
|
||
|
}
|
||
|
|
||
|
void clear_ram()
|
||
|
{
|
||
|
582: fd im -3
|
||
|
583: 3d pushspadd
|
||
|
584: 0d popsp
|
||
|
|
||
|
00000585 <.LM26>:
|
||
|
int i=0;
|
||
|
585: 80 im 0
|
||
|
|
||
|
00000586 <.LM27>:
|
||
|
// sdram from 8MB to 16MB
|
||
|
// sram from 0x200000
|
||
|
*zpu_ledr = 0xffffffff;
|
||
|
586: 0b nop
|
||
|
587: 80 im 0
|
||
|
588: fc im -4
|
||
|
589: b0 im 48
|
||
|
58a: 08 load
|
||
|
58b: 53 storesp 12
|
||
|
58c: 53 storesp 12
|
||
|
58d: ff im -1
|
||
|
58e: 72 loadsp 8
|
||
|
58f: 0c store
|
||
|
|
||
|
00000590 <.LM28>:
|
||
|
*zpu_ledg = 0x0;
|
||
|
590: 80 im 0
|
||
|
591: fc im -4
|
||
|
592: b4 im 52
|
||
|
593: 08 load
|
||
|
594: 73 loadsp 12
|
||
|
595: 71 loadsp 4
|
||
|
596: 0c store
|
||
|
597: 52 storesp 8
|
||
|
|
||
|
00000598 <.LM29>:
|
||
|
wait_us(600);
|
||
|
598: 84 im 4
|
||
|
599: d8 im -40
|
||
|
59a: 51 storesp 4
|
||
|
59b: fe im -2
|
||
|
59c: 96 im 22
|
||
|
59d: 3f callpcrel
|
||
|
|
||
|
0000059e <.LM30>:
|
||
|
|
||
|
for (i=0x200000; i!=0x280000; i+=1)
|
||
|
59e: 88 im 8
|
||
|
59f: 80 im 0
|
||
|
5a0: 0a flip
|
||
|
5a1: 53 storesp 12
|
||
|
|
||
|
000005a2 <.L32>:
|
||
|
{
|
||
|
// TODO - use short!
|
||
|
*(unsigned char volatile *)(i) = 0x0000;
|
||
|
5a2: 80 im 0
|
||
|
5a3: 73 loadsp 12
|
||
|
5a4: 70 loadsp 0
|
||
|
5a5: 81 im 1
|
||
|
5a6: 05 add
|
||
|
5a7: 55 storesp 20
|
||
|
5a8: 34 storeb
|
||
|
|
||
|
000005a9 <.LM32>:
|
||
|
5a9: 72 loadsp 8
|
||
|
5aa: a8 im 40
|
||
|
5ab: 80 im 0
|
||
|
5ac: 0a flip
|
||
|
5ad: 2e eq
|
||
|
5ae: 09 not
|
||
|
5af: 81 im 1
|
||
|
5b0: 06 and
|
||
|
5b1: f0 im -16
|
||
|
5b2: 38 neqbranch
|
||
|
|
||
|
000005b3 <.LM33>:
|
||
|
}
|
||
|
|
||
|
*zpu_ledr = 0x55555555;
|
||
|
5b3: 80 im 0
|
||
|
5b4: fc im -4
|
||
|
5b5: b0 im 48
|
||
|
5b6: 08 load
|
||
|
5b7: 54 storesp 16
|
||
|
5b8: 85 im 5
|
||
|
5b9: aa im 42
|
||
|
5ba: d5 im -43
|
||
|
5bb: aa im 42
|
||
|
5bc: d5 im -43
|
||
|
5bd: 74 loadsp 16
|
||
|
5be: 0c store
|
||
|
|
||
|
000005bf <.LM34>:
|
||
|
*zpu_ledg = 0x55555555;
|
||
|
5bf: 80 im 0
|
||
|
5c0: fc im -4
|
||
|
5c1: b4 im 52
|
||
|
5c2: 08 load
|
||
|
5c3: 52 storesp 8
|
||
|
5c4: 85 im 5
|
||
|
5c5: aa im 42
|
||
|
5c6: d5 im -43
|
||
|
5c7: aa im 42
|
||
|
5c8: d5 im -43
|
||
|
5c9: 72 loadsp 8
|
||
|
5ca: 0c store
|
||
|
|
||
|
000005cb <.LM35>:
|
||
|
|
||
|
for (i=0x800000; i!=0x1000000; i+=4)
|
||
|
5cb: 82 im 2
|
||
|
5cc: 80 im 0
|
||
|
5cd: 0a flip
|
||
|
5ce: 53 storesp 12
|
||
|
|
||
|
000005cf <.L36>:
|
||
|
{
|
||
|
*(unsigned int volatile *)(i) = 0x00000000;
|
||
|
5cf: 80 im 0
|
||
|
5d0: 73 loadsp 12
|
||
|
5d1: 70 loadsp 0
|
||
|
5d2: 84 im 4
|
||
|
5d3: 05 add
|
||
|
5d4: 55 storesp 20
|
||
|
5d5: 0c store
|
||
|
|
||
|
000005d6 <.LM37>:
|
||
|
5d6: 72 loadsp 8
|
||
|
5d7: 81 im 1
|
||
|
5d8: 80 im 0
|
||
|
5d9: 0a flip
|
||
|
5da: 2e eq
|
||
|
5db: 09 not
|
||
|
5dc: 81 im 1
|
||
|
5dd: 06 and
|
||
|
5de: f0 im -16
|
||
|
5df: 38 neqbranch
|
||
|
|
||
|
000005e0 <.LM38>:
|
||
|
}
|
||
|
|
||
|
*zpu_ledr = 0;
|
||
|
5e0: 80 im 0
|
||
|
5e1: 74 loadsp 16
|
||
|
5e2: 0c store
|
||
|
|
||
|
000005e3 <.LM39>:
|
||
|
*zpu_ledg = 0xffffffff;
|
||
|
5e3: ff im -1
|
||
|
5e4: 72 loadsp 8
|
||
|
5e5: 0c store
|
||
|
|
||
|
000005e6 <.LM40>:
|
||
|
wait_us(600);
|
||
|
5e6: 84 im 4
|
||
|
5e7: d8 im -40
|
||
|
5e8: 51 storesp 4
|
||
|
5e9: fd im -3
|
||
|
5ea: c8 im -56
|
||
|
5eb: 3f callpcrel
|
||
|
|
||
|
000005ec <.LM41>:
|
||
|
return;
|
||
|
5ec: 85 im 5
|
||
|
5ed: 3d pushspadd
|
||
|
5ee: 0d popsp
|
||
|
5ef: 04 poppc
|
||
|
|
||
|
000005f0 <clear_64k_ram>:
|
||
|
}
|
||
|
|
||
|
void clear_64k_ram()
|
||
|
{
|
||
|
5f0: fd im -3
|
||
|
5f1: 3d pushspadd
|
||
|
5f2: 0d popsp
|
||
|
|
||
|
000005f3 <.LM43>:
|
||
|
int i=0;
|
||
|
5f3: 80 im 0
|
||
|
|
||
|
000005f4 <.LM44>:
|
||
|
// sdram from 8MB to 16MB
|
||
|
// sram from 0x200000
|
||
|
|
||
|
*zpu_ledr = 0xf0f0f0f0;
|
||
|
5f4: 0b nop
|
||
|
5f5: 80 im 0
|
||
|
5f6: fc im -4
|
||
|
5f7: b0 im 48
|
||
|
5f8: 08 load
|
||
|
5f9: 53 storesp 12
|
||
|
5fa: 53 storesp 12
|
||
|
5fb: ff im -1
|
||
|
5fc: 87 im 7
|
||
|
5fd: c3 im -61
|
||
|
5fe: e1 im -31
|
||
|
5ff: f0 im -16
|
||
|
600: 72 loadsp 8
|
||
|
601: 0c store
|
||
|
|
||
|
00000602 <.LM45>:
|
||
|
*zpu_ledg = 0x0;
|
||
|
602: 80 im 0
|
||
|
603: fc im -4
|
||
|
604: b4 im 52
|
||
|
605: 08 load
|
||
|
606: 73 loadsp 12
|
||
|
607: 71 loadsp 4
|
||
|
608: 0c store
|
||
|
609: 52 storesp 8
|
||
|
|
||
|
0000060a <.LM46>:
|
||
|
wait_us(200000);
|
||
|
60a: 8c im 12
|
||
|
60b: 9a im 26
|
||
|
60c: c0 im -64
|
||
|
60d: 51 storesp 4
|
||
|
60e: fd im -3
|
||
|
60f: a3 im 35
|
||
|
610: 3f callpcrel
|
||
|
|
||
|
00000611 <.LM47>:
|
||
|
|
||
|
for (i=0x200000; i!=0x210000; i+=1)
|
||
|
611: 88 im 8
|
||
|
612: 80 im 0
|
||
|
613: 0a flip
|
||
|
614: 53 storesp 12
|
||
|
|
||
|
00000615 <.L46>:
|
||
|
{
|
||
|
// TODO - use short!
|
||
|
*(unsigned char volatile *)(i) = 0x0000;
|
||
|
615: 80 im 0
|
||
|
616: 73 loadsp 12
|
||
|
617: 70 loadsp 0
|
||
|
618: 81 im 1
|
||
|
619: 05 add
|
||
|
61a: 55 storesp 20
|
||
|
61b: 34 storeb
|
||
|
|
||
|
0000061c <.LM49>:
|
||
|
61c: 72 loadsp 8
|
||
|
61d: 81 im 1
|
||
|
61e: 84 im 4
|
||
|
61f: 80 im 0
|
||
|
620: 80 im 0
|
||
|
621: 2e eq
|
||
|
622: 09 not
|
||
|
623: 81 im 1
|
||
|
624: 06 and
|
||
|
625: ef im -17
|
||
|
626: 38 neqbranch
|
||
|
|
||
|
00000627 <.LM50>:
|
||
|
}
|
||
|
|
||
|
*zpu_ledr = 0x55555555;
|
||
|
627: 80 im 0
|
||
|
628: fc im -4
|
||
|
629: b0 im 48
|
||
|
62a: 08 load
|
||
|
62b: 54 storesp 16
|
||
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62c: 85 im 5
|
||
|
62d: aa im 42
|
||
|
62e: d5 im -43
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||
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62f: aa im 42
|
||
|
630: d5 im -43
|
||
|
631: 74 loadsp 16
|
||
|
632: 0c store
|
||
|
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|
00000633 <.LM51>:
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*zpu_ledg = 0x55555555;
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633: 80 im 0
|
||
|
634: fc im -4
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||
|
635: b4 im 52
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636: 08 load
|
||
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637: 52 storesp 8
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||
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638: 85 im 5
|
||
|
639: aa im 42
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||
|
63a: d5 im -43
|
||
|
63b: aa im 42
|
||
Also available in: Unified diff
Should never have been committed...