Project

General

Profile

« Previous | Next » 

Revision 278

Added by markw over 10 years ago

start of USB support - ram timing issue fixed

View differences:

mcc216/atari800core.qsf
set_global_assignment -name TOP_LEVEL_ENTITY atari800core_mcc
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "12.1 SP1"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "13:58:39 APRIL 11, 2013"
set_global_assignment -name LAST_QUARTUS_VERSION "12.1 SP1.33"
set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
......
set_global_assignment -name VHDL_FILE zpu_rom.vhdl
set_global_assignment -name VHDL_FILE atari800core_mcc.vhd
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
mcc216/atari800core_mcc.vhd
ARCHITECTURE vhdl OF atari800core_mcc IS
component usbHostCyc2Wrap_usb1t11
port (
clk_i :in std_logic;
rst_i :in std_logic;
address_i : in std_logic_vector(7 downto 0);
data_i : in std_logic_vector(7 downto 0);
data_o : out std_logic_vector(7 downto 0);
we_i :in std_logic;
strobe_i :in std_logic;
ack_o :out std_logic;
irq :out std_logic;
usbClk :in std_logic;
USBWireVPin :in std_logic;
USBWireVMin :in std_logic;
USBWireVPout :out std_logic;
USBWireVMout :out std_logic;
USBWireOE_n :out std_logic;
USBFullSpeed :out std_logic
);
end component;
component hq_dac
port (
reset :in std_logic;
......
signal CLK_SDRAM : std_logic;
-- SDRAM
signal PREREG_SDRAM_REQUEST : std_logic;
signal PREREG_SDRAM_READ_ENABLE : STD_LOGIC;
signal PREREG_SDRAM_WRITE_ENABLE : std_logic;
signal PREREG_SDRAM_ADDR : STD_LOGIC_VECTOR(22 DOWNTO 0);
SIGNAL PREREG_SDRAM_DI : std_logic_vector(31 downto 0);
SIGNAL PREREG_SDRAM_WIDTH_32BIT_ACCESS : std_logic;
SIGNAL PREREG_SDRAM_WIDTH_16BIT_ACCESS : std_logic;
SIGNAL PREREG_SDRAM_WIDTH_8BIT_ACCESS : std_logic;
signal SDRAM_REQUEST : std_logic;
signal SDRAM_REQUEST_COMPLETE : std_logic;
signal SDRAM_READ_ENABLE : STD_LOGIC;
signal SDRAM_WRITE_ENABLE : std_logic;
signal SDRAM_ADDR : STD_LOGIC_VECTOR(22 DOWNTO 0);
......
SIGNAL SDRAM_WIDTH_32BIT_ACCESS : std_logic;
SIGNAL SDRAM_WIDTH_16BIT_ACCESS : std_logic;
SIGNAL SDRAM_WIDTH_8BIT_ACCESS : std_logic;
signal SDRAM_REQUEST_COMPLETE : std_logic;
signal SDRAM_REFRESH : std_logic;
......
BEGIN
usbcon : usbHostCyc2Wrap_usb1t11
port map
(
clk_i => clk,
rst_i => not(reset_n),
address_i => (others=>'0'),
data_i => (others=>'0'),
data_o =>open,
we_i => '0',
strobe_i => '0',
ack_o => open,
irq => open,
usbClk => CLK_USB,
USB2_N <= USBWireVPout when USBWireOE_n='0' else 'Z';
USB2_P <= USBWireVMout when USBWireOE_n='0' else 'Z';
USBWireVPin <= USB2_N;
USBWireVMin <= USB2_P;
USBWireVPin => USBWireVPin,
USBWireVMin => USBWireVMin,
USBWireVPout => USBWireVPout,
USBWireVMout => USBWireVMout,
USBWireOE_n => USBWireOE_n,
USBFullSpeed => open
);
USB2_P <= USBWireVPout when USBWireOE_n='0' else 'Z';
USB2_N <= USBWireVMout when USBWireOE_n='0' else 'Z';
USBWireVPin <= USB2_P;
USBWireVMin <= USB2_N;
dac_left : hq_dac
port map
(
......
CONSOL_SELECT => CONSOL_SELECT,
CONSOL_START => CONSOL_START,
SDRAM_REQUEST => SDRAM_REQUEST,
SDRAM_REQUEST => PREREG_SDRAM_REQUEST,
SDRAM_REQUEST_COMPLETE => SDRAM_REQUEST_COMPLETE,
SDRAM_READ_ENABLE => SDRAM_READ_ENABLE,
SDRAM_WRITE_ENABLE => SDRAM_WRITE_ENABLE,
SDRAM_ADDR => SDRAM_ADDR,
SDRAM_READ_ENABLE => PREREG_SDRAM_READ_ENABLE,
SDRAM_WRITE_ENABLE => PREREG_SDRAM_WRITE_ENABLE,
SDRAM_ADDR => PREREG_SDRAM_ADDR,
SDRAM_DO => ram_do_reg,
SDRAM_DI => SDRAM_DI,
SDRAM_32BIT_WRITE_ENABLE => SDRAM_WIDTH_32bit_ACCESS,
SDRAM_16BIT_WRITE_ENABLE => SDRAM_WIDTH_16bit_ACCESS,
SDRAM_8BIT_WRITE_ENABLE => SDRAM_WIDTH_8bit_ACCESS,
SDRAM_DI => PREREG_SDRAM_DI,
SDRAM_32BIT_WRITE_ENABLE => PREREG_SDRAM_WIDTH_32bit_ACCESS,
SDRAM_16BIT_WRITE_ENABLE => PREREG_SDRAM_WIDTH_16bit_ACCESS,
SDRAM_8BIT_WRITE_ENABLE => PREREG_SDRAM_WIDTH_8bit_ACCESS,
SDRAM_REFRESH => SDRAM_REFRESH,
DMA_FETCH => dma_fetch,
......
process(clk_sdram,sdram_reset_ctrl_n_reg)
begin
if (sdram_reset_ctrl_n_reg='0') then
seq_reg <= "100000000000";
seq_reg <= "010000000000";
seq_ph_reg <= '1';
ref_reg <= '0';
......
process(seq_reg, seq_next, sdram_rdy, sdram_reset_n_reg, reset_atari)
begin
sdram_reset_n_next <= sdram_reset_n_reg;
if (sdram_rdy = '1' and seq_next(8)='1' and seq_reg(8)='0') then
if (sdram_rdy = '1' and seq_next(7)='1' and seq_reg(7)='0') then
sdram_reset_n_next <= '1';
end if;
if (reset_atari = '1') then
......
end if;
end process;
-- register sdram request on the falling edge, 1/3 timing not enough, but 1/2 timing should be... This pushes back request 1 clock cycle. Result can also be clocking on the falling edge!
process(clk,reset_n)
begin
if (reset_n='0') then
SDRAM_REQUEST <= '0';
SDRAM_READ_ENABLE <= '0';
SDRAM_WRITE_ENABLE <= '0';
SDRAM_ADDR <= (others=>'0');
SDRAM_DI <= (others=>'0');
SDRAM_WIDTH_32BIT_ACCESS <= '0';
SDRAM_WIDTH_16BIT_ACCESS <= '0';
SDRAM_WIDTH_8BIT_ACCESS <= '0';
elsif(clk'event and clk='0') then -- FALLING EDGE
SDRAM_REQUEST <= PREREG_SDRAM_REQUEST;
SDRAM_READ_ENABLE <= PREREG_SDRAM_READ_ENABLE;
SDRAM_WRITE_ENABLE <= PREREG_SDRAM_WRITE_ENABLE;
SDRAM_ADDR <= PREREG_SDRAM_ADDR;
SDRAM_DI <= PREREG_SDRAM_DI;
SDRAM_WIDTH_32BIT_ACCESS <= PREREG_SDRAM_WIDTH_32BIT_ACCESS;
SDRAM_WIDTH_16BIT_ACCESS <= PREREG_SDRAM_WIDTH_16BIT_ACCESS;
SDRAM_WIDTH_8BIT_ACCESS <= PREREG_SDRAM_WIDTH_8BIT_ACCESS;
end if;
end process;
-- Adapt SDRAM
process(sdram_request_reg, sdram_request, sdram_request_complete_reg, ram_do_reg, seq_reg, ram_do, ram_rd_active, ram_wr_active, SDRAM_WIDTH_8BIT_ACCESS, SDRAM_WRITE_ENABLE, SDRAM_READ_ENABLE, SDRAM_DI, SDRAM_ADDR)
begin
sdram_request_next <= sdram_request_reg or sdram_request;
sdram_request_next <= (sdram_request_reg or sdram_request) and not(sdram_request_complete_reg);
sdram_request_complete_next <= sdram_request_complete_reg;
ram_bena_next <= "00";
ram_di_next <= (others=>'0');
......
when "000000001000" =>
-- nop
when "000000010000" =>
sdram_request_complete_next <= '0';
-- nop
when "000000100000" =>
sdram_request_complete_next <= '0';
-- nop
when "000001000000" =>
if (SDRAM_READ_ENABLE = '1') then
......
when "001000000000" =>
-- nop
when "010000000000" =>
sdram_request_complete_next <= '0';
-- nop
when "100000000000" =>
sdram_request_complete_next <= '0';
-- nop
when others =>
-- never
......
GENERIC MAP
(
platform => 1,
spi_clock_div => 1 -- 28MHz/2. Max for SD cards is 25MHz...
spi_clock_div => 1, -- 28MHz/2. Max for SD cards is 25MHz...
memory => 8192,
usb => 1
)
PORT MAP
(
......
ZPU_OUT1 => zpu_out1,
ZPU_OUT2 => zpu_out2,
ZPU_OUT3 => zpu_out3,
ZPU_OUT4 => zpu_out4
ZPU_OUT4 => zpu_out4,
-- USB host
CLK_USB => CLK_USB,
USBWireVPin(0) => USBWireVPin,
USBWireVMin(0) => USBWireVMin,
USBWireVPout(0) => USBWireVPout,
USBWireVMout(0) => USBWireVMout,
USBWireOE_n(0) => USBWireOE_n
);
pause_atari <= zpu_out1(0);
......
zpu_rom1: entity work.zpu_rom
port map(
clock => clk,
address => zpu_addr_rom(13 downto 2),
address => zpu_addr_rom(14 downto 2),
q => zpu_rom_data
);
mcc216/atari800core_mcc.wcfg
</top_modules>
</db_ref>
</db_ref_list>
<WVObjectSize size="50" />
<WVObjectSize size="54" />
<wvobject fp_name="/atari800core_mcc_tb/reset_n" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">reset_n</obj_property>
<obj_property name="ObjectShortName">reset_n</obj_property>
......
<obj_property name="ElementShortName">sdram_clk</obj_property>
<obj_property name="ObjectShortName">sdram_clk</obj_property>
</wvobject>
<wvobject fp_name="/atari800core_mcc_tb/atari/atarixl_simple_sdram1/clk" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">clk</obj_property>
<obj_property name="ObjectShortName">clk</obj_property>
</wvobject>
<wvobject fp_name="/atari800core_mcc_tb/sdram_a" type="array" db_ref_id="1">
<obj_property name="ElementShortName">sdram_a[12:0]</obj_property>
<obj_property name="ObjectShortName">sdram_a[12:0]</obj_property>
......
<obj_property name="ObjectShortName">a[15:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/atari800core_mcc_tb/atari/pause_atari" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">pause_atari</obj_property>
<obj_property name="ObjectShortName">pause_atari</obj_property>
</wvobject>
<wvobject fp_name="/atari800core_mcc_tb/atari/atarixl_simple_sdram1/atari800xl/cpu6502/throttle" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">throttle</obj_property>
<obj_property name="ObjectShortName">throttle</obj_property>
......
<obj_property name="ElementShortName">sdram_request_complete</obj_property>
<obj_property name="ObjectShortName">sdram_request_complete</obj_property>
</wvobject>
<wvobject fp_name="/atari800core_mcc_tb/atari/sdram_reset_n_next" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">sdram_reset_n_next</obj_property>
<obj_property name="ObjectShortName">sdram_reset_n_next</obj_property>
</wvobject>
<wvobject fp_name="/atari800core_mcc_tb/atari/reset_atari" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">reset_atari</obj_property>
<obj_property name="ObjectShortName">reset_atari</obj_property>
</wvobject>
<wvobject fp_name="/atari800core_mcc_tb/atari/sdram_rdy" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">sdram_rdy</obj_property>
<obj_property name="ObjectShortName">sdram_rdy</obj_property>
......
<wvobject fp_name="/atari800core_mcc_tb/atari/seq_reg" type="array" db_ref_id="1">
<obj_property name="ElementShortName">seq_reg[11:0]</obj_property>
<obj_property name="ObjectShortName">seq_reg[11:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/atari800core_mcc_tb/atari/sd_dat0" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">sd_dat0</obj_property>
mcc216/usbpll.cmp
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
component usbpll
PORT
(
areset : IN STD_LOGIC := '0';
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC
);
end component;
mcc216/usbpll.ppf
<?xml version="1.0" encoding="UTF-8" ?>
<!DOCTYPE pinplan>
<pinplan intended_family="Cyclone III" variation_name="usbpll" megafunction_name="ALTPLL" specifies="all_ports">
<global>
<pin name="areset" direction="input" scope="external" />
<pin name="inclk0" direction="input" scope="external" source="clock" />
<pin name="c0" direction="output" scope="external" source="clock" />
<pin name="locked" direction="output" scope="external" />
</global>
</pinplan>
mcc216/usbpll.qip
set_global_assignment -name IP_TOOL_NAME "ALTPLL"
set_global_assignment -name IP_TOOL_VERSION "13.0"
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "usbpll.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "usbpll.cmp"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "usbpll.ppf"]
mcc216/usbpll.vhd
-- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: usbpll.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY usbpll IS
PORT
(
areset : IN STD_LOGIC := '0';
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC
);
END usbpll;
ARCHITECTURE SYN OF usbpll IS
SIGNAL sub_wire0 : STD_LOGIC ;
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC ;
SIGNAL sub_wire4 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire5_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire5 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT altpll
GENERIC (
bandwidth_type : STRING;
clk0_divide_by : NATURAL;
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
compensate_clock : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
operation_mode : STRING;
pll_type : STRING;
port_activeclock : STRING;
port_areset : STRING;
port_clkbad0 : STRING;
port_clkbad1 : STRING;
port_clkloss : STRING;
port_clkswitch : STRING;
port_configupdate : STRING;
port_fbin : STRING;
port_inclk0 : STRING;
port_inclk1 : STRING;
port_locked : STRING;
port_pfdena : STRING;
port_phasecounterselect : STRING;
port_phasedone : STRING;
port_phasestep : STRING;
port_phaseupdown : STRING;
port_pllena : STRING;
port_scanaclr : STRING;
port_scanclk : STRING;
port_scanclkena : STRING;
port_scandata : STRING;
port_scandataout : STRING;
port_scandone : STRING;
port_scanread : STRING;
port_scanwrite : STRING;
port_clk0 : STRING;
port_clk1 : STRING;
port_clk2 : STRING;
port_clk3 : STRING;
port_clk4 : STRING;
port_clk5 : STRING;
port_clkena0 : STRING;
port_clkena1 : STRING;
port_clkena2 : STRING;
port_clkena3 : STRING;
port_clkena4 : STRING;
port_clkena5 : STRING;
port_extclk0 : STRING;
port_extclk1 : STRING;
port_extclk2 : STRING;
port_extclk3 : STRING;
self_reset_on_loss_lock : STRING;
width_clock : NATURAL
);
PORT (
areset : IN STD_LOGIC ;
clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
locked : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
sub_wire5_bv(0 DOWNTO 0) <= "0";
sub_wire5 <= To_stdlogicvector(sub_wire5_bv);
locked <= sub_wire0;
sub_wire2 <= sub_wire1(0);
c0 <= sub_wire2;
sub_wire3 <= inclk0;
sub_wire4 <= sub_wire5(0 DOWNTO 0) & sub_wire3;
altpll_component : altpll
GENERIC MAP (
bandwidth_type => "AUTO",
clk0_divide_by => 5,
clk0_duty_cycle => 50,
clk0_multiply_by => 48,
clk0_phase_shift => "0",
compensate_clock => "CLK0",
inclk0_input_frequency => 200000,
intended_device_family => "Cyclone III",
lpm_hint => "CBX_MODULE_PREFIX=usbpll",
lpm_type => "altpll",
operation_mode => "NORMAL",
pll_type => "AUTO",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_USED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_UNUSED",
port_configupdate => "PORT_UNUSED",
port_fbin => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_USED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_UNUSED",
port_phasedone => "PORT_UNUSED",
port_phasestep => "PORT_UNUSED",
port_phaseupdown => "PORT_UNUSED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_UNUSED",
port_scanclkena => "PORT_UNUSED",
port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_UNUSED",
port_clk2 => "PORT_UNUSED",
port_clk3 => "PORT_UNUSED",
port_clk4 => "PORT_UNUSED",
port_clk5 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
port_extclk0 => "PORT_UNUSED",
port_extclk1 => "PORT_UNUSED",
port_extclk2 => "PORT_UNUSED",
port_extclk3 => "PORT_UNUSED",
self_reset_on_loss_lock => "OFF",
width_clock => 5
)
PORT MAP (
areset => areset,
inclk => sub_wire4,
locked => sub_wire0,
clk => sub_wire1
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "48.000000"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "5.000"
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "48.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "usbpll.mif"
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "5"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "48"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "200000"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
-- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
-- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL usbpll.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL usbpll.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL usbpll.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL usbpll.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL usbpll.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL usbpll_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
-- Retrieval info: CBX_MODULE_PREFIX: ON
mcc216/zpu_rom.vhdl
entity zpu_rom is
port(
clock:in std_logic;
address:in std_logic_vector(11 downto 0);
address:in std_logic_vector(12 downto 0);
q:out std_logic_vector(31 downto 0)
);
end zpu_rom;
architecture syn of zpu_rom is
type rom_type is array(0 to 4095) of std_logic_vector(31 downto 0);
type rom_type is array(0 to 8191) of std_logic_vector(31 downto 0);
signal ROM:rom_type:=
(
X"0b0b0b89",
......
X"00000000",
X"00000000",
X"71fc0608",
X"0b0b80f3",
X"e0738306",
X"0b0b81ce",
X"88738306",
X"10100508",
X"060b0b0b",
X"88a20400",
......
X"00000000",
X"00000000",
X"00000000",
X"810b80f7",
X"a40c5104",
X"810b81d4",
X"ec0c5104",
X"00000000",
X"00000000",
X"00000000",
......
X"0a100a53",
X"72ed3851",
X"51535104",
X"83e08008",
X"83e08408",
X"83e08808",
X"83c08008",
X"83c08408",
X"83c08808",
X"757580f3",
X"a32d5050",
X"83e08008",
X"5683e088",
X"0c83e084",
X"0c83e080",
X"c12d5050",
X"83c08008",
X"5683c088",
X"0c83c084",
X"0c83c080",
X"0c510483",
X"e0800883",
X"e0840883",
X"e0880875",
X"7580f2e2",
X"c0800883",
X"c0840883",
X"c0880875",
X"7580f380",
X"2d505083",
X"e0800856",
X"83e0880c",
X"83e0840c",
X"83e0800c",
X"c0800856",
X"83c0880c",
X"83c0840c",
X"83c0800c",
X"51040000",
X"800489aa",
X"0489aa0b",
X"80dbdb04",
X"80dbf104",
X"f43d0d7e",
X"8f3dec11",
X"56565890",
X"53f01552",
X"775193c4",
X"3f83e080",
X"3f83c080",
X"0880d638",
X"78902e09",
X"810680cd",
X"3802ab05",
X"3380f7ac",
X"0b80f7ac",
X"3381d4f4",
X"0b81d4f4",
X"33575856",
X"8c397476",
X"2e8a3884",
......
X"56705556",
X"5696800a",
X"52775192",
X"f33f83e0",
X"f33f83c0",
X"80088638",
X"78752e85",
X"38805685",
X"39811733",
X"567583e0",
X"567583c0",
X"800c8e3d",
X"0d04fc3d",
X"0d767052",
X"55b3a83f",
X"83e08008",
X"83c08008",
X"15ff0554",
X"73752e8e",
X"38733353",
......
X"38ff1454",
X"ef397752",
X"811451b2",
X"c03f83e0",
X"c03f83c0",
X"80083070",
X"83e08008",
X"83c08008",
X"07802583",
X"e0800c53",
X"c0800c53",
X"863d0d04",
X"fc3d0d76",
X"70525599",
X"e03f83e0",
X"e03f83c0",
X"80085481",
X"5383e080",
X"5383c080",
X"0880c738",
X"745199a3",
X"3f83e080",
X"080b0b80",
X"f5a05383",
X"e0800852",
X"3f83c080",
X"080b0b81",
X"d2e85383",
X"c0800852",
X"53ff8f3f",
X"83e08008",
X"83c08008",
X"a5380b0b",
X"80f5a452",
X"81d2ec52",
X"7251fefe",
X"3f83e080",
X"3f83c080",
X"0894380b",
X"0b80f5a8",
X"0b81d2f0",
X"527251fe",
X"ed3f83e0",
X"ed3f83c0",
X"8008802e",
X"83388154",
X"73537283",
X"e0800c86",
X"c0800c86",
X"3d0d04fd",
X"3d0d7570",
X"525498f9",
X"3f815383",
X"e0800898",
X"c0800898",
X"38735198",
X"c23f83e0",
X"a0085283",
X"e0800851",
X"c23f83c0",
X"b0085283",
X"c0800851",
X"feb43f83",
X"e0800853",
X"7283e080",
X"c0800853",
X"7283c080",
X"0c853d0d",
X"04df3d0d",
X"a43d0870",
X"525e8ee7",
X"3f83e080",
X"3f83c080",
X"0833953d",
X"56547396",
X"3880fab0",
X"3881d884",
X"527451b1",
X"9a3f9a39",
X"7d527851",
X"91e83f84",
X"e3397d51",
X"8ecd3f83",
X"e0800852",
X"c0800852",
X"74518dfd",
X"3f804380",
X"42804180",
X"4083e0a8",
X"4083c0b8",
X"0852943d",
X"70525d94",
X"d03f83e0",
X"d03f83c0",
X"80085980",
X"0b83e080",
X"0b83c080",
X"08555b83",
X"e080087b",
X"c080087b",
X"2e943881",
X"1b74525b",
X"97d23f83",
X"e0800854",
X"83e08008",
X"c0800854",
X"83c08008",
X"ee38805a",
X"ff5f7909",
X"709f2c7b",
......
X"5a525555",
X"80752595",
X"38765197",
X"973f83e0",
X"973f83c0",
X"800876ff",
X"18585557",
X"738024ed",
......
X"585d5880",
X"7a259538",
X"775196ec",
X"3f83e080",
X"3f83c080",
X"0876ff18",
X"58555873",
X"8024ed38",
X"800b83e7",
X"c00c800b",
X"83e7e40c",
X"0b0b80f5",
X"ac518bbe",
X"800b83c7",
X"d00c800b",
X"83c8840c",
X"0b0b81d2",
X"f4518bbe",
X"3f81800b",
X"83e7e40c",
X"0b0b80f5",
X"b4518bae",
X"83c8840c",
X"0b0b81d2",
X"fc518bae",
X"3fa80b83",
X"e7c00c76",
X"c7d00c76",
X"802e80e8",
X"3883e7c0",
X"3883c7d0",
X"08777932",
X"70307072",
X"07802570",
X"872b83e7",
X"e40c5156",
X"872b83c8",
X"840c5156",
X"78535656",
X"969f3f83",
X"e0800880",
X"c0800880",
X"2e8a380b",
X"0b80f5bc",
X"0b81d384",
X"518af33f",
X"765195df",
X"3f83e080",
X"3f83c080",
X"08520b0b",
X"80f6c851",
X"81d49051",
X"8ae03f76",
X"5195e53f",
X"83e08008",
X"83e7c008",
X"83c08008",
X"83c7d008",
X"55577574",
X"258638a8",
X"1656f739",
X"7583e7c0",
X"7583c7d0",
X"0c86f076",
X"24ff9438",
X"87980b83",
X"e7c00c77",
X"c7d00c77",
X"802eb738",
X"7751959b",
X"3f83e080",
X"3f83c080",
X"08785255",
X"95bb3f0b",
X"0b80f5c4",
X"5483e080",
X"0b81d38c",
X"5483c080",
X"088f3887",
X"39807634",
X"81d8390b",
X"0b80f5c0",
X"0b81d388",
X"54745373",
X"520b0b80",
X"f5945189",
X"520b0b81",
X"d2dc5189",
X"f93f8054",
X"0b0b80f7",
X"a05189ee",
X"0b0b81d4",
X"e85189ee",
X"3f811454",
X"73a82e09",
X"8106ed38",
......
X"beef3f80",
X"52903d70",
X"525780e1",
X"a13f8352",
X"bf3f8352",
X"765180e1",
X"993f6281",
X"b73f6281",
X"91386180",
X"2e80fd38",
X"7b5473ff",
X"2e963878",
X"802e818c",
X"38785194",
X"b73f83e0",
X"b73f83c0",
X"8008ff15",
X"5559e739",
X"78802e80",
X"f7387851",
X"94b33f83",
X"e0800880",
X"c0800880",
X"2efbfd38",
X"785193fb",
X"3f83e080",
X"3f83c080",
X"08520b0b",
X"80f59c51",
X"81d2e451",
X"abda3f83",
X"e08008a3",
X"c08008a3",
X"387c51ad",
X"923f83e0",
X"923f83c0",
X"80085574",
X"ff165654",
X"807425ae",
......
X"af2efec5",
X"38e93978",
X"5193ba3f",
X"83e08008",
X"83c08008",
X"527c51ac",
X"ca3f8f39",
X"7f882960",
......
X"fd396280",
X"2efbbe38",
X"80527651",
X"80dff73f",
X"80e0953f",
X"a33d0d04",
X"803d0d90",
X"80f83370",
X"88b83370",
X"81ff0670",
X"842a8132",
X"70810651",
X"51515170",
X"802e8d38",
X"a80b9080",
X"f834b80b",
X"9080f834",
X"7083e080",
X"a80b9088",
X"b834b80b",
X"9088b834",
X"7083c080",
X"0c823d0d",
X"04803d0d",
X"9080f833",
X"9088b833",
X"7081ff06",
X"70852a81",
X"32708106",
X"51515151",
X"70802e8d",
X"38980b90",
X"80f834b8",
X"0b9080f8",
X"347083e0",
X"88b834b8",
X"0b9088b8",
X"347083c0",
X"800c823d",
X"0d04930b",
X"9080fc34",
X"ff0b9080",
X"e83404ff",
X"9088bc34",
X"ff0b9088",
X"a83404ff",
X"3d0d028f",
X"05335280",
X"0b9080fc",
X"0b9088bc",
X"348a51bc",
X"b43fdf3f",
X"80f80b90",
X"80e03480",
X"0b9080c8",
X"88a03480",
X"0b908888",
X"34fa1252",
X"719080c0",
X"71908880",
X"34800b90",
X"80d83471",
X"9080d034",
X"9080f852",
X"88983471",
X"90889034",
X"9088b852",
X"807234b8",
X"7234833d",
X"0d04803d",
X"0d028b05",
X"33517090",
X"80f434fe",
X"bf3f83e0",
X"88b434fe",
X"bf3f83c0",
X"8008802e",
X"f638823d",
X"0d04803d",
X"0d853980",
X"c6853ffe",
X"d83f83e0",
X"c6873ffe",
X"d83f83c0",
X"8008802e",
X"f2389080",
X"f4337081",
X"ff0683e0",
X"f2389088",
X"b4337081",
X"ff0683c0",
X"800c5182",
X"3d0d0480",
X"3d0da30b",
X"9080fc34",
X"ff0b9080",
X"e8349080",
X"f851a871",
X"9088bc34",
X"ff0b9088",
X"a8349088",
X"b851a871",
X"34b87134",
X"823d0d04",
X"803d0d90",
X"80fc3370",
X"88bc3370",
X"81c00670",
X"30708025",
X"83e0800c",
X"83c0800c",
X"51515182",
X"3d0d0480",
X"3d0d9080",
X"f8337081",
X"3d0d9088",
X"b8337081",
X"ff067083",
X"2a813270",
X"81065151",
X"51517080",
X"2ee838b0",
X"0b9080f8",
X"0b9088b8",
X"34b80b90",
X"80f83482",
X"88b83482",
X"3d0d0480",
X"3d0d9080",
X"ac088106",
X"83e0800c",
X"83c0800c",
X"823d0d04",
X"fd3d0d75",
X"77545480",
X"73259438",
X"73708105",
X"55335280",
X"f5c85185",
X"55335281",
X"d3905185",
X"a13fff13",
X"53e93985",
X"3d0d04f6",
......
X"81558539",
X"747a2955",
X"74527551",
X"80ddf73f",
X"83e08008",
X"80de953f",
X"83c08008",
X"7a27ed38",
X"74802e80",
X"e0387452",
X"755180dd",
X"e13f83e0",
X"ff3f83c0",
X"80087553",
X"76525480",
X"dde43f83",
X"e080087a",
X"de823f83",
X"c080087a",
X"53755256",
X"80ddc73f",
X"83e08008",
X"80dde53f",
X"83c08008",
X"7930707b",
X"079f2a70",
X"77802407",
X"51515455",
X"72873883",
X"e08008c2",
X"c08008c2",
X"38768118",
X"b0165558",
X"58897425",
......
X"58810547",
X"fd833994",
X"3d0d0472",
X"83e0900c",
X"7183e094",
X"83c0900c",
X"7183c094",
X"0c04fb3d",
X"0d883d70",
X"70840552",
X"08575475",
X"5383e090",
X"085283e0",
X"5383c090",
X"085283c0",
X"940851fc",
X"c63f873d",
X"0d04ff3d",
......
X"0d04fd3d",
X"0d757052",
X"54a3c43f",
X"83e08008",
X"83c08008",
X"14537274",
X"2e9238ff",
X"13703353",
X"5371af2e",
X"098106ee",
X"38811353",
X"7283e080",
X"7283c080",
X"0c853d0d",
X"04fd3d0d",
X"75777053",
X"5454c73f",
X"83e08008",
X"83c08008",
X"732ea138",
X"83e08008",
X"83c08008",
X"733152ff",
X"125271ff",
X"2e8f3872",
......
X"3d0d7251",
X"ff903f82",
X"3d0d0471",
X"83e0800c",
X"83c0800c",
X"04803d0d",
X"72518071",
X"34810bbc",
X"120c800b",
X"80c0120c",
X"823d0d04",
X"800b83e2",
X"d408248a",
X"800b83c2",
X"e408248a",
X"38a4ae3f",
X"ff0b83e2",
X"d40c800b",
X"83e0800c",
X"ff0b83c2",
X"e40c800b",
X"83c0800c",
X"04ff3d0d",
X"735283e0",
X"b008722e",
X"735283c0",
X"c008722e",
X"8d38d93f",
X"71519699",
X"3f7183e0",
X"b00c833d",
X"3f7183c0",
X"c00c833d",
X"0d04f43d",
X"0d7e6062",
X"5c5a5581",
......
X"51cf3f79",
X"58807a25",
X"80f73883",
X"e3840870",
X"c3940870",
X"892a5783",
X"ff067884",
X"80723156",
X"56577378",
X"25833873",
X"557583e2",
X"d4082e84",
X"557583c2",
X"e4082e84",
X"38ff893f",
X"83e2d408",
X"83c2e408",
X"8025a638",
X"75892b51",
X"98dc3f83",
X"e384088f",
X"c394088f",
X"3dfc1155",
X"5c548152",
X"f81b5196",
X"c63f7614",
X"83e3840c",
X"7583e2d4",
X"83c3940c",
X"7583c2e4",
X"0c745376",
X"527851a2",
X"df3f83e0",
X"800883e3",
X"84081683",
X"e3840c78",
X"df3f83c0",
X"800883c3",
X"94081683",
X"c3940c78",
X"7631761b",
X"5b595677",
X"8024ff8b",
......
X"0c547554",
X"75802e83",
X"38815473",
X"83e0800c",
X"83c0800c",
X"8e3d0d04",
X"fc3d0dfe",
X"9b3f7651",
......
X"78527751",
X"95e93f79",
X"75710c54",
X"83e08008",
X"5483e080",
X"83c08008",
X"5483c080",
X"08802e83",
X"38815473",
X"83e0800c",
X"83c0800c",
X"863d0d04",
X"fe3d0d75",
X"83e2d408",
X"83c2e408",
X"53538072",
X"24893871",
X"732e8438",
X"fdd63f74",
X"51fdea3f",
X"725197ae",
X"3f83e080",
X"085283e0",
X"3f83c080",
X"085283c0",
X"8008802e",
X"83388152",
X"7183e080",
X"7183c080",
X"0c843d0d",
X"04803d0d",
X"7280c011",
X"0883e080",
X"0883c080",
X"0c51823d",
X"0d04803d",
X"0d72bc11",
X"0883e080",
X"0883c080",
X"0c51823d",
X"0d0480c4",
X"0b83e080",
X"0b83c080",
X"0c04fd3d",
... This diff was truncated because it exceeds the maximum size that can be displayed.

Also available in: Unified diff