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Revision 25

Added by markw over 11 years ago

Added video bits to generic, since I am having to adjust this everywhere.

View differences:

common/a8core/atari800core.vhd
GENERIC
(
cycle_length : integer := 16; -- or 32...
video_bits : integer := 8;
palette : integer :=1 -- 0:gtia colour on VGA_B, 1:altirra, 2:laoo
);
PORT
......
-- VIDEO OUT - PAL/NTSC, original Atari timings approx (may be higher res)
VGA_VS : OUT STD_LOGIC;
VGA_HS : OUT STD_LOGIC;
VGA_B : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
VGA_G : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
VGA_R : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
VGA_B : OUT STD_LOGIC_VECTOR(video_bits-1 DOWNTO 0);
VGA_G : OUT STD_LOGIC_VECTOR(video_bits-1 DOWNTO 0);
VGA_R : OUT STD_LOGIC_VECTOR(video_bits-1 DOWNTO 0);
-- AUDIO OUT - Pokey/GTIA 1-bit and Covox all mixed
-- TODO - choose stereo/mono pokey
......
signal COLOUR : std_logic_vector(7 downto 0);
-- GTIA PALETTE
signal VGA_R_WIDE : std_logic_vector(7 downto 0);
signal VGA_G_WIDE : std_logic_vector(7 downto 0);
signal VGA_B_WIDE : std_logic_vector(7 downto 0);
-- CPU
SIGNAL CPU_6502_RESET : STD_LOGIC;
SIGNAL CPU_ADDR : STD_LOGIC_VECTOR(15 DOWNTO 0);
......
gen_palette_altirra : if palette=1 generate
palette1 : entity work.gtia_palette(altirra)
port map (ATARI_COLOUR=>COLOUR, R_next=>VGA_R, G_next=>VGA_G, B_next=>VGA_B);
port map (ATARI_COLOUR=>COLOUR, R_next=>VGA_R_WIDE, G_next=>VGA_G_WIDE, B_next=>VGA_B_WIDE);
end generate;
gen_palette_laoo : if palette=2 generate
palette2 : entity work.gtia_palette(laoo)
port map (ATARI_COLOUR=>COLOUR, R_next=>VGA_R, G_next=>VGA_G, B_next=>VGA_B);
port map (ATARI_COLOUR=>COLOUR, R_next=>VGA_R_WIDE, G_next=>VGA_G_WIDE, B_next=>VGA_B_WIDE);
end generate;
VGA_R(video_bits-1 downto 0) <= VGA_R_WIDE(7 downto 8-video_bits);
VGA_G(video_bits-1 downto 0) <= VGA_G_WIDE(7 downto 8-video_bits);
VGA_B(video_bits-1 downto 0) <= VGA_B_WIDE(7 downto 8-video_bits);
irq_glue1 : entity work.irq_glue
PORT MAP(pokey_irq => POKEY_IRQ,
pia_irqa => PIA_IRQA,
common/a8core/atari800core_helloworld.vhd
-- use CLK of 1.79*cycle_length
-- I've tested 16 and 32 only, but 4 and 8 might work...
cycle_length : integer := 16; -- or 32...
video_bits : integer := 8;
internal_ram : integer := 16384 -- at start of memory map
);
......
-- VIDEO OUT - PAL/NTSC, original Atari timings approx (may be higher res)
VGA_VS : OUT STD_LOGIC;
VGA_HS : OUT STD_LOGIC;
VGA_B : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
VGA_G : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
VGA_R : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
VGA_B : OUT STD_LOGIC_VECTOR(video_bits-1 DOWNTO 0);
VGA_G : OUT STD_LOGIC_VECTOR(video_bits-1 DOWNTO 0);
VGA_R : OUT STD_LOGIC_VECTOR(video_bits-1 DOWNTO 0);
-- AUDIO OUT - Pokey/GTIA 1-bit and Covox all mixed
-- TODO - choose stereo/mono pokey
common/a8core/atari800core_simple_sdram.vhd
-- use CLK of 1.79*cycle_length
-- I've tested 16 and 32 only, but 4 and 8 might work...
cycle_length : integer := 16; -- or 32...
-- how many bits for video
video_bits : integer := 8;
-- For initial port may help to have no
internal_rom : integer := 1; -- if 0 expects it in sdram,is 1:16k os+basic, is 2:... TODO
......
-- VIDEO OUT - PAL/NTSC, original Atari timings approx (may be higher res)
VGA_VS : OUT STD_LOGIC;
VGA_HS : OUT STD_LOGIC;
VGA_B : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
VGA_G : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
VGA_R : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
VGA_B : OUT STD_LOGIC_VECTOR(video_bits-1 DOWNTO 0);
VGA_G : OUT STD_LOGIC_VECTOR(video_bits-1 DOWNTO 0);
VGA_R : OUT STD_LOGIC_VECTOR(video_bits-1 DOWNTO 0);
-- AUDIO OUT - Pokey/GTIA 1-bit and Covox all mixed
-- TODO - choose stereo/mono pokey
......
end atari800core_simple_sdram;
ARCHITECTURE vhdl OF atari800core_simple_sdram IS
-- PIA
SIGNAL CA1_IN : STD_LOGIC;
SIGNAL CB1_IN: STD_LOGIC;
SIGNAL CA2_OUT : STD_LOGIC;
SIGNAL CA2_DIR_OUT: STD_LOGIC;
SIGNAL CB2_OUT : STD_LOGIC;
SIGNAL CB2_DIR_OUT: STD_LOGIC;
SIGNAL CA2_IN: STD_LOGIC;
SIGNAL CB2_IN: STD_LOGIC;
SIGNAL PORTA_IN : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL PORTA_OUT : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL PORTA_DIR_OUT : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL PORTB_IN : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL PORTB_OUT : STD_LOGIC_VECTOR(7 DOWNTO 0);
--SIGNAL PORTB_DIR_OUT : STD_LOGIC_VECTOR(7 DOWNTO 0);
-- PIA
SIGNAL CA1_IN : STD_LOGIC;
SIGNAL CB1_IN: STD_LOGIC;
SIGNAL CA2_OUT : STD_LOGIC;
SIGNAL CA2_DIR_OUT: STD_LOGIC;
SIGNAL CB2_OUT : STD_LOGIC;
SIGNAL CB2_DIR_OUT: STD_LOGIC;
SIGNAL CA2_IN: STD_LOGIC;
SIGNAL CB2_IN: STD_LOGIC;
SIGNAL PORTA_IN : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL PORTA_OUT : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL PORTA_DIR_OUT : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL PORTB_IN : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL PORTB_OUT : STD_LOGIC_VECTOR(7 DOWNTO 0);
--SIGNAL PORTB_DIR_OUT : STD_LOGIC_VECTOR(7 DOWNTO 0);
-- GTIA
signal GTIA_TRIG : std_logic_vector(3 downto 0);
-- ANTIC
signal ANTIC_LIGHTPEN : std_logic;
-- CARTRIDGE ACCESS
SIGNAL CART_RD4 : STD_LOGIC;
SIGNAL CART_RD5 : STD_LOGIC;
-- PBI
SIGNAL PBI_WRITE_DATA : std_logic_vector(31 downto 0);
-- INTERNAL ROM/RAM
SIGNAL RAM_ADDR : STD_LOGIC_VECTOR(18 DOWNTO 0);
SIGNAL RAM_DO : STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL RAM_REQUEST : STD_LOGIC;
SIGNAL RAM_REQUEST_COMPLETE : STD_LOGIC;
SIGNAL RAM_WRITE_ENABLE : STD_LOGIC;
SIGNAL ROM_ADDR : STD_LOGIC_VECTOR(21 DOWNTO 0);
SIGNAL ROM_DO : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL ROM_REQUEST : STD_LOGIC;
SIGNAL ROM_REQUEST_COMPLETE : STD_LOGIC;
-- CONFIG
SIGNAL USE_SDRAM : STD_LOGIC;
SIGNAL ROM_IN_RAM : STD_LOGIC;
-- GTIA
signal GTIA_TRIG : std_logic_vector(3 downto 0);
-- ANTIC
signal ANTIC_LIGHTPEN : std_logic;
-- CARTRIDGE ACCESS
SIGNAL CART_RD4 : STD_LOGIC;
SIGNAL CART_RD5 : STD_LOGIC;
-- PBI
SIGNAL PBI_WRITE_DATA : std_logic_vector(31 downto 0);
-- INTERNAL ROM/RAM
SIGNAL RAM_ADDR : STD_LOGIC_VECTOR(18 DOWNTO 0);
SIGNAL RAM_DO : STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL RAM_REQUEST : STD_LOGIC;
SIGNAL RAM_REQUEST_COMPLETE : STD_LOGIC;
SIGNAL RAM_WRITE_ENABLE : STD_LOGIC;
SIGNAL ROM_ADDR : STD_LOGIC_VECTOR(21 DOWNTO 0);
SIGNAL ROM_DO : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL ROM_REQUEST : STD_LOGIC;
SIGNAL ROM_REQUEST_COMPLETE : STD_LOGIC;
-- CONFIG
SIGNAL USE_SDRAM : STD_LOGIC;
SIGNAL ROM_IN_RAM : STD_LOGIC;
BEGIN
-- PIA mapping
......
atari800xl : entity work.atari800core
GENERIC MAP
(
cycle_length => cycle_length
cycle_length => cycle_length,
video_bits => video_bits
)
PORT MAP
(
......
KEYBOARD_SCAN => KEYBOARD_SCAN,
POT_IN => "00000000",
POT_RESET => open,
POT_RESET => open,
-- PBI
PBI_ADDR => open,
......
DMA_WRITE_DATA => DMA_WRITE_DATA,
MEMORY_READY_DMA => MEMORY_READY_DMA,
RAM_SELECT => RAM_SELECT,
ROM_SELECT => ROM_SELECT,
RAM_SELECT => RAM_SELECT,
ROM_SELECT => ROM_SELECT,
CART_EMULATION_SELECT => "0000000",
CART_EMULATION_ACTIVATE => '0',
PAL => PAL,

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