Revision 235
Added by markw almost 11 years ago
| de1_5200/atari800core.qsf | ||
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# -------------------------------------------------------------------------- #
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#
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# Copyright (C) 1991-2012 Altera Corporation
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# Your use of Altera Corporation's design tools, logic functions
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# and other software and tools, and its AMPP partner logic
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# functions, and any output files from any of the foregoing
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# (including device programming or simulation files), and any
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# associated documentation or information are expressly subject
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# to the terms and conditions of the Altera Program License
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# Subscription Agreement, Altera MegaCore Function License
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# Agreement, or other applicable license agreement, including,
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# without limitation, that your use is for the sole purpose of
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# programming logic devices manufactured by Altera and sold by
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# Altera or its authorized distributors. Please refer to the
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# applicable agreement for further details.
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#
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# -------------------------------------------------------------------------- #
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#
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# Quartus II 64-Bit
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# Version 12.1 Build 243 01/31/2013 Service Pack 1 SJ Web Edition
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# Date created = 13:58:39 April 11, 2013
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#
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# -------------------------------------------------------------------------- #
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#
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# Notes:
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#
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# 1) The default values for assignments are stored in the file:
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# atari800core_assignment_defaults.qdf
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# If this file doesn't exist, see file:
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# assignment_defaults.qdf
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#
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# 2) Altera recommends that you do not modify this file. This
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# file is updated automatically by the Quartus II software
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# and any changes you make may be lost or overwritten.
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#
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# -------------------------------------------------------------------------- #
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set_global_assignment -name FAMILY "Cyclone II"
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set_global_assignment -name DEVICE EP2C20F484C7
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set_global_assignment -name TOP_LEVEL_ENTITY atari800core_de1
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set_global_assignment -name ORIGINAL_QUARTUS_VERSION "12.1 SP1"
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set_global_assignment -name PROJECT_CREATION_TIME_DATE "13:58:39 APRIL 11, 2013"
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set_global_assignment -name LAST_QUARTUS_VERSION "12.1 SP1.33"
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set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
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set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
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set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
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set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
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set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
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set_location_assignment PIN_A15 -to GPIO_0[4]
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set_location_assignment PIN_B15 -to GPIO_0[5]
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set_location_assignment PIN_A16 -to GPIO_0[6]
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set_location_assignment PIN_B16 -to GPIO_0[7]
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set_location_assignment PIN_A17 -to GPIO_0[8]
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set_location_assignment PIN_B17 -to GPIO_0[9]
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set_location_assignment PIN_A18 -to GPIO_0[10]
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set_location_assignment PIN_B18 -to GPIO_0[11]
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set_location_assignment PIN_A19 -to GPIO_0[12]
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set_location_assignment PIN_B19 -to GPIO_0[13]
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set_location_assignment PIN_A20 -to GPIO_0[14]
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set_location_assignment PIN_B20 -to GPIO_0[15]
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set_location_assignment PIN_C21 -to GPIO_0[16]
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set_location_assignment PIN_C22 -to GPIO_0[17]
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set_location_assignment PIN_D21 -to GPIO_0[18]
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set_location_assignment PIN_D22 -to GPIO_0[19]
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set_location_assignment PIN_E21 -to GPIO_0[20]
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set_location_assignment PIN_E22 -to GPIO_0[21]
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set_location_assignment PIN_F21 -to GPIO_0[22]
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set_location_assignment PIN_F22 -to GPIO_0[23]
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set_location_assignment PIN_G21 -to GPIO_0[24]
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set_location_assignment PIN_G22 -to GPIO_0[25]
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set_location_assignment PIN_J21 -to GPIO_0[26]
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set_location_assignment PIN_J22 -to GPIO_0[27]
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set_location_assignment PIN_K21 -to GPIO_0[28]
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set_location_assignment PIN_K22 -to GPIO_0[29]
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set_location_assignment PIN_J19 -to GPIO_0[30]
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set_location_assignment PIN_J20 -to GPIO_0[31]
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set_location_assignment PIN_J18 -to GPIO_0[32]
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set_location_assignment PIN_K20 -to GPIO_0[33]
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set_location_assignment PIN_L19 -to GPIO_0[34]
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set_location_assignment PIN_L18 -to GPIO_0[35]
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set_location_assignment PIN_H12 -to GPIO_1[0]
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set_location_assignment PIN_H13 -to GPIO_1[1]
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set_location_assignment PIN_H14 -to GPIO_1[2]
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set_location_assignment PIN_G15 -to GPIO_1[3]
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set_location_assignment PIN_E14 -to GPIO_1[4]
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set_location_assignment PIN_E15 -to GPIO_1[5]
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set_location_assignment PIN_F15 -to GPIO_1[6]
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set_location_assignment PIN_G16 -to GPIO_1[7]
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set_location_assignment PIN_F12 -to GPIO_1[8]
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set_location_assignment PIN_F13 -to GPIO_1[9]
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set_location_assignment PIN_C14 -to GPIO_1[10]
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set_location_assignment PIN_D14 -to GPIO_1[11]
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set_location_assignment PIN_D15 -to GPIO_1[12]
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set_location_assignment PIN_D16 -to GPIO_1[13]
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set_location_assignment PIN_C17 -to GPIO_1[14]
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set_location_assignment PIN_C18 -to GPIO_1[15]
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set_location_assignment PIN_C19 -to GPIO_1[16]
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set_location_assignment PIN_C20 -to GPIO_1[17]
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set_location_assignment PIN_D19 -to GPIO_1[18]
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set_location_assignment PIN_D20 -to GPIO_1[19]
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set_location_assignment PIN_E20 -to GPIO_1[20]
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set_location_assignment PIN_F20 -to GPIO_1[21]
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set_location_assignment PIN_E19 -to GPIO_1[22]
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set_location_assignment PIN_E18 -to GPIO_1[23]
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set_location_assignment PIN_G20 -to GPIO_1[24]
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set_location_assignment PIN_G18 -to GPIO_1[25]
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set_location_assignment PIN_G17 -to GPIO_1[26]
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set_location_assignment PIN_H17 -to GPIO_1[27]
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set_location_assignment PIN_J15 -to GPIO_1[28]
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set_location_assignment PIN_H18 -to GPIO_1[29]
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set_location_assignment PIN_N22 -to GPIO_1[30]
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set_location_assignment PIN_N21 -to GPIO_1[31]
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set_location_assignment PIN_P15 -to GPIO_1[32]
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set_location_assignment PIN_N15 -to GPIO_1[33]
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set_location_assignment PIN_P17 -to GPIO_1[34]
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set_location_assignment PIN_P18 -to GPIO_1[35]
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set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[0]
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set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[1]
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set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[2]
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set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[3]
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set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[4]
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set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[5]
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set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[6]
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set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[7]
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set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[8]
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set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[9]
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set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[10]
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set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[11]
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set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[12]
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set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[13]
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set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[14]
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set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[15]
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set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[16]
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set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[17]
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set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[18]
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set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[19]
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set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[20]
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set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[21]
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set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[22]
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set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[23]
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set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[24]
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set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[25]
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set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to GPIO_0[26]
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set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[27]
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set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[28]
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[29]
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set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[30]
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set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[31]
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set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[32]
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set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[33]
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set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[34]
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set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[35]
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set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[0]
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set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[1]
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set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[2]
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set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[3]
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set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[4]
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set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[5]
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set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[6]
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set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[7]
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set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[8]
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set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[9]
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set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[10]
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set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[11]
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set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[12]
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set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[13]
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set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[14]
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set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[15]
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set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[16]
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set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[17]
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set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[18]
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set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[19]
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set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[20]
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set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[21]
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set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[22]
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set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[23]
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set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[24]
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set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[25]
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set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[26]
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set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[27]
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set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[28]
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set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[29]
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set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[30]
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set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[31]
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set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[32]
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set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[33]
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set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[34]
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set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[35]
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set_location_assignment PIN_L22 -to SW[0]
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set_location_assignment PIN_L21 -to SW[1]
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set_location_assignment PIN_M22 -to SW[2]
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set_location_assignment PIN_V12 -to SW[3]
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set_location_assignment PIN_W12 -to SW[4]
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set_location_assignment PIN_U12 -to SW[5]
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set_location_assignment PIN_U11 -to SW[6]
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set_location_assignment PIN_M2 -to SW[7]
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set_location_assignment PIN_M1 -to SW[8]
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set_location_assignment PIN_L2 -to SW[9]
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set_instance_assignment -name IO_STANDARD LVTTL -to SW[0]
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set_instance_assignment -name IO_STANDARD LVTTL -to SW[1]
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set_instance_assignment -name IO_STANDARD LVTTL -to SW[2]
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set_instance_assignment -name IO_STANDARD LVTTL -to SW[3]
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set_instance_assignment -name IO_STANDARD LVTTL -to SW[4]
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set_instance_assignment -name IO_STANDARD LVTTL -to SW[5]
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set_instance_assignment -name IO_STANDARD LVTTL -to SW[6]
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set_instance_assignment -name IO_STANDARD LVTTL -to SW[7]
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set_instance_assignment -name IO_STANDARD LVTTL -to SW[8]
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set_instance_assignment -name IO_STANDARD LVTTL -to SW[9]
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set_location_assignment PIN_J2 -to HEX0[0]
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set_location_assignment PIN_J1 -to HEX0[1]
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set_location_assignment PIN_H2 -to HEX0[2]
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set_location_assignment PIN_H1 -to HEX0[3]
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set_location_assignment PIN_F2 -to HEX0[4]
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set_location_assignment PIN_F1 -to HEX0[5]
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set_location_assignment PIN_E2 -to HEX0[6]
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set_location_assignment PIN_E1 -to HEX1[0]
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set_location_assignment PIN_H6 -to HEX1[1]
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set_location_assignment PIN_H5 -to HEX1[2]
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set_location_assignment PIN_H4 -to HEX1[3]
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set_location_assignment PIN_G3 -to HEX1[4]
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set_location_assignment PIN_D2 -to HEX1[5]
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set_location_assignment PIN_D1 -to HEX1[6]
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set_location_assignment PIN_G5 -to HEX2[0]
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set_location_assignment PIN_G6 -to HEX2[1]
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set_location_assignment PIN_C2 -to HEX2[2]
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set_location_assignment PIN_C1 -to HEX2[3]
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set_location_assignment PIN_E3 -to HEX2[4]
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set_location_assignment PIN_E4 -to HEX2[5]
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set_location_assignment PIN_D3 -to HEX2[6]
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set_location_assignment PIN_F4 -to HEX3[0]
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set_location_assignment PIN_D5 -to HEX3[1]
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set_location_assignment PIN_D6 -to HEX3[2]
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set_location_assignment PIN_J4 -to HEX3[3]
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set_location_assignment PIN_L8 -to HEX3[4]
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set_location_assignment PIN_F3 -to HEX3[5]
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set_location_assignment PIN_D4 -to HEX3[6]
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set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[0]
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set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[1]
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set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[2]
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set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[3]
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set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[4]
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set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[5]
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set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[6]
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set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[0]
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set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[1]
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set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[2]
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set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[3]
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set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[4]
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set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[5]
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set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[6]
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set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[0]
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set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[1]
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set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[2]
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set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[3]
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set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[4]
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set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[5]
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set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[6]
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set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[0]
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set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[1]
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set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[2]
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set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[3]
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set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[4]
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set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[5]
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set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[6]
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set_location_assignment PIN_R22 -to KEY[0]
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set_location_assignment PIN_R21 -to KEY[1]
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set_location_assignment PIN_T22 -to KEY[2]
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set_location_assignment PIN_T21 -to KEY[3]
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set_location_assignment PIN_R20 -to LEDR[0]
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set_location_assignment PIN_R19 -to LEDR[1]
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set_location_assignment PIN_U19 -to LEDR[2]
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set_location_assignment PIN_Y19 -to LEDR[3]
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set_location_assignment PIN_T18 -to LEDR[4]
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set_location_assignment PIN_V19 -to LEDR[5]
|
||
|
set_location_assignment PIN_Y18 -to LEDR[6]
|
||
|
set_location_assignment PIN_U18 -to LEDR[7]
|
||
|
set_location_assignment PIN_R18 -to LEDR[8]
|
||
|
set_location_assignment PIN_R17 -to LEDR[9]
|
||
|
set_location_assignment PIN_U22 -to LEDG[0]
|
||
|
set_location_assignment PIN_U21 -to LEDG[1]
|
||
|
set_location_assignment PIN_V22 -to LEDG[2]
|
||
|
set_location_assignment PIN_V21 -to LEDG[3]
|
||
|
set_location_assignment PIN_W22 -to LEDG[4]
|
||
|
set_location_assignment PIN_W21 -to LEDG[5]
|
||
|
set_location_assignment PIN_Y22 -to LEDG[6]
|
||
|
set_location_assignment PIN_Y21 -to LEDG[7]
|
||
|
set_instance_assignment -name IO_STANDARD LVTTL -to KEY[0]
|
||
|
set_instance_assignment -name IO_STANDARD LVTTL -to KEY[1]
|
||
|
set_instance_assignment -name IO_STANDARD LVTTL -to KEY[2]
|
||
|
set_instance_assignment -name IO_STANDARD LVTTL -to KEY[3]
|
||
|
set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[0]
|
||
|
set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[1]
|
||
|
set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[2]
|
||
|
set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[3]
|
||
|
set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[4]
|
||
|
set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[5]
|
||
|
set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[6]
|
||
|
set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[7]
|
||
|
set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[8]
|
||
|
set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[9]
|
||
|
set_instance_assignment -name IO_STANDARD LVTTL -to LEDG[0]
|
||
|
set_instance_assignment -name IO_STANDARD LVTTL -to LEDG[1]
|
||
|
set_instance_assignment -name IO_STANDARD LVTTL -to LEDG[2]
|
||
|
set_instance_assignment -name IO_STANDARD LVTTL -to LEDG[3]
|
||
|
set_instance_assignment -name IO_STANDARD LVTTL -to LEDG[4]
|
||
|
set_instance_assignment -name IO_STANDARD LVTTL -to LEDG[5]
|
||
|
set_instance_assignment -name IO_STANDARD LVTTL -to LEDG[6]
|
||
|
set_instance_assignment -name IO_STANDARD LVTTL -to LEDG[7]
|
||
|
set_location_assignment PIN_D12 -to CLOCK_27[0]
|
||
|
set_location_assignment PIN_E12 -to CLOCK_27[1]
|
||
|
set_location_assignment PIN_B12 -to CLOCK_24[0]
|
||
|
set_location_assignment PIN_A12 -to CLOCK_24[1]
|
||
|
set_location_assignment PIN_L1 -to CLOCK_50
|
||
|
set_location_assignment PIN_M21 -to EXT_CLOCK
|
||
|
set_instance_assignment -name IO_STANDARD LVTTL -to CLOCK_27[1]
|
||
|
set_instance_assignment -name IO_STANDARD LVTTL -to CLOCK_24[0]
|
||
|
set_instance_assignment -name IO_STANDARD LVTTL -to CLOCK_24[1]
|
||
|
set_instance_assignment -name IO_STANDARD LVTTL -to CLOCK_50
|
||
|
set_instance_assignment -name IO_STANDARD LVTTL -to EXT_CLOCK
|
||
|
set_location_assignment PIN_H15 -to PS2_CLK
|
||
|
set_location_assignment PIN_J14 -to PS2_DAT
|
||
|
set_location_assignment PIN_F14 -to UART_RXD
|
||
|
set_location_assignment PIN_G12 -to UART_TXD
|
||
|
set_instance_assignment -name IO_STANDARD LVTTL -to PS2_CLK
|
||
|
set_instance_assignment -name IO_STANDARD LVTTL -to PS2_DAT
|
||
|
set_instance_assignment -name IO_STANDARD LVTTL -to UART_RXD
|
||
|
set_instance_assignment -name IO_STANDARD LVTTL -to UART_TXD
|
||
|
set_location_assignment PIN_E8 -to TDI
|
||
|
set_location_assignment PIN_D8 -to TCS
|
||
|
set_location_assignment PIN_C7 -to TCK
|
||
|
set_location_assignment PIN_D7 -to TDO
|
||
|
set_instance_assignment -name IO_STANDARD LVTTL -to TDI
|
||
|
set_instance_assignment -name IO_STANDARD LVTTL -to TCS
|
||
|
set_instance_assignment -name IO_STANDARD LVTTL -to TCK
|
||
|
set_instance_assignment -name IO_STANDARD LVTTL -to TDO
|
||
|
set_location_assignment PIN_D9 -to VGA_R[0]
|
||
|
set_location_assignment PIN_C9 -to VGA_R[1]
|
||
|
set_location_assignment PIN_A7 -to VGA_R[2]
|
||
|
set_location_assignment PIN_B7 -to VGA_R[3]
|
||
|
set_location_assignment PIN_B8 -to VGA_G[0]
|
||
|
set_location_assignment PIN_C10 -to VGA_G[1]
|
||
|
set_location_assignment PIN_B9 -to VGA_G[2]
|
||
|
set_location_assignment PIN_A8 -to VGA_G[3]
|
||
|
set_location_assignment PIN_A9 -to VGA_B[0]
|
||
|
set_location_assignment PIN_D11 -to VGA_B[1]
|
||
|
set_location_assignment PIN_A10 -to VGA_B[2]
|
||
|
set_location_assignment PIN_B10 -to VGA_B[3]
|
||
|
set_location_assignment PIN_A11 -to VGA_HS
|
||
|
set_location_assignment PIN_B11 -to VGA_VS
|
||
|
set_instance_assignment -name IO_STANDARD LVTTL -to VGA_R[0]
|
||
|
set_instance_assignment -name IO_STANDARD LVTTL -to VGA_R[1]
|
||
|
set_instance_assignment -name IO_STANDARD LVTTL -to VGA_R[2]
|
||
|
set_instance_assignment -name IO_STANDARD LVTTL -to VGA_R[3]
|
||
|
set_instance_assignment -name IO_STANDARD LVTTL -to VGA_G[0]
|
||
|
set_instance_assignment -name IO_STANDARD LVTTL -to VGA_G[1]
|
||
|
set_instance_assignment -name IO_STANDARD LVTTL -to VGA_G[2]
|
||
|
set_instance_assignment -name IO_STANDARD LVTTL -to VGA_G[3]
|
||
|
set_instance_assignment -name IO_STANDARD LVTTL -to VGA_B[0]
|
||
|
set_instance_assignment -name IO_STANDARD LVTTL -to VGA_B[1]
|
||
|
set_instance_assignment -name IO_STANDARD LVTTL -to VGA_B[2]
|
||
|
set_instance_assignment -name IO_STANDARD LVTTL -to VGA_B[3]
|
||
|
set_instance_assignment -name IO_STANDARD LVTTL -to VGA_HS
|
||
|
set_instance_assignment -name IO_STANDARD LVTTL -to VGA_VS
|
||
|
set_location_assignment PIN_A3 -to I2C_SCLK
|
||
|
set_location_assignment PIN_B3 -to I2C_SDAT
|
||
|
set_location_assignment PIN_A6 -to AUD_ADCLRCK
|
||
|
set_location_assignment PIN_B6 -to AUD_ADCDAT
|
||
|
set_location_assignment PIN_A5 -to AUD_DACLRCK
|
||
|
set_location_assignment PIN_B5 -to AUD_DACDAT
|
||
|
set_location_assignment PIN_B4 -to AUD_XCK
|
||
|
set_location_assignment PIN_A4 -to AUD_BCLK
|
||
|
set_instance_assignment -name IO_STANDARD LVTTL -to I2C_SCLK
|
||
|
set_instance_assignment -name IO_STANDARD LVTTL -to I2C_SDAT
|
||
|
set_instance_assignment -name IO_STANDARD LVTTL -to AUD_ADCLRCK
|
||
|
set_instance_assignment -name IO_STANDARD LVTTL -to AUD_ADCDAT
|
||
|
set_instance_assignment -name IO_STANDARD LVTTL -to AUD_DACLRCK
|
||
|
set_instance_assignment -name IO_STANDARD LVTTL -to AUD_DACDAT
|
||
|
set_instance_assignment -name IO_STANDARD LVTTL -to AUD_XCK
|
||
|
set_instance_assignment -name IO_STANDARD LVTTL -to AUD_BCLK
|
||
|
set_location_assignment PIN_W4 -to DRAM_ADDR[0]
|
||
|
set_location_assignment PIN_W5 -to DRAM_ADDR[1]
|
||
|
set_location_assignment PIN_Y3 -to DRAM_ADDR[2]
|
||
|
set_location_assignment PIN_Y4 -to DRAM_ADDR[3]
|
||
|
set_location_assignment PIN_R6 -to DRAM_ADDR[4]
|
||
|
set_location_assignment PIN_R5 -to DRAM_ADDR[5]
|
||
|
set_location_assignment PIN_P6 -to DRAM_ADDR[6]
|
||
|
set_location_assignment PIN_P5 -to DRAM_ADDR[7]
|
||
|
set_location_assignment PIN_P3 -to DRAM_ADDR[8]
|
||
|
set_location_assignment PIN_N4 -to DRAM_ADDR[9]
|
||
|
set_location_assignment PIN_W3 -to DRAM_ADDR[10]
|
||
|
set_location_assignment PIN_N6 -to DRAM_ADDR[11]
|
||
|
set_location_assignment PIN_U3 -to DRAM_BA_0
|
||
|
set_location_assignment PIN_V4 -to DRAM_BA_1
|
||
|
set_location_assignment PIN_T3 -to DRAM_CAS_N
|
||
|
set_location_assignment PIN_N3 -to DRAM_CKE
|
||
|
set_location_assignment PIN_U4 -to DRAM_CLK
|
||
|
set_location_assignment PIN_T6 -to DRAM_CS_N
|
||
|
set_location_assignment PIN_U1 -to DRAM_DQ[0]
|
||
|
set_location_assignment PIN_U2 -to DRAM_DQ[1]
|
||
|
set_location_assignment PIN_V1 -to DRAM_DQ[2]
|
||
|
set_location_assignment PIN_V2 -to DRAM_DQ[3]
|
||
|
set_location_assignment PIN_W1 -to DRAM_DQ[4]
|
||
|
set_location_assignment PIN_W2 -to DRAM_DQ[5]
|
||
|
set_location_assignment PIN_Y1 -to DRAM_DQ[6]
|
||
|
set_location_assignment PIN_Y2 -to DRAM_DQ[7]
|
||
|
set_location_assignment PIN_N1 -to DRAM_DQ[8]
|
||
|
set_location_assignment PIN_N2 -to DRAM_DQ[9]
|
||
|
set_location_assignment PIN_P1 -to DRAM_DQ[10]
|
||
|
set_location_assignment PIN_P2 -to DRAM_DQ[11]
|
||
|
set_location_assignment PIN_R1 -to DRAM_DQ[12]
|
||
|
set_location_assignment PIN_R2 -to DRAM_DQ[13]
|
||
|
set_location_assignment PIN_T1 -to DRAM_DQ[14]
|
||
|
set_location_assignment PIN_T2 -to DRAM_DQ[15]
|
||
|
set_location_assignment PIN_R7 -to DRAM_LDQM
|
||
|
set_location_assignment PIN_T5 -to DRAM_RAS_N
|
||
|
set_location_assignment PIN_M5 -to DRAM_UDQM
|
||
|
set_location_assignment PIN_R8 -to DRAM_WE_N
|
||
|
set_location_assignment PIN_AB20 -to FL_ADDR[0]
|
||
|
set_location_assignment PIN_AA14 -to FL_ADDR[1]
|
||
|
set_location_assignment PIN_Y16 -to FL_ADDR[2]
|
||
|
set_location_assignment PIN_R15 -to FL_ADDR[3]
|
||
|
set_location_assignment PIN_T15 -to FL_ADDR[4]
|
||
|
set_location_assignment PIN_U15 -to FL_ADDR[5]
|
||
|
set_location_assignment PIN_V15 -to FL_ADDR[6]
|
||
|
set_location_assignment PIN_W15 -to FL_ADDR[7]
|
||
|
set_location_assignment PIN_R14 -to FL_ADDR[8]
|
||
|
set_location_assignment PIN_Y13 -to FL_ADDR[9]
|
||
|
set_location_assignment PIN_R12 -to FL_ADDR[10]
|
||
|
set_location_assignment PIN_T12 -to FL_ADDR[11]
|
||
|
set_location_assignment PIN_AB14 -to FL_ADDR[12]
|
||
|
set_location_assignment PIN_AA13 -to FL_ADDR[13]
|
||
|
set_location_assignment PIN_AB13 -to FL_ADDR[14]
|
||
|
set_location_assignment PIN_AA12 -to FL_ADDR[15]
|
||
|
set_location_assignment PIN_AB12 -to FL_ADDR[16]
|
||
|
set_location_assignment PIN_AA20 -to FL_ADDR[17]
|
||
|
set_location_assignment PIN_U14 -to FL_ADDR[18]
|
||
|
set_location_assignment PIN_V14 -to FL_ADDR[19]
|
||
|
set_location_assignment PIN_U13 -to FL_ADDR[20]
|
||
|
set_location_assignment PIN_R13 -to FL_ADDR[21]
|
||
|
set_location_assignment PIN_AB16 -to FL_DQ[0]
|
||
|
set_location_assignment PIN_AA16 -to FL_DQ[1]
|
||
|
set_location_assignment PIN_AB17 -to FL_DQ[2]
|
||
|
set_location_assignment PIN_AA17 -to FL_DQ[3]
|
||
|
set_location_assignment PIN_AB18 -to FL_DQ[4]
|
||
|
set_location_assignment PIN_AA18 -to FL_DQ[5]
|
||
|
set_location_assignment PIN_AB19 -to FL_DQ[6]
|
||
|
set_location_assignment PIN_AA19 -to FL_DQ[7]
|
||
|
set_location_assignment PIN_AA15 -to FL_OE_N
|
||
|
set_location_assignment PIN_W14 -to FL_RST_N
|
||
|
set_location_assignment PIN_Y14 -to FL_WE_N
|
||
|
set_location_assignment PIN_AA3 -to SRAM_ADDR[0]
|
||
|
set_location_assignment PIN_AB3 -to SRAM_ADDR[1]
|
||
|
set_location_assignment PIN_AA4 -to SRAM_ADDR[2]
|
||
|
set_location_assignment PIN_AB4 -to SRAM_ADDR[3]
|
||
|
set_location_assignment PIN_AA5 -to SRAM_ADDR[4]
|
||
|
set_location_assignment PIN_AB10 -to SRAM_ADDR[5]
|
||
|
set_location_assignment PIN_AA11 -to SRAM_ADDR[6]
|
||
|
set_location_assignment PIN_AB11 -to SRAM_ADDR[7]
|
||
|
set_location_assignment PIN_V11 -to SRAM_ADDR[8]
|
||
|
set_location_assignment PIN_W11 -to SRAM_ADDR[9]
|
||
|
set_location_assignment PIN_R11 -to SRAM_ADDR[10]
|
||
|
set_location_assignment PIN_T11 -to SRAM_ADDR[11]
|
||
|
set_location_assignment PIN_Y10 -to SRAM_ADDR[12]
|
||
|
set_location_assignment PIN_U10 -to SRAM_ADDR[13]
|
||
|
set_location_assignment PIN_R10 -to SRAM_ADDR[14]
|
||
|
set_location_assignment PIN_T7 -to SRAM_ADDR[15]
|
||
|
set_location_assignment PIN_Y6 -to SRAM_ADDR[16]
|
||
|
set_location_assignment PIN_Y5 -to SRAM_ADDR[17]
|
||
|
set_location_assignment PIN_AB5 -to SRAM_CE_N
|
||
|
set_location_assignment PIN_AA6 -to SRAM_DQ[0]
|
||
|
set_location_assignment PIN_AB6 -to SRAM_DQ[1]
|
||
|
set_location_assignment PIN_AA7 -to SRAM_DQ[2]
|
||
|
set_location_assignment PIN_AB7 -to SRAM_DQ[3]
|
||
|
set_location_assignment PIN_AA8 -to SRAM_DQ[4]
|
||
|
set_location_assignment PIN_AB8 -to SRAM_DQ[5]
|
||
|
set_location_assignment PIN_AA9 -to SRAM_DQ[6]
|
||
|
set_location_assignment PIN_AB9 -to SRAM_DQ[7]
|
||
|
set_location_assignment PIN_Y9 -to SRAM_DQ[8]
|
||
|
set_location_assignment PIN_W9 -to SRAM_DQ[9]
|
||
|
set_location_assignment PIN_V9 -to SRAM_DQ[10]
|
||
|
set_location_assignment PIN_U9 -to SRAM_DQ[11]
|
||
|
set_location_assignment PIN_R9 -to SRAM_DQ[12]
|
||
|
set_location_assignment PIN_W8 -to SRAM_DQ[13]
|
||
|
set_location_assignment PIN_V8 -to SRAM_DQ[14]
|
||
|
set_location_assignment PIN_U8 -to SRAM_DQ[15]
|
||
|
set_location_assignment PIN_Y7 -to SRAM_LB_N
|
||
|
set_location_assignment PIN_T8 -to SRAM_OE_N
|
||
|
set_location_assignment PIN_W7 -to SRAM_UB_N
|
||
|
set_location_assignment PIN_AA10 -to SRAM_WE_N
|
||
|
set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_CE_N
|
||
|
set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_LB_N
|
||
|
set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_OE_N
|
||
|
set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_UB_N
|
||
|
set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_WE_N
|
||
|
set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_ADDR[0]
|
||
|
set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_ADDR[1]
|
||
|
set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_ADDR[2]
|
||
|
set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_ADDR[3]
|
||
|
set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_ADDR[4]
|
||
|
set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_ADDR[5]
|
||
|
set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_ADDR[6]
|
||
|
set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_ADDR[7]
|
||
|
set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_ADDR[8]
|
||
|
set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_ADDR[9]
|
||
|
set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_ADDR[10]
|
||
|
set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_ADDR[11]
|
||
|
set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_ADDR[12]
|
||
|
set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_ADDR[13]
|
||
|
set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_ADDR[14]
|
||
|
set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_ADDR[15]
|
||
|
set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_ADDR[16]
|
||
|
set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_ADDR[17]
|
||
|
set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_DQ[0]
|
||
|
set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_DQ[1]
|
||
|
set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_DQ[2]
|
||
|
set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_DQ[3]
|
||
|
set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_DQ[4]
|
||
|
set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_DQ[5]
|
||
|
set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_DQ[6]
|
||
|
set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_DQ[7]
|
||
|
set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_DQ[8]
|
||
|
set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_DQ[9]
|
||
|
set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_DQ[10]
|
||
|
set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_DQ[11]
|
||
|
set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_DQ[12]
|
||
|
set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_DQ[13]
|
||
|
set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_DQ[14]
|
||
|
set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_DQ[15]
|
||
|
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
|
||
|
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
|
||
|
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
|
||
|
set_global_assignment -name ENABLE_SIGNALTAP ON
|
||
|
set_location_assignment PIN_V20 -to SD_CLK
|
||
|
set_location_assignment PIN_Y20 -to SD_CMD
|
||
|
set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
|
||
|
set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
|
||
|
set_global_assignment -name USE_CONFIGURATION_DEVICE ON
|
||
|
set_global_assignment -name STRATIX_CONFIGURATION_DEVICE EPCS4
|
||
|
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS OFF
|
||
|
set_global_assignment -name BLOCK_DESIGN_NAMING AUTO
|
||
|
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
|
||
|
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
|
||
|
set_location_assignment PIN_W20 -to SD_DATA
|
||
|
set_location_assignment PIN_U20 -to SD_THREE
|
||
|
set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
|
||
|
set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "USE AS REGULAR IO"
|
||
|
set_global_assignment -name SMART_RECOMPILE ON
|
||
|
set_global_assignment -name ENABLE_DRC_SETTINGS ON
|
||
|
set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED
|
||
|
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC OFF
|
||
|
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION OFF
|
||
|
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING OFF
|
||
|
set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL MAXIMUM
|
||
|
set_global_assignment -name AUTO_PACKED_REGISTERS_STRATIXII NORMAL
|
||
|
set_global_assignment -name FITTER_EFFORT "AUTO FIT"
|
||
|
set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"
|
||
|
set_location_assignment PIN_A13 -to GPIO_0[0]
|
||
|
set_location_assignment PIN_B13 -to GPIO_0[1]
|
||
|
set_location_assignment PIN_A14 -to GPIO_0[2]
|
||
|
set_location_assignment PIN_B14 -to GPIO_0[3]
|
||
|
|
||
|
set_global_assignment -name USE_SIGNALTAP_FILE output_files/stp1.stp
|
||
|
set_global_assignment -name SIGNALTAP_FILE output_files/stp1.stp
|
||
|
|
||
|
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
|
||
|
|
||
|
set_global_assignment -name VHDL_FILE gpio.vhd
|
||
|
set_global_assignment -name VHDL_FILE atari800core_de1.vhd
|
||
|
set_global_assignment -name VHDL_FILE hexdecoder.vhd
|
||
|
set_global_assignment -name VHDL_FILE i2c_loader.vhd
|
||
|
set_global_assignment -name VHDL_FILE i2s_intf.vhd
|
||
|
set_global_assignment -name VHDL_FILE i2sslave.vhdl
|
||
|
set_global_assignment -name QIP_FILE pll_pal.qip
|
||
|
set_global_assignment -name QIP_FILE pll_ntsc.qip
|
||
|
set_global_assignment -name QIP_FILE pll.qip
|
||
|
set_global_assignment -name VHDL_FILE sram.vhdl
|
||
|
set_global_assignment -name VHDL_FILE sync_switches.vhd
|
||
|
set_global_assignment -name VHDL_FILE zpu_rom.vhdl
|
||
|
|
||
| de1_5200/atari800core.sdc | ||
|---|---|---|
|
create_clock -period 50MHz [get_ports CLOCK_50]
|
||
|
derive_pll_clocks
|
||
|
|
||
|
set_input_delay -max -clock CLOCK_50 -1.5 [get_ports SRAM_DQ*]
|
||
|
set_input_delay -min -clock CLOCK_50 -1.5 [get_ports SRAM_DQ*]
|
||
|
|
||
| de1_5200/atari800core_de1.vhd | ||
|---|---|---|
|
---------------------------------------------------------------------------
|
||
|
-- (c) 2013 mark watson
|
||
|
-- I am happy for anyone to use this for non-commercial use.
|
||
|
-- If my vhdl files are used commercially or otherwise sold,
|
||
|
-- please contact me for explicit permission at scrameta (gmail).
|
||
|
-- This applies for source and binary form and derived works.
|
||
|
---------------------------------------------------------------------------
|
||
|
|
||
|
LIBRARY ieee;
|
||
|
USE ieee.std_logic_1164.all;
|
||
|
use ieee.numeric_std.all;
|
||
|
|
||
|
LIBRARY work;
|
||
|
|
||
|
ENTITY atari800core_de1 IS
|
||
|
GENERIC
|
||
|
(
|
||
|
TV : integer -- 1 = PAL, 0=NTSC
|
||
|
);
|
||
|
PORT
|
||
|
(
|
||
|
CLOCK_50 : IN STD_LOGIC;
|
||
|
|
||
|
AUD_BCLK : IN STD_LOGIC;
|
||
|
AUD_DACLRCK : IN STD_LOGIC;
|
||
|
I2C_SCLK : INOUT STD_LOGIC;
|
||
|
I2C_SDAT : INOUT STD_LOGIC;
|
||
|
|
||
|
PS2_CLK : IN STD_LOGIC;
|
||
|
PS2_DAT : IN STD_LOGIC;
|
||
|
|
||
|
UART_RXD : IN STD_LOGIC;
|
||
|
UART_TXD : OUT STD_LOGIC;
|
||
|
|
||
|
GPIO_0 : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0);
|
||
|
GPIO_1 : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0);
|
||
|
|
||
|
KEY : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||
|
SW : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
|
||
|
|
||
|
AUD_XCK : OUT STD_LOGIC;
|
||
|
AUD_DACDAT : OUT STD_LOGIC;
|
||
|
|
||
|
FL_OE_N : OUT STD_LOGIC;
|
||
|
FL_WE_N : OUT STD_LOGIC;
|
||
|
FL_RST_N : OUT STD_LOGIC;
|
||
|
FL_ADDR : OUT STD_LOGIC_VECTOR(21 DOWNTO 0);
|
||
|
FL_DQ : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||
|
|
||
|
SRAM_CE_N : OUT STD_LOGIC;
|
||
|
SRAM_OE_N : OUT STD_LOGIC;
|
||
|
SRAM_WE_N : OUT STD_LOGIC;
|
||
|
SRAM_LB_N : OUT STD_LOGIC;
|
||
|
SRAM_UB_N : OUT STD_LOGIC;
|
||
|
SRAM_ADDR : OUT STD_LOGIC_VECTOR(17 DOWNTO 0);
|
||
|
SRAM_DQ : INOUT STD_LOGIC_VECTOR(15 DOWNTO 0);
|
||
|
|
||
|
DRAM_BA_0 : OUT STD_LOGIC;
|
||
|
DRAM_BA_1 : OUT STD_LOGIC;
|
||
|
DRAM_CS_N : OUT STD_LOGIC;
|
||
|
DRAM_RAS_N : OUT STD_LOGIC;
|
||
|
DRAM_CAS_N : OUT STD_LOGIC;
|
||
|
DRAM_WE_N : OUT STD_LOGIC;
|
||
|
DRAM_LDQM : OUT STD_LOGIC;
|
||
|
DRAM_UDQM : OUT STD_LOGIC;
|
||
|
DRAM_CLK : OUT STD_LOGIC;
|
||
|
DRAM_CKE : OUT STD_LOGIC;
|
||
|
DRAM_ADDR : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
|
||
|
DRAM_DQ : INOUT STD_LOGIC_VECTOR(15 DOWNTO 0);
|
||
|
|
||
|
SD_CLK : OUT STD_LOGIC;
|
||
|
SD_CMD : OUT STD_LOGIC;
|
||
|
SD_THREE : OUT STD_LOGIC;
|
||
|
SD_DATA : IN STD_LOGIC;
|
||
|
|
||
|
HEX0 : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
|
||
|
HEX1 : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
|
||
|
HEX2 : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
|
||
|
HEX3 : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
|
||
|
|
||
|
LEDG : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||
|
LEDR : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
|
||
|
|
||
|
VGA_VS : OUT STD_LOGIC;
|
||
|
VGA_HS : OUT STD_LOGIC;
|
||
|
VGA_B : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||
|
VGA_G : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||
|
VGA_R : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
|
||
|
);
|
||
|
END atari800core_de1;
|
||
|
|
||
|
ARCHITECTURE vhdl OF atari800core_de1 IS
|
||
|
-- SYSTEM
|
||
|
SIGNAL CLK : STD_LOGIC;
|
||
|
SIGNAL CLK_SDRAM : STD_LOGIC;
|
||
|
SIGNAL RESET_N : STD_LOGIC;
|
||
|
signal SDRAM_RESET_N : std_logic;
|
||
|
SIGNAL PLL_LOCKED : STD_LOGIC;
|
||
|
|
||
|
-- GTIA
|
||
|
signal CONSOL_OUT : std_logic_vector(3 downto 0);
|
||
|
signal CONSOL_IN : std_logic_vector(3 downto 0);
|
||
|
signal GTIA_TRIG : std_logic_vector(3 downto 0);
|
||
|
|
||
|
-- CARTRIDGE ACCESS
|
||
|
--SIGNAL CART_RD4 : STD_LOGIC;
|
||
|
--SIGNAL CART_RD5 : STD_LOGIC;
|
||
|
--SIGNAL CART_S4_n : STD_LOGIC;
|
||
|
--SIGNAL CART_S5_n : STD_LOGIC;
|
||
|
--SIGNAL CART_CCTL_n : STD_LOGIC;
|
||
|
|
||
|
-- PBI
|
||
|
SIGNAL PBI_WRITE_DATA : std_logic_vector(31 downto 0);
|
||
|
SIGNAL PBI_WIDTH_32BIT_ACCESS : std_logic;
|
||
|
SIGNAL PBI_WIDTH_16BIT_ACCESS : std_logic;
|
||
|
SIGNAL PBI_WIDTH_8BIT_ACCESS : std_logic;
|
||
|
|
||
|
-- INTERNAL ROM/RAM
|
||
|
SIGNAL RAM_ADDR : STD_LOGIC_VECTOR(18 DOWNTO 0);
|
||
|
SIGNAL RAM_DO : STD_LOGIC_VECTOR(15 DOWNTO 0);
|
||
|
SIGNAL RAM_REQUEST : STD_LOGIC;
|
||
|
SIGNAL RAM_REQUEST_COMPLETE : STD_LOGIC;
|
||
|
SIGNAL RAM_WRITE_ENABLE : STD_LOGIC;
|
||
|
|
||
|
SIGNAL ROM_ADDR : STD_LOGIC_VECTOR(21 DOWNTO 0);
|
||
|
SIGNAL ROM_DO : STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||
|
SIGNAL ROM_REQUEST : STD_LOGIC;
|
||
|
SIGNAL ROM_REQUEST_COMPLETE : STD_LOGIC;
|
||
|
|
||
|
-- SDRAM
|
||
|
signal SDRAM_REQUEST : std_logic;
|
||
|
signal SDRAM_REQUEST_COMPLETE : std_logic;
|
||
|
signal SDRAM_READ_ENABLE : STD_LOGIC;
|
||
|
signal SDRAM_WRITE_ENABLE : std_logic;
|
||
|
signal SDRAM_ADDR : STD_LOGIC_VECTOR(22 DOWNTO 0);
|
||
|
signal SDRAM_DO : STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||
|
|
||
|
signal SDRAM_REFRESH : std_logic;
|
||
|
|
||
|
-- pokey keyboard
|
||
|
SIGNAL KEYBOARD_SCAN : std_logic_vector(5 downto 0);
|
||
|
SIGNAL KEYBOARD_RESPONSE : std_logic_vector(1 downto 0);
|
||
|
|
||
|
-- SIO
|
||
|
SIGNAL SIO_RXD : std_logic;
|
||
|
SIGNAL SIO_COMMAND : std_logic;
|
||
|
SIGNAL SIO_TXD : std_logic;
|
||
|
|
||
|
SIGNAL GPIO_SIO_RXD : std_logic;
|
||
|
|
||
|
-- VIDEO
|
||
|
signal VGA_VS_RAW : std_logic;
|
||
|
signal VGA_HS_RAW : std_logic;
|
||
|
|
||
|
-- AUDIO
|
||
|
signal AUDIO_LEFT : std_logic_vector(15 downto 0);
|
||
|
signal AUDIO_RIGHT : std_logic_vector(15 downto 0);
|
||
|
|
||
|
-- dma/virtual drive
|
||
|
signal DMA_ADDR_FETCH : std_logic_vector(23 downto 0);
|
||
|
signal DMA_WRITE_DATA : std_logic_vector(31 downto 0);
|
||
|
signal DMA_FETCH : std_logic;
|
||
|
signal DMA_32BIT_WRITE_ENABLE : std_logic;
|
||
|
signal DMA_16BIT_WRITE_ENABLE : std_logic;
|
||
|
signal DMA_8BIT_WRITE_ENABLE : std_logic;
|
||
|
signal DMA_READ_ENABLE : std_logic;
|
||
|
signal DMA_MEMORY_READY : std_logic;
|
||
|
signal DMA_MEMORY_DATA : std_logic_vector(31 downto 0);
|
||
|
|
||
|
signal ZPU_ADDR_ROM : std_logic_vector(15 downto 0);
|
||
|
signal ZPU_ROM_DATA : std_logic_vector(31 downto 0);
|
||
|
|
||
|
signal ZPU_OUT1 : std_logic_vector(31 downto 0);
|
||
|
signal ZPU_OUT2 : std_logic_vector(31 downto 0);
|
||
|
signal ZPU_OUT3 : std_logic_vector(31 downto 0);
|
||
|
signal ZPU_OUT4 : std_logic_vector(31 downto 0);
|
||
|
|
||
|
signal zpu_pokey_enable : std_logic;
|
||
|
signal zpu_sio_txd : std_logic;
|
||
|
signal zpu_sio_rxd : std_logic;
|
||
|
signal zpu_sio_command : std_logic;
|
||
|
|
||
|
SIGNAL FKEYS : std_logic_vector(11 downto 0);
|
||
|
|
||
|
-- system control from zpu
|
||
|
signal reset_atari : std_logic;
|
||
|
signal pause_atari : std_logic;
|
||
|
SIGNAL speed_6502 : std_logic_vector(5 downto 0);
|
||
|
|
||
|
-- GPIO
|
||
|
signal GPIO_0_DIR_OUT : std_logic_vector(35 downto 0);
|
||
|
signal GPIO_0_OUT : std_logic_vector(35 downto 0);
|
||
|
signal GPIO_1_DIR_OUT : std_logic_vector(35 downto 0);
|
||
|
signal GPIO_1_OUT : std_logic_vector(35 downto 0);
|
||
|
signal TRIGGERS : std_logic_vector(3 downto 0);
|
||
|
|
||
|
-- POT
|
||
|
signal POT_RESET : std_logic;
|
||
|
signal POT_IN : std_logic_vector(7 downto 0);
|
||
|
|
||
|
BEGIN
|
||
|
|
||
|
-- ANYTHING NOT CONNECTED...
|
||
|
--GPIO_0(0) <= 'Z';
|
||
|
--GPIO_0(35 downto 2) <= (others=>'Z');
|
||
|
--GPIO_1(35 downto 0) <= (others=>'Z');
|
||
|
|
||
|
FL_OE_N <= '1';
|
||
|
FL_WE_N <= '1';
|
||
|
FL_RST_N <= '1';
|
||
|
FL_ADDR <= (others=>'0');
|
||
|
|
||
|
LEDG <= (others=>'1');
|
||
|
LEDR <= (others=>'1');
|
||
|
|
||
|
-- TODO FUJI? Or Program counter or...
|
||
|
hexdecoder0 : entity work.hexdecoder
|
||
|
PORT MAP(CLK => CLK,
|
||
|
NUMBER => X"5",
|
||
|
DIGIT => HEX0);
|
||
|
|
||
|
|
||
|
hexdecoder1 : entity work.hexdecoder
|
||
|
PORT MAP(CLK => CLK,
|
||
|
NUMBER => X"2",
|
||
|
DIGIT => HEX1);
|
||
|
|
||
|
|
||
|
hexdecoder2 : entity work.hexdecoder
|
||
|
PORT MAP(CLK => CLK,
|
||
|
NUMBER => X"0",
|
||
|
DIGIT => HEX2);
|
||
|
|
||
|
|
||
|
hexdecoder3 : entity work.hexdecoder
|
||
|
PORT MAP(CLK => CLK,
|
||
|
NUMBER => X"0",
|
||
|
DIGIT => HEX3);
|
||
|
|
||
|
sram1 : entity work.sram
|
||
|
PORT MAP(WREN => RAM_WRITE_ENABLE,
|
||
|
clk => CLK,
|
||
|
reset_n => RESET_N,
|
||
|
request => RAM_REQUEST,
|
||
|
width_16bit => PBI_WIDTH_16BIT_ACCESS,
|
||
|
ADDRESS => RAM_ADDR,
|
||
|
DIN => PBI_WRITE_DATA(15 DOWNTO 0),
|
||
|
SRAM_DQ => SRAM_DQ,
|
||
|
SRAM_CE_N => SRAM_CE_N,
|
||
|
SRAM_OE_N => SRAM_OE_N,
|
||
|
SRAM_WE_N => SRAM_WE_N,
|
||
|
SRAM_LB_N => SRAM_LB_N,
|
||
|
SRAM_UB_N => SRAM_UB_N,
|
||
|
complete => RAM_REQUEST_COMPLETE,
|
||
|
DOUT => RAM_DO,
|
||
|
SRAM_ADDR => SRAM_ADDR);
|
||
|
|
||
|
sdram_adaptor : entity work.sdram_statemachine
|
||
|
GENERIC MAP(ADDRESS_WIDTH => 22,
|
||
|
AP_BIT => 10,
|
||
|
COLUMN_WIDTH => 8,
|
||
|
ROW_WIDTH => 12
|
||
|
)
|
||
|
PORT MAP(CLK_SYSTEM => CLK,
|
||
|
CLK_SDRAM => CLK_SDRAM,
|
||
|
RESET_N => RESET_N,
|
||
|
READ_EN => SDRAM_READ_ENABLE,
|
||
|
WRITE_EN => SDRAM_WRITE_ENABLE,
|
||
|
REQUEST => SDRAM_REQUEST,
|
||
|
BYTE_ACCESS => PBI_WIDTH_8BIT_ACCESS,
|
||
|
WORD_ACCESS => PBI_WIDTH_16BIT_ACCESS,
|
||
|
LONGWORD_ACCESS => PBI_WIDTH_32BIT_ACCESS,
|
||
|
REFRESH => SDRAM_REFRESH,
|
||
|
ADDRESS_IN => SDRAM_ADDR,
|
||
|
DATA_IN => PBI_WRITE_DATA(31 downto 0),
|
||
|
SDRAM_DQ => DRAM_DQ,
|
||
|
COMPLETE => SDRAM_REQUEST_COMPLETE,
|
||
|
SDRAM_BA0 => DRAM_BA_0,
|
||
|
SDRAM_BA1 => DRAM_BA_1,
|
||
|
SDRAM_CKE => DRAM_CKE,
|
||
|
SDRAM_CS_N => DRAM_CS_N,
|
||
|
SDRAM_RAS_N => DRAM_RAS_N,
|
||
|
SDRAM_CAS_N => DRAM_CAS_N,
|
||
|
SDRAM_WE_N => DRAM_WE_N,
|
||
|
SDRAM_ldqm => DRAM_LDQM,
|
||
|
SDRAM_udqm => DRAM_UDQM,
|
||
|
DATA_OUT => SDRAM_DO,
|
||
|
SDRAM_ADDR => DRAM_ADDR(11 downto 0),
|
||
|
reset_client_n => SDRAM_RESET_N
|
||
|
);
|
||
|
|
||
|
-- GTIA triggers
|
||
|
--GTIA_TRIG <= CART_RD5&"1"&JOY2_n(4)&JOY1_n(4);
|
||
|
GTIA_TRIG <= TRIGGERS(3 downto 0);
|
||
|
|
||
|
-- Internal rom/ram
|
||
|
internalromram1 : entity work.internalromram
|
||
|
GENERIC MAP
|
||
|
(
|
||
|
internal_rom => 0,
|
||
|
internal_ram => 0
|
||
|
)
|
||
|
PORT MAP (
|
||
|
clock => CLK,
|
||
|
reset_n => RESET_N,
|
||
|
|
||
|
ROM_ADDR => ROM_ADDR,
|
||
|
ROM_REQUEST_COMPLETE => ROM_REQUEST_COMPLETE,
|
||
|
ROM_REQUEST => ROM_REQUEST,
|
||
|
ROM_DATA => ROM_DO,
|
||
|
|
||
|
RAM_ADDR => RAM_ADDR,
|
||
|
RAM_WR_ENABLE => RAM_WRITE_ENABLE,
|
||
|
RAM_DATA_IN => PBI_WRITE_DATA(7 downto 0),
|
||
|
RAM_REQUEST_COMPLETE => open,
|
||
|
RAM_REQUEST => RAM_REQUEST,
|
||
|
RAM_DATA => open
|
||
|
);
|
||
|
|
||
|
--sync_switches1 : entity work.sync_switches
|
||
|
--PORT MAP(CLK => CLK,
|
||
|
-- KEY => KEY,
|
||
|
-- SW => SW,
|
||
|
-- SYNC_KEYS => SYNC_KEYS,
|
||
|
-- SYNC_SWITCHES => SYNC_SWITCHES);
|
||
|
|
||
|
gpio0_gen:
|
||
|
for I in 0 to 35 generate
|
||
|
gpio_0(I) <= gpio_0_out(I) when gpio_0_dir_out(I)='1' else 'Z';
|
||
|
end generate gpio0_gen;
|
||
|
|
||
|
gpio1_gen:
|
||
|
for I in 0 to 35 generate
|
||
|
gpio_1(I) <= gpio_1_out(I) when gpio_1_dir_out(I)='1' else 'Z';
|
||
|
end generate gpio1_gen;
|
||
|
|
||
|
gpio1 : entity work.gpio
|
||
|
PORT MAP(clk => CLK,
|
||
|
gpio_enable => '1',
|
||
|
pot_reset => pot_reset,
|
||
|
pbi_write_enable => '0',
|
||
|
cart_request => '0',
|
||
|
cart_complete => open,
|
||
|
cart_data_read => open,
|
||
|
s4_n => '0',
|
||
|
s5_n => '0',
|
||
|
cctl_n => '0',
|
||
|
cart_data_write => x"00",
|
||
|
GPIO_0_IN => GPIO_0,
|
||
|
GPIO_0_OUT => GPIO_0_OUT,
|
||
|
GPIO_0_DIR_OUT => GPIO_0_DIR_OUT,
|
||
|
GPIO_1_IN => GPIO_1,
|
||
|
GPIO_1_OUT => GPIO_1_OUT,
|
||
|
GPIO_1_DIR_OUT => GPIO_1_DIR_OUT,
|
||
|
keyboard_scan => KEYBOARD_SCAN, --5200
|
||
|
pbi_addr_out => X"0000",
|
||
|
porta_out => (others=>'0'),
|
||
|
porta_output => (others=>'0'),
|
||
|
lightpen => open,
|
||
|
rd4 => open,
|
||
|
rd5 => open,
|
||
|
keyboard_response => KEYBOARD_RESPONSE, -- 5200
|
||
|
porta_in => open,
|
||
|
pot_in => pot_in,
|
||
|
trig_in => TRIGGERS, -- 5200
|
||
|
CA2_DIR_OUT => '0',
|
||
|
CA2_OUT => '0',
|
||
|
CA2_IN => open,
|
||
|
CB2_DIR_OUT => '0',
|
||
|
CB2_OUT => '0',
|
||
|
CB2_IN => open,
|
||
|
SIO_IN => GPIO_SIO_RXD,
|
||
|
SIO_OUT => SIO_TXD,
|
||
|
CONSOL => CONSOL_OUT
|
||
|
);
|
||
|
|
||
|
--b2v_inst22 : entity work.scandoubler
|
||
|
--PORT MAP(CLK => CLK,
|
||
|
-- RESET_N => RESET_N,
|
||
|
-- VGA => VGA,
|
||
|
-- COMPOSITE_ON_HSYNC => COMPOSITE_ON_HSYNC,
|
||
|
-- colour_enable => SCANDOUBLER_SHARED_ENABLE_LOW,
|
||
|
-- doubled_enable => SCANDOUBLER_SHARED_ENABLE_HIGH,
|
||
|
-- vsync_in => SYNTHESIZED_WIRE_12,
|
||
|
-- hsync_in => SYNTHESIZED_WIRE_13,
|
||
|
-- colour_in => SYNTHESIZED_WIRE_14,
|
||
|
-- VSYNC => VGA_VS,
|
||
|
-- HSYNC => VGA_HS,
|
||
|
-- B => VGA_B,
|
||
|
-- G => VGA_G,
|
||
|
-- R => VGA_R);
|
||
|
|
||
|
|
||
|
audio_codec_config_over_i2c : entity work.i2c_loader
|
||
|
GENERIC MAP(device_address => 26,
|
||
|
log2_divider => 6,
|
||
|
num_retries => 0
|
||
|
)
|
||
|
PORT MAP(CLK => CLK,
|
||
|
nRESET => RESET_N,
|
||
|
I2C_SCL => I2C_SCLK,
|
||
|
I2C_SDA => I2C_SDAT);
|
||
|
|
||
|
audio_codec_data : entity work.i2sslave
|
||
|
PORT MAP(CLK => CLK,
|
||
|
BCLK => AUD_BCLK,
|
||
|
DACLRC => AUD_DACLRCK,
|
||
|
LEFT_IN => AUDIO_LEFT,
|
||
|
RIGHT_IN => AUDIO_RIGHT,
|
||
|
MCLK_2 => AUD_XCK,
|
||
|
DACDAT => AUD_DACDAT);
|
||
|
|
||
|
|
||
|
pll : entity work.pll
|
||
|
PORT MAP(inclk0 => CLOCK_50,
|
||
|
c0 => CLK_SDRAM,
|
||
|
c1 => CLK,
|
||
|
c2 => DRAM_CLK,
|
||
|
locked => PLL_LOCKED);
|
||
|
|
||
|
--gen_ntsc_pll : if tv=0 generate
|
||
|
--pll : entity work.pll_ntsc
|
||
|
--PORT MAP(inclk0 => CLOCK_27(0),
|
||
|
-- c0 => CLK_SDRAM,
|
||
|
-- c1 => CLK,
|
||
|
-- c2 => DRAM_CLK,
|
||
|
-- locked => PLL_LOCKED);
|
||
|
--end generate;
|
||
|
--
|
||
|
--gen_pal_pll : if tv=1 generate
|
||
|
--pll : entity work.pll_pal
|
||
|
--PORT MAP(inclk0 => CLOCK_27(0),
|
||
|
-- c0 => CLK_SDRAM,
|
||
|
-- c1 => CLK,
|
||
|
-- c2 => DRAM_CLK,
|
||
|
-- locked => PLL_LOCKED);
|
||
|
--end generate;
|
||
|
|
||
|
RESET_N <= PLL_LOCKED;
|
||
|
|
||
|
-- PS2 to pokey (just for fkeys!)
|
||
|
keyboard_map1 : entity work.ps2_to_atari800
|
||
|
PORT MAP
|
||
|
(
|
||
|
CLK => clk,
|
||
|
RESET_N => reset_n,
|
||
|
PS2_CLK => ps2_clk,
|
||
|
PS2_DAT => ps2_dat,
|
||
|
|
||
|
KEYBOARD_SCAN => KEYBOARD_SCAN,
|
||
|
KEYBOARD_RESPONSE => open,
|
||
|
|
||
|
CONSOL_START => open,
|
||
|
CONSOL_SELECT => open,
|
||
|
CONSOL_OPTION => open,
|
||
|
|
||
|
FKEYS => FKEYS
|
||
|
);
|
||
|
|
||
|
-- SIO
|
||
|
-- TODO combine
|
||
|
--SIO_RXD <= UART_RXD;
|
||
|
UART_TXD <= SIO_TXD;
|
||
|
--GPIO_0(1) <= SIO_COMMAND;
|
||
|
|
||
|
SIO_COMMAND <= 'Z'; -- no PIA...
|
||
|
zpu_sio_command <= SIO_COMMAND;
|
||
|
zpu_sio_rxd <= SIO_TXD;
|
||
|
SIO_RXD <= zpu_sio_txd and UART_RXD;
|
||
|
|
||
|
-- VIDEO
|
||
|
VGA_HS <= not(VGA_HS_RAW xor VGA_VS_RAW);
|
||
|
VGA_VS <= not(VGA_VS_RAW);
|
||
|
|
||
|
CONSOL_IN <= "1000";
|
||
|
|
||
|
atari800 : entity work.atari5200core
|
||
|
GENERIC MAP
|
||
|
(
|
||
|
cycle_length => 32,
|
||
|
video_bits => 4
|
||
|
)
|
||
|
PORT MAP
|
||
|
(
|
||
|
CLK => CLK,
|
||
|
RESET_N => RESET_N and SDRAM_RESET_N and not(reset_atari),
|
||
|
|
||
|
VIDEO_VS => VGA_VS_RAW,
|
||
|
VIDEO_HS => VGA_HS_RAW,
|
||
|
VIDEO_B => VGA_B,
|
||
|
VIDEO_G => VGA_G,
|
||
|
VIDEO_R => VGA_R,
|
||
|
|
||
|
AUDIO_L => AUDIO_LEFT,
|
||
|
AUDIO_R => AUDIO_RIGHT,
|
||
|
|
||
|
KEYBOARD_RESPONSE => KEYBOARD_RESPONSE,
|
||
|
KEYBOARD_SCAN => KEYBOARD_SCAN,
|
||
|
|
||
|
POT_IN => POT_IN,
|
||
|
POT_RESET => POT_RESET,
|
||
|
|
||
|
PBI_ADDR => open,
|
||
|
PBI_WRITE_ENABLE => open,
|
||
|
PBI_SNOOP_DATA => open,
|
||
|
PBI_WRITE_DATA => PBI_WRITE_DATA,
|
||
|
PBI_WIDTH_8bit_ACCESS => PBI_WIDTH_8bit_ACCESS,
|
||
|
PBI_WIDTH_16bit_ACCESS => PBI_WIDTH_16bit_ACCESS,
|
||
|
PBI_WIDTH_32bit_ACCESS => PBI_WIDTH_32bit_ACCESS,
|
||
|
|
||
|
PBI_ROM_DO => "11111111",
|
||
|
PBI_REQUEST => open,
|
||
|
PBI_REQUEST_COMPLETE => '1',
|
||
|
|
||
|
SIO_RXD => SIO_RXD,
|
||
|
SIO_TXD => SIO_TXD,
|
||
|
|
||
|
CONSOL_OUT => CONSOL_OUT,
|
||
|
CONSOL_IN => CONSOL_IN,
|
||
|
GTIA_TRIG => GTIA_TRIG,
|
||
|
|
||
|
SDRAM_REQUEST => SDRAM_REQUEST,
|
||
|
SDRAM_REQUEST_COMPLETE => SDRAM_REQUEST_COMPLETE,
|
||
|
SDRAM_READ_ENABLE => SDRAM_READ_ENABLE,
|
||
|
SDRAM_WRITE_ENABLE => SDRAM_WRITE_ENABLE,
|
||
|
SDRAM_ADDR => SDRAM_ADDR,
|
||
|
SDRAM_DO => SDRAM_DO,
|
||
|
|
||
|
ANTIC_REFRESH => SDRAM_REFRESH,
|
||
|
|
||
|
RAM_ADDR => RAM_ADDR,
|
||
|
RAM_DO => RAM_DO,
|
||
|
RAM_REQUEST => RAM_REQUEST,
|
||
|
RAM_REQUEST_COMPLETE => RAM_REQUEST_COMPLETE,
|
||
|
RAM_WRITE_ENABLE => RAM_WRITE_ENABLE,
|
||
|
|
||
|
ROM_ADDR => ROM_ADDR,
|
||
|
ROM_DO => ROM_DO,
|
||
|
ROM_REQUEST => ROM_REQUEST,
|
||
|
ROM_REQUEST_COMPLETE => ROM_REQUEST_COMPLETE,
|
||
|
|
||
|
DMA_FETCH => dma_fetch,
|
||
|
DMA_READ_ENABLE => dma_read_enable,
|
||
|
DMA_32BIT_WRITE_ENABLE => dma_32bit_write_enable,
|
||
|
DMA_16BIT_WRITE_ENABLE => dma_16bit_write_enable,
|
||
|
DMA_8BIT_WRITE_ENABLE => dma_8bit_write_enable,
|
||
|
DMA_ADDR => dma_addr_fetch,
|
||
|
DMA_WRITE_DATA => dma_write_data,
|
||
|
MEMORY_READY_DMA => dma_memory_ready,
|
||
|
--DMA_MEMORY_DATA => dma_memory_data,
|
||
|
PBI_SNOOP_DATA => DMA_MEMORY_DATA,
|
||
|
|
||
|
USE_SDRAM => '1', --SW(9), -- TODO
|
||
|
ROM_IN_RAM => '1',
|
||
|
HALT => pause_atari,
|
||
|
THROTTLE_COUNT_6502 => speed_6502
|
||
|
);
|
||
|
|
||
|
zpu: entity work.zpucore
|
||
|
GENERIC MAP
|
||
|
(
|
||
|
platform => 1,
|
||
|
spi_clock_div => 1 -- 28MHz/2. Max for SD cards is 25MHz...
|
||
|
)
|
||
|
PORT MAP
|
||
|
(
|
||
|
-- standard...
|
||
|
CLK => CLK,
|
||
|
RESET_N => RESET_N and sdram_reset_n,
|
||
|
|
||
|
-- dma bus master (with many waitstates...)
|
||
|
ZPU_ADDR_FETCH => dma_addr_fetch,
|
||
|
ZPU_DATA_OUT => dma_write_data,
|
||
|
ZPU_FETCH => dma_fetch,
|
||
|
ZPU_32BIT_WRITE_ENABLE => dma_32bit_write_enable,
|
||
|
ZPU_16BIT_WRITE_ENABLE => dma_16bit_write_enable,
|
||
|
ZPU_8BIT_WRITE_ENABLE => dma_8bit_write_enable,
|
||
|
ZPU_READ_ENABLE => dma_read_enable,
|
||
|
ZPU_MEMORY_READY => dma_memory_ready,
|
||
|
ZPU_MEMORY_DATA => dma_memory_data,
|
||
|
|
||
|
-- rom bus master
|
||
|
-- data on next cycle after addr
|
||
|
ZPU_ADDR_ROM => zpu_addr_rom,
|
||
|
ZPU_ROM_DATA => zpu_rom_data,
|
||
|
|
||
|
-- spi master
|
||
|
-- Too painful to bit bang spi from zpu, so we have a hardware master in here
|
||
|
ZPU_SD_DAT0 => sd_data,
|
||
|
ZPU_SD_CLK => sd_clk,
|
||
|
ZPU_SD_CMD => sd_cmd,
|
||
|
ZPU_SD_DAT3 => sd_three,
|
||
|
|
||
|
-- SIO
|
||
|
-- Ditto for speaking to Atari, we have a built in Pokey
|
||
|
ZPU_POKEY_ENABLE => zpu_pokey_enable,
|
||
|
ZPU_SIO_TXD => zpu_sio_txd,
|
||
|
ZPU_SIO_RXD => zpu_sio_rxd,
|
||
|
ZPU_SIO_COMMAND => zpu_sio_command,
|
||
|
|
||
|
-- external control
|
||
|
-- switches etc. sector DMA blah blah.
|
||
|
ZPU_IN1 => X"00000"&FKEYS,
|
||
|
ZPU_IN2 => X"00000000",
|
||
|
ZPU_IN3 => X"00000000",
|
||
|
ZPU_IN4 => X"00000000",
|
||
|
|
||
|
-- ouputs - e.g. Atari system control, halt, throttle, rom select
|
||
|
ZPU_OUT1 => zpu_out1,
|
||
|
ZPU_OUT2 => zpu_out2,
|
||
|
ZPU_OUT3 => zpu_out3,
|
||
|
ZPU_OUT4 => zpu_out4
|
||
|
);
|
||
|
|
||
|
pause_atari <= zpu_out1(0);
|
||
|
reset_atari <= zpu_out1(1);
|
||
|
speed_6502 <= zpu_out1(7 downto 2);
|
||
|
|
||
|
zpu_rom1: entity work.zpu_rom
|
||
|
port map(
|
||
|
clock => clk,
|
||
|
address => zpu_addr_rom(13 downto 2),
|
||
|
q => zpu_rom_data
|
||
|
);
|
||
|
|
||
|
enable_179_clock_div_zpu_pokey : entity work.enable_divider
|
||
|
generic map (COUNT=>32) -- cycle_length
|
||
|
port map(clk=>clk,reset_n=>reset_n,enable_in=>'1',enable_out=>zpu_pokey_enable);
|
||
|
|
||
|
END vhdl;
|
||
| de1_5200/atari5200core.qsf | ||
|---|---|---|
|
# -------------------------------------------------------------------------- #
|
||
|
#
|
||
|
# Copyright (C) 1991-2012 Altera Corporation
|
||
|
# Your use of Altera Corporation's design tools, logic functions
|
||
|
# and other software and tools, and its AMPP partner logic
|
||
|
# functions, and any output files from any of the foregoing
|
||
|
# (including device programming or simulation files), and any
|
||
|
# associated documentation or information are expressly subject
|
||
|
# to the terms and conditions of the Altera Program License
|
||
|
# Subscription Agreement, Altera MegaCore Function License
|
||
|
# Agreement, or other applicable license agreement, including,
|
||
|
# without limitation, that your use is for the sole purpose of
|
||
|
# programming logic devices manufactured by Altera and sold by
|
||
|
# Altera or its authorized distributors. Please refer to the
|
||
|
# applicable agreement for further details.
|
||
|
#
|
||
|
# -------------------------------------------------------------------------- #
|
||
|
#
|
||
|
# Quartus II 64-Bit
|
||
|
# Version 12.1 Build 243 01/31/2013 Service Pack 1 SJ Web Edition
|
||
|
# Date created = 13:58:39 April 11, 2013
|
||
|
#
|
||
|
# -------------------------------------------------------------------------- #
|
||
|
#
|
||
|
# Notes:
|
||
|
#
|
||
|
# 1) The default values for assignments are stored in the file:
|
||
|
# atari5200core_assignment_defaults.qdf
|
||
|
# If this file doesn't exist, see file:
|
||
|
# assignment_defaults.qdf
|
||
|
#
|
||
|
# 2) Altera recommends that you do not modify this file. This
|
||
|
# file is updated automatically by the Quartus II software
|
||
|
# and any changes you make may be lost or overwritten.
|
||
|
#
|
||
|
# -------------------------------------------------------------------------- #
|
||
|
|
||
|
|
||
|
set_global_assignment -name FAMILY "Cyclone II"
|
||
|
set_global_assignment -name DEVICE EP2C20F484C7
|
||
|
set_global_assignment -name TOP_LEVEL_ENTITY atari5200core_de1
|
||
|
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "12.1 SP1"
|
||
|
set_global_assignment -name PROJECT_CREATION_TIME_DATE "13:58:39 APRIL 11, 2013"
|
||
|
set_global_assignment -name LAST_QUARTUS_VERSION "12.1 SP1.33"
|
||
|
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
|
||
|
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
|
||
|
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
|
||
|
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
|
||
|
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
|
||
|
set_location_assignment PIN_A15 -to GPIO_0[4]
|
||
|
set_location_assignment PIN_B15 -to GPIO_0[5]
|
||
|
set_location_assignment PIN_A16 -to GPIO_0[6]
|
||
|
set_location_assignment PIN_B16 -to GPIO_0[7]
|
||
|
set_location_assignment PIN_A17 -to GPIO_0[8]
|
||
|
set_location_assignment PIN_B17 -to GPIO_0[9]
|
||
|
set_location_assignment PIN_A18 -to GPIO_0[10]
|
||
|
set_location_assignment PIN_B18 -to GPIO_0[11]
|
||
|
set_location_assignment PIN_A19 -to GPIO_0[12]
|
||
|
set_location_assignment PIN_B19 -to GPIO_0[13]
|
||
|
set_location_assignment PIN_A20 -to GPIO_0[14]
|
||
|
set_location_assignment PIN_B20 -to GPIO_0[15]
|
||
|
set_location_assignment PIN_C21 -to GPIO_0[16]
|
||
|
set_location_assignment PIN_C22 -to GPIO_0[17]
|
||
|
set_location_assignment PIN_D21 -to GPIO_0[18]
|
||
|
set_location_assignment PIN_D22 -to GPIO_0[19]
|
||
|
set_location_assignment PIN_E21 -to GPIO_0[20]
|
||
|
set_location_assignment PIN_E22 -to GPIO_0[21]
|
||
|
set_location_assignment PIN_F21 -to GPIO_0[22]
|
||
|
set_location_assignment PIN_F22 -to GPIO_0[23]
|
||
|
set_location_assignment PIN_G21 -to GPIO_0[24]
|
||
|
set_location_assignment PIN_G22 -to GPIO_0[25]
|
||
|
set_location_assignment PIN_J21 -to GPIO_0[26]
|
||
|
set_location_assignment PIN_J22 -to GPIO_0[27]
|
||
|
set_location_assignment PIN_K21 -to GPIO_0[28]
|
||
|
set_location_assignment PIN_K22 -to GPIO_0[29]
|
||
|
set_location_assignment PIN_J19 -to GPIO_0[30]
|
||
|
set_location_assignment PIN_J20 -to GPIO_0[31]
|
||
|
set_location_assignment PIN_J18 -to GPIO_0[32]
|
||
|
set_location_assignment PIN_K20 -to GPIO_0[33]
|
||
|
set_location_assignment PIN_L19 -to GPIO_0[34]
|
||
|
set_location_assignment PIN_L18 -to GPIO_0[35]
|
||
|
set_location_assignment PIN_H12 -to GPIO_1[0]
|
||
|
set_location_assignment PIN_H13 -to GPIO_1[1]
|
||
|
set_location_assignment PIN_H14 -to GPIO_1[2]
|
||
|
set_location_assignment PIN_G15 -to GPIO_1[3]
|
||
|
set_location_assignment PIN_E14 -to GPIO_1[4]
|
||
|
set_location_assignment PIN_E15 -to GPIO_1[5]
|
||
|
set_location_assignment PIN_F15 -to GPIO_1[6]
|
||
|
set_location_assignment PIN_G16 -to GPIO_1[7]
|
||
|
set_location_assignment PIN_F12 -to GPIO_1[8]
|
||
|
set_location_assignment PIN_F13 -to GPIO_1[9]
|
||
|
set_location_assignment PIN_C14 -to GPIO_1[10]
|
||
|
set_location_assignment PIN_D14 -to GPIO_1[11]
|
||
|
set_location_assignment PIN_D15 -to GPIO_1[12]
|
||
|
set_location_assignment PIN_D16 -to GPIO_1[13]
|
||
|
set_location_assignment PIN_C17 -to GPIO_1[14]
|
||
|
set_location_assignment PIN_C18 -to GPIO_1[15]
|
||
|
set_location_assignment PIN_C19 -to GPIO_1[16]
|
||
|
set_location_assignment PIN_C20 -to GPIO_1[17]
|
||
|
set_location_assignment PIN_D19 -to GPIO_1[18]
|
||
|
set_location_assignment PIN_D20 -to GPIO_1[19]
|
||
|
set_location_assignment PIN_E20 -to GPIO_1[20]
|
||
|
set_location_assignment PIN_F20 -to GPIO_1[21]
|
||
|
set_location_assignment PIN_E19 -to GPIO_1[22]
|
||
|
set_location_assignment PIN_E18 -to GPIO_1[23]
|
||
|
set_location_assignment PIN_G20 -to GPIO_1[24]
|
||
|
set_location_assignment PIN_G18 -to GPIO_1[25]
|
||
|
set_location_assignment PIN_G17 -to GPIO_1[26]
|
||
|
set_location_assignment PIN_H17 -to GPIO_1[27]
|
||
|
set_location_assignment PIN_J15 -to GPIO_1[28]
|
||
|
set_location_assignment PIN_H18 -to GPIO_1[29]
|
||
|
set_location_assignment PIN_N22 -to GPIO_1[30]
|
||
|
set_location_assignment PIN_N21 -to GPIO_1[31]
|
||
|
set_location_assignment PIN_P15 -to GPIO_1[32]
|
||
|
set_location_assignment PIN_N15 -to GPIO_1[33]
|
||
|
set_location_assignment PIN_P17 -to GPIO_1[34]
|
||
|
set_location_assignment PIN_P18 -to GPIO_1[35]
|
||
|
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[0]
|
||
|
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[1]
|
||
|
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[2]
|
||
|
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[3]
|
||
|
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[4]
|
||
|
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[5]
|
||
|
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[6]
|
||
|
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[7]
|
||
|
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[8]
|
||
|
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[9]
|
||
|
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[10]
|
||
|
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[11]
|
||
|
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[12]
|
||
|
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[13]
|
||
|
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[14]
|
||
|
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[15]
|
||
|
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[16]
|
||
|
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[17]
|
||
|
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[18]
|
||
|
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[19]
|
||
|
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[20]
|
||
|
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[21]
|
||
|
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[22]
|
||
|
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[23]
|
||
|
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[24]
|
||
|
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[25]
|
||
|
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to GPIO_0[26]
|
||
|
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[27]
|
||
|
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[28]
|
||
|
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[29]
|
||
|
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[30]
|
||
|
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[31]
|
||
|
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[32]
|
||
|
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[33]
|
||
|
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[34]
|
||
|
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[35]
|
||
|
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[0]
|
||
|
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[1]
|
||
|
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[2]
|
||
|
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[3]
|
||
|
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[4]
|
||
|
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[5]
|
||
|
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[6]
|
||
|
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[7]
|
||
|
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[8]
|
||
|
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[9]
|
||
|
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[10]
|
||
|
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[11]
|
||
|
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[12]
|
||
|
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[13]
|
||
|
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[14]
|
||
|
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[15]
|
||
|
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[16]
|
||
|
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[17]
|
||
|
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[18]
|
||
|
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[19]
|
||
|
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[20]
|
||
|
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[21]
|
||
|
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[22]
|
||
|
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[23]
|
||
|
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[24]
|
||
|
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[25]
|
||
|
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[26]
|
||
|
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[27]
|
||
|
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[28]
|
||
|
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[29]
|
||
|
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[30]
|
||
|
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[31]
|
||
|
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[32]
|
||
|
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[33]
|
||
|
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[34]
|
||
|
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[35]
|
||
|
set_location_assignment PIN_L22 -to SW[0]
|
||
|
set_location_assignment PIN_L21 -to SW[1]
|
||
|
set_location_assignment PIN_M22 -to SW[2]
|
||
|
set_location_assignment PIN_V12 -to SW[3]
|
||
|
set_location_assignment PIN_W12 -to SW[4]
|
||
|
set_location_assignment PIN_U12 -to SW[5]
|
||
|
set_location_assignment PIN_U11 -to SW[6]
|
||
|
set_location_assignment PIN_M2 -to SW[7]
|
||
|
set_location_assignment PIN_M1 -to SW[8]
|
||
|
set_location_assignment PIN_L2 -to SW[9]
|
||
|
set_instance_assignment -name IO_STANDARD LVTTL -to SW[0]
|
||
|
set_instance_assignment -name IO_STANDARD LVTTL -to SW[1]
|
||
|
set_instance_assignment -name IO_STANDARD LVTTL -to SW[2]
|
||
|
set_instance_assignment -name IO_STANDARD LVTTL -to SW[3]
|
||
|
set_instance_assignment -name IO_STANDARD LVTTL -to SW[4]
|
||
|
set_instance_assignment -name IO_STANDARD LVTTL -to SW[5]
|
||
|
set_instance_assignment -name IO_STANDARD LVTTL -to SW[6]
|
||
|
set_instance_assignment -name IO_STANDARD LVTTL -to SW[7]
|
||
|
set_instance_assignment -name IO_STANDARD LVTTL -to SW[8]
|
||
|
set_instance_assignment -name IO_STANDARD LVTTL -to SW[9]
|
||
|
set_location_assignment PIN_J2 -to HEX0[0]
|
||
|
set_location_assignment PIN_J1 -to HEX0[1]
|
||
|
set_location_assignment PIN_H2 -to HEX0[2]
|
||
|
set_location_assignment PIN_H1 -to HEX0[3]
|
||
|
set_location_assignment PIN_F2 -to HEX0[4]
|
||
|
set_location_assignment PIN_F1 -to HEX0[5]
|
||
|
set_location_assignment PIN_E2 -to HEX0[6]
|
||
|
set_location_assignment PIN_E1 -to HEX1[0]
|
||
|
set_location_assignment PIN_H6 -to HEX1[1]
|
||
|
set_location_assignment PIN_H5 -to HEX1[2]
|
||
|
set_location_assignment PIN_H4 -to HEX1[3]
|
||
|
set_location_assignment PIN_G3 -to HEX1[4]
|
||
|
set_location_assignment PIN_D2 -to HEX1[5]
|
||
|
set_location_assignment PIN_D1 -to HEX1[6]
|
||
|
set_location_assignment PIN_G5 -to HEX2[0]
|
||
|
set_location_assignment PIN_G6 -to HEX2[1]
|
||
|
set_location_assignment PIN_C2 -to HEX2[2]
|
||
|
set_location_assignment PIN_C1 -to HEX2[3]
|
||
|
set_location_assignment PIN_E3 -to HEX2[4]
|
||
|
set_location_assignment PIN_E4 -to HEX2[5]
|
||
|
set_location_assignment PIN_D3 -to HEX2[6]
|
||
|
set_location_assignment PIN_F4 -to HEX3[0]
|
||
|
set_location_assignment PIN_D5 -to HEX3[1]
|
||
|
set_location_assignment PIN_D6 -to HEX3[2]
|
||
|
set_location_assignment PIN_J4 -to HEX3[3]
|
||
|
set_location_assignment PIN_L8 -to HEX3[4]
|
||
|
set_location_assignment PIN_F3 -to HEX3[5]
|
||
|
set_location_assignment PIN_D4 -to HEX3[6]
|
||
|
set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[0]
|
||
|
set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[1]
|
||
|
set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[2]
|
||
|
set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[3]
|
||
|
set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[4]
|
||
|
set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[5]
|
||
|
set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[6]
|
||
|
set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[0]
|
||
|
set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[1]
|
||
|
set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[2]
|
||
|
set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[3]
|
||
|
set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[4]
|
||
|
set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[5]
|
||
|
set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[6]
|
||
|
set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[0]
|
||
|
set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[1]
|
||
|
set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[2]
|
||
|
set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[3]
|
||
|
set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[4]
|
||
|
set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[5]
|
||
|
set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[6]
|
||
|
set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[0]
|
||
|
set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[1]
|
||
|
set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[2]
|
||
|
set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[3]
|
||
|
set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[4]
|
||
|
set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[5]
|
||
|
set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[6]
|
||
Also available in: Unified diff
Make sures its named 5200 throughout