EclaireXL

set_global_assignment -name IP_TOOL_NAME "RAM: 2-PORT"

set_global_assignment -name IP_TOOL_VERSION "12.1"

set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "mist_sector_buffer.vhd"]

set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "mist_sector_buffer.cmp"]

--------------------------------------------------------------------------- -- (c) 2013 mark watson

-- I am happy for anyone to use this for non-commercial use.

-- If my vhdl files are used commercially or otherwise sold,

-- please contact me for explicit permission at scrameta (gmail).

-- This applies for source and binary form and derived works.

---------------------------------------------------------------------------

LIBRARY ieee;

USE ieee.std_logic_1164.all;

use ieee.numeric_std.all;

LIBRARY work;

ENTITY atari800core_mist IS

GENERIC

(

TV : integer; -- 1 = PAL, 0=NTSC

VIDEO : integer; -- 1 = RGB, 2 = VGA

COMPOSITE_SYNC : integer; --0 = no, 1 = yes!

SCANDOUBLE : integer -- 1 = YES, 0=NO, (+ later scanlines etc)

);

PORT

(

CLOCK_27 : IN STD_LOGIC_VECTOR(1 downto 0);

VGA_VS : OUT STD_LOGIC;

VGA_HS : OUT STD_LOGIC;

VGA_B : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);

VGA_G : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);

VGA_R : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);

AUDIO_L : OUT std_logic;

AUDIO_R : OUT std_logic;

SDRAM_BA : OUT STD_LOGIC_VECTOR(1 downto 0);

SDRAM_nCS : OUT STD_LOGIC;

SDRAM_nRAS : OUT STD_LOGIC;

SDRAM_nCAS : OUT STD_LOGIC;

SDRAM_nWE : OUT STD_LOGIC;

SDRAM_DQMH : OUT STD_LOGIC;

SDRAM_DQML : OUT STD_LOGIC;

SDRAM_CLK : OUT STD_LOGIC;

SDRAM_CKE : OUT STD_LOGIC;

SDRAM_A : OUT STD_LOGIC_VECTOR(12 DOWNTO 0);

SDRAM_DQ : INOUT STD_LOGIC_VECTOR(15 DOWNTO 0);

LED : OUT std_logic;

UART_TX : OUT STD_LOGIC;

UART_RX : IN STD_LOGIC;

SPI_DO : INOUT STD_LOGIC;

SPI_DI : IN STD_LOGIC;

SPI_SCK : IN STD_LOGIC;

SPI_SS2 : IN STD_LOGIC;

SPI_SS3 : IN STD_LOGIC;

SPI_SS4 : IN STD_LOGIC;

CONF_DATA0 : IN STD_LOGIC -- AKA SPI_SS5

);

END atari800core_mist;

ARCHITECTURE vhdl OF atari800core_mist IS

component hq_dac

port (

reset :in std_logic;

clk :in std_logic;

clk_ena : in std_logic;

pcm_in : in std_logic_vector(19 downto 0);

dac_out : out std_logic

);

end component;

component user_io

GENERIC(

STRLEN : in integer := 0

);

PORT(

-- conf_str? how to do in vhdl...

-- mist spi to firmware

SPI_CLK : in std_logic;

SPI_SS_IO : in std_logic;

SPI_MISO : out std_logic;

SPI_MOSI : in std_logic;

-- joysticks

JOYSTICK_0 : out std_logic_vector(5 downto 0);

JOYSTICK_1 : out std_logic_vector(5 downto 0);

JOYSTICK_ANALOG_0 : out std_logic_vector(15 downto 0);

JOYSTICK_ANALOG_1 : out std_logic_vector(15 downto 0); -- x axis is top 8 bits, y axis is bottom 8 bits. signed.

BUTTONS : out std_logic_vector(1 downto 0);

SWITCHES : out std_logic_vector(1 downto 0);

STATUS : out std_logic_vector(7 downto 0); -- what is this?

-- ps2

PS2_CLK : in std_logic; --12-16khz

PS2_KBD_CLK : out std_logic;

PS2_KBD_DATA : out std_logic;

-- serial (one way?)

SERIAL_DATA : in std_logic_vector(7 downto 0);

SERIAL_STROBE : in std_logic;

-- connection to sd card emulation

sd_lba : in std_logic_vector(31 downto 0);

sd_rd : in std_logic;

sd_wr : in std_logic;

sd_ack : out std_logic;

sd_conf : in std_logic;

sd_sdhc : in std_logic;

sd_dout : out std_logic_vector(7 downto 0);

sd_dout_strobe : out std_logic;

sd_din : in std_logic_vector(7 downto 0);

sd_din_strobe : out std_logic

);

end component;

signal AUDIO_L_PCM : std_logic_vector(15 downto 0);

signal AUDIO_R_PCM : std_logic_vector(15 downto 0);

signal VGA_VS_RAW : std_logic;

signal VGA_HS_RAW : std_logic;

signal RESET_n : std_logic;

signal PLL_LOCKED : std_logic;

signal CLK : std_logic;

signal CLK_SDRAM : std_logic;

signal CLK_PLL1 : std_logic; -- cascaded to get better pal clock

signal PLL1_LOCKED : std_logic;

SIGNAL PS2_CLK : std_logic;

SIGNAL PS2_DAT : std_logic;

SIGNAL CONSOL_OPTION_RAW : STD_LOGIC;

SIGNAL CONSOL_OPTION : STD_LOGIC;

SIGNAL CONSOL_SELECT_RAW : STD_LOGIC;

SIGNAL CONSOL_SELECT : STD_LOGIC;

SIGNAL CONSOL_START_RAW : STD_LOGIC;

SIGNAL CONSOL_START : STD_LOGIC;

SIGNAL FKEYS : std_logic_vector(11 downto 0);

signal capslock_pressed : std_logic;

signal capsheld_next : std_logic;

signal capsheld_reg : std_logic;

signal mist_sector_ready : std_logic;

signal mist_sector_ready_sync : std_logic;

signal mist_sector_request : std_logic;

signal mist_sector_request_sync : std_logic;

signal mist_sector_write : std_logic;

signal mist_sector_write_sync : std_logic;

signal mist_sector : std_logic_vector(25 downto 0);

signal mist_sector_sync : std_logic_vector(25 downto 0);

signal mist_addr : std_logic_vector(8 downto 0);

signal mist_do : std_logic_vector(7 downto 0);

signal mist_di : std_logic_vector(7 downto 0);

signal mist_wren : std_logic;

signal spi_miso_data : std_logic;

signal spi_miso_io : std_logic;

signal mist_buttons : std_logic_vector(1 downto 0);

signal mist_switches : std_logic_vector(1 downto 0);

signal JOY1 : STD_LOGIC_VECTOR(5 DOWNTO 0);

signal JOY2 : STD_LOGIC_VECTOR(5 DOWNTO 0);

signal JOY1X : std_logic_vector(7 downto 0);

signal JOY1Y : std_logic_vector(7 downto 0);

signal JOY2X : std_logic_vector(7 downto 0);

signal JOY2Y : std_logic_vector(7 downto 0);

signal JOY1_n : STD_LOGIC_VECTOR(4 DOWNTO 0);

signal JOY2_n : STD_LOGIC_VECTOR(4 DOWNTO 0);

signal joy_still : std_logic;

SIGNAL KEYBOARD_RESPONSE : STD_LOGIC_VECTOR(1 DOWNTO 0);

SIGNAL KEYBOARD_SCAN : STD_LOGIC_VECTOR(5 DOWNTO 0);

signal controller_select : std_logic_vector(1 downto 0);

SIGNAL PAL : std_logic;

SIGNAL COMPOSITE_ON_HSYNC : std_logic;

SIGNAL VGA : std_logic;

signal SDRAM_REQUEST : std_logic;

signal SDRAM_REQUEST_COMPLETE : std_logic;

signal SDRAM_READ_ENABLE : STD_LOGIC;

signal SDRAM_WRITE_ENABLE : std_logic;

signal SDRAM_ADDR : STD_LOGIC_VECTOR(22 DOWNTO 0);

signal SDRAM_DO : STD_LOGIC_VECTOR(31 DOWNTO 0);

signal SDRAM_DI : STD_LOGIC_VECTOR(31 DOWNTO 0);

signal SDRAM_WIDTH_8bit_ACCESS : std_logic;

signal SDRAM_WIDTH_16bit_ACCESS : std_logic;

signal SDRAM_WIDTH_32bit_ACCESS : std_logic;

signal SDRAM_REFRESH : std_logic;

signal SDRAM_RESET_N : std_logic;

-- dma/virtual drive

signal DMA_ADDR_FETCH : std_logic_vector(23 downto 0);

signal DMA_WRITE_DATA : std_logic_vector(31 downto 0);

signal DMA_FETCH : std_logic;

signal DMA_32BIT_WRITE_ENABLE : std_logic;

signal DMA_16BIT_WRITE_ENABLE : std_logic;

signal DMA_8BIT_WRITE_ENABLE : std_logic;

signal DMA_READ_ENABLE : std_logic;

signal DMA_MEMORY_READY : std_logic;

signal DMA_MEMORY_DATA : std_logic_vector(31 downto 0);

signal ZPU_ADDR_ROM : std_logic_vector(15 downto 0);

signal ZPU_ROM_DATA : std_logic_vector(31 downto 0);

signal ZPU_OUT1 : std_logic_vector(31 downto 0);

signal ZPU_OUT2 : std_logic_vector(31 downto 0);

signal ZPU_OUT3 : std_logic_vector(31 downto 0);

signal ZPU_OUT4 : std_logic_vector(31 downto 0);

signal zpu_pokey_enable : std_logic;

signal zpu_sio_txd : std_logic;

signal zpu_sio_rxd : std_logic;

signal zpu_sio_command : std_logic;

-- system control from zpu

signal ram_select : std_logic_vector(2 downto 0);

signal rom_select : std_logic_vector(5 downto 0);

signal reset_atari : std_logic;

signal pause_atari : std_logic;

SIGNAL speed_6502 : std_logic_vector(5 downto 0);

-- mist sector

signal ZPU_ROM_DATA_MUX : std_logic_vector(31 downto 0);

signal ZPU_SECTOR_DATA : std_logic_vector(31 downto 0);

signal ZPU_ROM_DO : std_logic_vector(31 downto 0);

signal ZPU_ROM_WREN : std_logic;

-- ps2

signal SLOW_PS2_CLK : std_logic; -- around 16KHz

-- scandoubler

signal half_scandouble_enable_reg : std_logic;

signal half_scandouble_enable_next : std_logic;

signal VIDEO_B : std_logic_vector(7 downto 0);

BEGIN

pal <= '1' when tv=1 else '0';

vga <= '1' when video=2 else '0';

composite_on_hsync <= '1' when composite_sync=1 else '0';

-- mist spi io

mist_spi_interface : entity work.data_io

PORT map

(

CLK =>spi_sck,

RESET_n =>reset_n,

-- SPI connection - up to upstream to make miso 'Z' on ss_io going high

SPI_CLK =>spi_sck,

SPI_SS_IO => spi_ss2,

SPI_MISO => spi_miso_data,

SPI_MOSI => spi_di,

-- Sector access request

read_request => mist_sector_request_sync,

write_request => mist_sector_write_sync,

--request => mist_sector_request_sync,

sector => mist_sector_sync(25 downto 0),

ready => mist_sector_ready,

-- DMA to RAM

ADDR => mist_addr,

DATA_OUT => mist_do,

DATA_IN => mist_di,

WR_EN => mist_wren

);

-- TODO, review if these are all needed when ZPU connected again...

select_sync : entity work.synchronizer

PORT MAP ( CLK => clk, raw => mist_sector_ready, sync=>mist_sector_ready_sync);

select_sync2 : entity work.synchronizer

PORT MAP ( CLK => spi_sck, raw => mist_sector_request, sync=>mist_sector_request_sync);

select_sync3 : entity work.synchronizer

PORT MAP ( CLK => spi_sck, raw => mist_sector_write, sync=>mist_sector_write_sync);

sector_sync0 : entity work.synchronizer

PORT MAP ( CLK => spi_sck, raw => mist_sector(0), sync=>mist_sector_sync(0));

sector_sync1 : entity work.synchronizer

PORT MAP ( CLK => spi_sck, raw => mist_sector(1), sync=>mist_sector_sync(1));

sector_sync2 : entity work.synchronizer

PORT MAP ( CLK => spi_sck, raw => mist_sector(2), sync=>mist_sector_sync(2));

sector_sync3 : entity work.synchronizer

PORT MAP ( CLK => spi_sck, raw => mist_sector(3), sync=>mist_sector_sync(3));

sector_sync4 : entity work.synchronizer

PORT MAP ( CLK => spi_sck, raw => mist_sector(4), sync=>mist_sector_sync(4));

sector_sync5 : entity work.synchronizer

PORT MAP ( CLK => spi_sck, raw => mist_sector(5), sync=>mist_sector_sync(5));

sector_sync6 : entity work.synchronizer

PORT MAP ( CLK => spi_sck, raw => mist_sector(6), sync=>mist_sector_sync(6));

sector_sync7 : entity work.synchronizer

PORT MAP ( CLK => spi_sck, raw => mist_sector(7), sync=>mist_sector_sync(7));

sector_sync8 : entity work.synchronizer

PORT MAP ( CLK => spi_sck, raw => mist_sector(8), sync=>mist_sector_sync(8));

sector_sync9 : entity work.synchronizer

PORT MAP ( CLK => spi_sck, raw => mist_sector(9), sync=>mist_sector_sync(9));

sector_sync10 : entity work.synchronizer

PORT MAP ( CLK => spi_sck, raw => mist_sector(10), sync=>mist_sector_sync(10));

sector_sync11 : entity work.synchronizer

PORT MAP ( CLK => spi_sck, raw => mist_sector(11), sync=>mist_sector_sync(11));

sector_sync12 : entity work.synchronizer

PORT MAP ( CLK => spi_sck, raw => mist_sector(12), sync=>mist_sector_sync(12));

sector_sync13 : entity work.synchronizer

PORT MAP ( CLK => spi_sck, raw => mist_sector(13), sync=>mist_sector_sync(13));

sector_sync14 : entity work.synchronizer

PORT MAP ( CLK => spi_sck, raw => mist_sector(14), sync=>mist_sector_sync(14));

sector_sync15 : entity work.synchronizer

PORT MAP ( CLK => spi_sck, raw => mist_sector(15), sync=>mist_sector_sync(15));

sector_sync16 : entity work.synchronizer

PORT MAP ( CLK => spi_sck, raw => mist_sector(16), sync=>mist_sector_sync(16));

sector_sync17 : entity work.synchronizer

PORT MAP ( CLK => spi_sck, raw => mist_sector(17), sync=>mist_sector_sync(17));

sector_sync18 : entity work.synchronizer

PORT MAP ( CLK => spi_sck, raw => mist_sector(18), sync=>mist_sector_sync(18));

sector_sync19 : entity work.synchronizer

PORT MAP ( CLK => spi_sck, raw => mist_sector(19), sync=>mist_sector_sync(19));

sector_sync20 : entity work.synchronizer

PORT MAP ( CLK => spi_sck, raw => mist_sector(20), sync=>mist_sector_sync(20));

sector_sync21 : entity work.synchronizer

PORT MAP ( CLK => spi_sck, raw => mist_sector(21), sync=>mist_sector_sync(21));

sector_sync22 : entity work.synchronizer

PORT MAP ( CLK => spi_sck, raw => mist_sector(22), sync=>mist_sector_sync(22));

sector_sync23 : entity work.synchronizer

PORT MAP ( CLK => spi_sck, raw => mist_sector(23), sync=>mist_sector_sync(23));

sector_sync24 : entity work.synchronizer

PORT MAP ( CLK => spi_sck, raw => mist_sector(24), sync=>mist_sector_sync(24));

sector_sync25 : entity work.synchronizer

PORT MAP ( CLK => spi_sck, raw => mist_sector(25), sync=>mist_sector_sync(25));

spi_do <= spi_miso_io when CONF_DATA0 ='0' else spi_miso_data when spi_SS2='0' else 'Z';

mist_sector_buffer1 : entity work.mist_sector_buffer

PORT map

(

address_a => mist_addr,

address_b => zpu_addr_rom(8 downto 2),

clock_a => spi_sck,

clock_b => clk,

data_a => mist_do,

data_b => dma_write_data(7 downto 0)&dma_write_data(15 downto 8)&dma_write_data(23 downto 16)&dma_write_data(31 downto 24),

wren_a => mist_wren,

wren_b => zpu_rom_wren,

q_a => mist_di,

q_b => zpu_sector_data

);

my_user_io : user_io

PORT map(

SPI_CLK => SPI_SCK,

SPI_SS_IO => CONF_DATA0,

SPI_MISO => SPI_miso_io,

SPI_MOSI => SPI_DI,

JOYSTICK_0 => joy2,

JOYSTICK_1 => joy1,

JOYSTICK_ANALOG_0(15 downto 8) => joy2x,

JOYSTICK_ANALOG_0(7 downto 0) => joy2y,

JOYSTICK_ANALOG_1(15 downto 8) => joy1x,

JOYSTICK_ANALOG_1(7 downto 0) => joy1y,

BUTTONS => mist_buttons,

SWITCHES => mist_switches,

PS2_CLK => SLOW_PS2_CLK,

PS2_KBD_CLK => ps2_clk,

PS2_KBD_DATA => ps2_dat,

STATUS => open,

SERIAL_DATA => (others=>'0'),

SERIAL_STROBE => '0',

sd_lba => (others=>'0'),

sd_rd => '0',

sd_wr => '0',

sd_conf => '0',

sd_sdhc => '0',

sd_din => (others=>'0')

);

joy1_n <= not(joy1(5)&joy1(3 downto 0));

joy2_n <= not(joy2(5)&joy2(3 downto 0));

-- PS2 to pokey

keyboard_map1 : entity work.ps2_to_atari5200

PORT MAP

(

CLK => clk,

RESET_N => reset_n,

PS2_CLK => ps2_clk,

PS2_DAT => ps2_dat,

FIRE2 => '0'&'0'&joy2(4)&joy1(4),

CONTROLLER_SELECT => CONTROLLER_SELECT, -- selected stick keyboard/shift button

KEYBOARD_SCAN => KEYBOARD_SCAN,

KEYBOARD_RESPONSE => KEYBOARD_RESPONSE,

FKEYS => FKEYS

);

--keyboard_map1 : entity work.ps2_to_atari800

-- PORT MAP

-- (

-- CLK => clk,

-- RESET_N => reset_n,

-- PS2_CLK => ps2_clk,

-- PS2_DAT => ps2_dat,

--

-- KEYBOARD_SCAN => KEYBOARD_SCAN,

-- KEYBOARD_RESPONSE => KEYBOARD_RESPONSE,

--

-- CONSOL_START => CONSOL_START_RAW,

-- CONSOL_SELECT => CONSOL_SELECT_RAW,

-- CONSOL_OPTION => CONSOL_OPTION_RAW,

--

-- FKEYS => FKEYS

-- );

CONSOL_START <= CONSOL_START_RAW or (mist_buttons(1) and not(joy1_n(4)));

joy_still <= joy1_n(3) and joy1_n(2) and joy1_n(1) and joy1_n(0);

CONSOL_SELECT <= CONSOL_SELECT_RAW or (mist_buttons(1) and joy1_n(4) and not(joy_still));

CONSOL_OPTION <= CONSOL_OPTION_RAW or (mist_buttons(1) and joy1_n(4) and joy_still);

dac_left : hq_dac

port map

(

reset => not(reset_n),

clk => clk,

clk_ena => '1',

pcm_in => AUDIO_L_PCM&"0000",

dac_out => audio_l

);

dac_right : hq_dac

port map

(

reset => not(reset_n),

clk => clk,

clk_ena => '1',

pcm_in => AUDIO_R_PCM&"0000",

dac_out => audio_r

);

gen_ntsc_pll : if tv=0 generate

mist_pll : entity work.pll_ntsc

PORT MAP(inclk0 => CLOCK_27(0),

c0 => CLK_SDRAM,

c1 => CLK,

c2 => SDRAM_CLK,

c3 => SLOW_PS2_CLK,

locked => PLL_LOCKED);

end generate;

gen_pal_pll : if tv=1 generate

mist_pll : entity work.pll_pal_pre

PORT MAP(inclk0 => CLOCK_27(0),

c0 => CLK_PLL1,

locked => PLL1_LOCKED);

mist_pll2 : entity work.pll_pal_post

PORT MAP(inclk0 => CLK_PLL1,

c0 => CLK_SDRAM,

c1 => CLK,

c2 => SDRAM_CLK,

c3 => SLOW_PS2_CLK,

areset => not(PLL1_LOCKED),

locked => PLL_LOCKED);

end generate;

reset_n <= PLL_LOCKED;

atari5200_test : entity work.atari5200core_simplesdram

GENERIC MAP

(

cycle_length => 32,

--internal_rom => 4, --5200 rom...

internal_rom => 0, --5200 rom...

internal_ram => 0, -- only 1 option for 5200...

video_bits => 8,

palette => 0

)

PORT MAP

(

CLK => CLK,

RESET_N => RESET_N and SDRAM_RESET_N and not(reset_atari),

VIDEO_VS => VGA_VS_RAW,

VIDEO_HS => VGA_HS_RAW,

VIDEO_B => VIDEO_B,

VIDEO_G => open,

VIDEO_R => open,

AUDIO_L => AUDIO_L_PCM,

AUDIO_R => AUDIO_R_PCM,

SDRAM_REQUEST => SDRAM_REQUEST,

SDRAM_REQUEST_COMPLETE => SDRAM_REQUEST_COMPLETE,

SDRAM_READ_ENABLE => SDRAM_READ_ENABLE,

SDRAM_WRITE_ENABLE => SDRAM_WRITE_ENABLE,

SDRAM_ADDR => SDRAM_ADDR,

SDRAM_DO => SDRAM_DO,

SDRAM_DI => SDRAM_DI,

SDRAM_32BIT_WRITE_ENABLE => SDRAM_WIDTH_32bit_ACCESS,

SDRAM_16BIT_WRITE_ENABLE => SDRAM_WIDTH_16bit_ACCESS,

SDRAM_8BIT_WRITE_ENABLE => SDRAM_WIDTH_8bit_ACCESS,

SDRAM_REFRESH => SDRAM_REFRESH,

DMA_FETCH => dma_fetch,

DMA_READ_ENABLE => dma_read_enable,

DMA_32BIT_WRITE_ENABLE => dma_32bit_write_enable,

DMA_16BIT_WRITE_ENABLE => dma_16bit_write_enable,

DMA_8BIT_WRITE_ENABLE => dma_8bit_write_enable,

DMA_ADDR => dma_addr_fetch,

DMA_WRITE_DATA => dma_write_data,

MEMORY_READY_DMA => dma_memory_ready,

DMA_MEMORY_DATA => dma_memory_data,

THROTTLE_COUNT_6502 => speed_6502,

HALT => pause_atari,

-- JOYSTICK

JOY1_X => signed(joy1x),

JOY1_Y => signed(joy1y),

JOY1_BUTTON => joy1_n(4),

JOY2_X => signed(joy2x),

JOY2_Y => signed(joy2y),

JOY2_BUTTON => joy2_n(4),

-- Pokey keyboard matrix

-- Standard component available to connect this to PS2

KEYBOARD_RESPONSE => KEYBOARD_RESPONSE,

KEYBOARD_SCAN => KEYBOARD_SCAN,

CONTROLLER_SELECT => CONTROLLER_SELECT

);

--atarixl_simple_sdram1 : entity work.atari800core_simple_sdram

-- GENERIC MAP

-- (

-- cycle_length => 32,

-- internal_rom => 0,

-- internal_ram => 0,

-- video_bits => 8,

-- palette => 0

-- )

-- PORT MAP

-- (

-- CLK => CLK,

-- RESET_N => RESET_N and SDRAM_RESET_N and not(reset_atari),

--

-- VIDEO_VS => VGA_VS_RAW,

-- VIDEO_HS => VGA_HS_RAW,

-- VIDEO_B => VIDEO_B,

-- VIDEO_G => open,

-- VIDEO_R => open,

--

-- AUDIO_L => AUDIO_L_PCM,

-- AUDIO_R => AUDIO_R_PCM,

--

-- JOY1_n => JOY1_n(4)&JOY1_n(0)&JOY1_n(1)&JOY1_n(2)&JOY1_n(3),

-- JOY2_n => JOY2_n(4)&JOY2_n(0)&JOY2_n(1)&JOY2_n(2)&JOY2_n(3),

--

-- KEYBOARD_RESPONSE => KEYBOARD_RESPONSE,

-- KEYBOARD_SCAN => KEYBOARD_SCAN,

--

-- SIO_COMMAND => zpu_sio_command,

-- SIO_RXD => zpu_sio_txd,

-- SIO_TXD => zpu_sio_rxd,

--

-- CONSOL_OPTION => CONSOL_OPTION,

-- CONSOL_SELECT => CONSOL_SELECT,

-- CONSOL_START => CONSOL_START,

--

-- SDRAM_REQUEST => SDRAM_REQUEST,

-- SDRAM_REQUEST_COMPLETE => SDRAM_REQUEST_COMPLETE,

-- SDRAM_READ_ENABLE => SDRAM_READ_ENABLE,

-- SDRAM_WRITE_ENABLE => SDRAM_WRITE_ENABLE,

-- SDRAM_ADDR => SDRAM_ADDR,

-- SDRAM_DO => SDRAM_DO,

-- SDRAM_DI => SDRAM_DI,

-- SDRAM_32BIT_WRITE_ENABLE => SDRAM_WIDTH_32bit_ACCESS,

-- SDRAM_16BIT_WRITE_ENABLE => SDRAM_WIDTH_16bit_ACCESS,

-- SDRAM_8BIT_WRITE_ENABLE => SDRAM_WIDTH_8bit_ACCESS,

-- SDRAM_REFRESH => SDRAM_REFRESH,

--

-- DMA_FETCH => dma_fetch,

-- DMA_READ_ENABLE => dma_read_enable,

-- DMA_32BIT_WRITE_ENABLE => dma_32bit_write_enable,

-- DMA_16BIT_WRITE_ENABLE => dma_16bit_write_enable,

-- DMA_8BIT_WRITE_ENABLE => dma_8bit_write_enable,

-- DMA_ADDR => dma_addr_fetch,

-- DMA_WRITE_DATA => dma_write_data,

-- MEMORY_READY_DMA => dma_memory_ready,

-- DMA_MEMORY_DATA => dma_memory_data,

--

-- RAM_SELECT => ram_select,

-- ROM_SELECT => rom_select,

-- PAL => PAL,

-- HALT => pause_atari,

-- THROTTLE_COUNT_6502 => speed_6502

-- );

sdram_adaptor : entity work.sdram_statemachine

GENERIC MAP(ADDRESS_WIDTH => 22,

AP_BIT => 10,

COLUMN_WIDTH => 8,

ROW_WIDTH => 12

)

PORT MAP(CLK_SYSTEM => CLK,

CLK_SDRAM => CLK_SDRAM,

RESET_N => RESET_N,

READ_EN => SDRAM_READ_ENABLE,

WRITE_EN => SDRAM_WRITE_ENABLE,

REQUEST => SDRAM_REQUEST,

BYTE_ACCESS => SDRAM_WIDTH_8BIT_ACCESS,

WORD_ACCESS => SDRAM_WIDTH_16BIT_ACCESS,

LONGWORD_ACCESS => SDRAM_WIDTH_32BIT_ACCESS,

REFRESH => SDRAM_REFRESH,

ADDRESS_IN => SDRAM_ADDR,

DATA_IN => SDRAM_DI,

SDRAM_DQ => SDRAM_DQ,

COMPLETE => SDRAM_REQUEST_COMPLETE,

SDRAM_BA0 => SDRAM_BA(0),

SDRAM_BA1 => SDRAM_BA(1),

SDRAM_CKE => SDRAM_CKE,

SDRAM_CS_N => SDRAM_nCS,

SDRAM_RAS_N => SDRAM_nRAS,

SDRAM_CAS_N => SDRAM_nCAS,

SDRAM_WE_N => SDRAM_nWE,

SDRAM_ldqm => SDRAM_DQML,

SDRAM_udqm => SDRAM_DQMH,

DATA_OUT => SDRAM_DO,

SDRAM_ADDR => SDRAM_A(11 downto 0),

reset_client_n => SDRAM_RESET_N

);

SDRAM_A(12) <= '0';

--SDRAM_REFRESH <= '0'; -- TODO

-- Until SDRAM enabled... TODO

--SDRAM_nCS <= '1';

--SDRAM_DQ <= (others=>'Z');

--SDRAM_CKE <= '1';

LED <= zpu_sio_rxd;

--VGA_HS <= not(VGA_HS_RAW xor VGA_VS_RAW);

--VGA_VS <= not(VGA_VS_RAW);

process(clk,RESET_N,SDRAM_RESET_N,reset_atari)

begin

if ((RESET_N and SDRAM_RESET_N and not(reset_atari))='0') then

half_scandouble_enable_reg <= '0';

elsif (clk'event and clk='1') then

half_scandouble_enable_reg <= half_scandouble_enable_next;

end if;

end process;

half_scandouble_enable_next <= not(half_scandouble_enable_reg);

scandoubler1: entity work.scandoubler

GENERIC MAP

(

video_bits=>6

)

PORT MAP

(

CLK => CLK,

RESET_N => RESET_N and SDRAM_RESET_N and not(reset_atari),

VGA => vga,

COMPOSITE_ON_HSYNC => composite_on_hsync,

colour_enable => half_scandouble_enable_reg,

doubled_enable => '1',

scanlines_on => mist_switches(1),

-- GTIA interface

colour_in => VIDEO_B,

vsync_in => VGA_VS_RAW,

hsync_in => VGA_HS_RAW,

-- TO TV...

R => VGA_R,

G => VGA_G,

B => VGA_B,

VSYNC => VGA_VS,

HSYNC => VGA_HS

);

zpu: entity work.zpucore

GENERIC MAP

(

platform => 1,

spi_clock_div => 1 -- 28MHz/2. Max for SD cards is 25MHz...

)

PORT MAP

(

-- standard...

CLK => CLK,

RESET_N => RESET_N and sdram_reset_n,

-- dma bus master (with many waitstates...)

ZPU_ADDR_FETCH => dma_addr_fetch,

ZPU_DATA_OUT => dma_write_data,

ZPU_FETCH => dma_fetch,

ZPU_32BIT_WRITE_ENABLE => dma_32bit_write_enable,

ZPU_16BIT_WRITE_ENABLE => dma_16bit_write_enable,

ZPU_8BIT_WRITE_ENABLE => dma_8bit_write_enable,

ZPU_READ_ENABLE => dma_read_enable,

ZPU_MEMORY_READY => dma_memory_ready,

ZPU_MEMORY_DATA => dma_memory_data,

-- rom bus master

-- data on next cycle after addr

ZPU_ADDR_ROM => zpu_addr_rom,

ZPU_ROM_DATA => zpu_rom_data_mux,

ZPU_ROM_WREN => zpu_rom_wren, -- special for mist...

-- spi master

-- not used for mist...

ZPU_SD_DAT0 => '0',

ZPU_SD_CLK => open,

ZPU_SD_CMD => open,

ZPU_SD_DAT3 => open,

-- SIO

-- Ditto for speaking to Atari, we have a built in Pokey

ZPU_POKEY_ENABLE => zpu_pokey_enable,

ZPU_SIO_TXD => zpu_sio_txd,

ZPU_SIO_RXD => zpu_sio_rxd,

ZPU_SIO_COMMAND => zpu_sio_command,

-- external control

-- switches etc. sector DMA blah blah.

ZPU_IN1 => X"00000"&(FKEYS(11) or (mist_buttons(0) and not(joy1_n(4))))&(FKEYS(10) or (mist_buttons(0) and joy1_n(4) and joy_still))&(FKEYS(9) or (mist_buttons(0) and joy1_n(4) and not(joy_still)))&FKEYS(8 downto 0),

ZPU_IN2 => X"00000000",

ZPU_IN3 => X"00000000",

ZPU_IN4 => X"000000"&"0000000"&mist_sector_ready_sync,

-- ouputs - e.g. Atari system control, halt, throttle, rom select

ZPU_OUT1 => zpu_out1,

ZPU_OUT2 => zpu_out2,

ZPU_OUT3 => zpu_out3,

ZPU_OUT4 => zpu_out4

);

mist_sector <= zpu_out4(25 downto 0);

mist_sector_request <= zpu_out4(26);

mist_sector_write <= zpu_out4(27);

pause_atari <= zpu_out1(0);

reset_atari <= zpu_out1(1);

speed_6502 <= zpu_out1(7 downto 2);

ram_select <= zpu_out1(10 downto 8);

rom_select <= zpu_out1(16 downto 11);

zpu_rom1: entity work.zpu_rom

port map(

clock => clk,

address => zpu_addr_rom(13 downto 2),

q => zpu_rom_data

);

process(zpu_addr_rom, zpu_rom_data, zpu_sector_data)

begin

zpu_rom_data_mux <= zpu_rom_data;

if (zpu_addr_rom(15 downto 14) = "01") then

zpu_rom_data_mux <= zpu_sector_data(7 downto 0)&zpu_sector_data(15 downto 8)&zpu_sector_data(23 downto 16)&zpu_sector_data(31 downto 24);

end if;

end process;

enable_179_clock_div_zpu_pokey : entity work.enable_divider

generic map (COUNT=>32) -- cycle_length

port map(clk=>clk,reset_n=>reset_n,enable_in=>'1',enable_out=>zpu_pokey_enable);

END vhdl;

<?xml version="1.0" encoding="UTF-8" ?>

<!DOCTYPE pinplan>

<pinplan intended_family="Cyclone III" variation_name="pll_pal_pre" megafunction_name="ALTPLL" specifies="all_ports">

<global>

<pin name="inclk0" direction="input" scope="external" source="clock" />

<pin name="c0" direction="output" scope="external" source="clock" />

<pin name="locked" direction="output" scope="external" />

</global>

</pinplan>

set_global_assignment -name IP_TOOL_NAME "ALTPLL"

set_global_assignment -name IP_TOOL_VERSION "13.0"

set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll_pal_post.vhd"]

set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_pal_post.cmp"]

set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_pal_post.ppf"]

<?xml version="1.0" encoding="UTF-8"?>

<wave_config>

<wave_state>

</wave_state>

<db_ref_list>

<db_ref path="data_io.wdb" id="1" type="auto">

<top_modules>

<top_module name="data_io_tb" />

<top_module name="numeric_std" />

<top_module name="std_logic_1164" />

<top_module name="std_logic_arith" />

<top_module name="std_logic_textio" />

<top_module name="std_logic_unsigned" />

<top_module name="textio" />

</top_modules>

</db_ref>

</db_ref_list>

<WVObjectSize size="19" />

<wvobject fp_name="/data_io_tb/reset_n" type="logic" db_ref_id="1">

<obj_property name="ElementShortName">reset_n</obj_property>

<obj_property name="ObjectShortName">reset_n</obj_property>

</wvobject>

<wvobject fp_name="/data_io_tb/request" type="logic" db_ref_id="1">

<obj_property name="ElementShortName">request</obj_property>

<obj_property name="ObjectShortName">request</obj_property>

</wvobject>

<wvobject fp_name="/data_io_tb/write" type="logic" db_ref_id="1">

<obj_property name="ElementShortName">write</obj_property>

<obj_property name="ObjectShortName">write</obj_property>

</wvobject>

<wvobject fp_name="/data_io_tb/ready" type="logic" db_ref_id="1">

<obj_property name="ElementShortName">ready</obj_property>

<obj_property name="ObjectShortName">ready</obj_property>

</wvobject>

<wvobject fp_name="/data_io_tb/spi_miso" type="logic" db_ref_id="1">

<obj_property name="ElementShortName">spi_miso</obj_property>

<obj_property name="ObjectShortName">spi_miso</obj_property>

</wvobject>

<wvobject fp_name="/data_io_tb/spi_mosi" type="logic" db_ref_id="1">

<obj_property name="ElementShortName">spi_mosi</obj_property>

<obj_property name="ObjectShortName">spi_mosi</obj_property>

</wvobject>

<wvobject fp_name="/data_io_tb/spi_clk" type="logic" db_ref_id="1">

<obj_property name="ElementShortName">spi_clk</obj_property>

<obj_property name="ObjectShortName">spi_clk</obj_property>

</wvobject>

<wvobject fp_name="/data_io_tb/spi_tx_data" type="array" db_ref_id="1">

<obj_property name="ElementShortName">spi_tx_data[7:0]</obj_property>

<obj_property name="ObjectShortName">spi_tx_data[7:0]</obj_property>

<obj_property name="Radix">HEXRADIX</obj_property>

</wvobject>

<wvobject fp_name="/data_io_tb/spi_rx_data" type="array" db_ref_id="1">

<obj_property name="ElementShortName">spi_rx_data[7:0]</obj_property>

<obj_property name="ObjectShortName">spi_rx_data[7:0]</obj_property>

<obj_property name="Radix">HEXRADIX</obj_property>

</wvobject>

<wvobject fp_name="/data_io_tb/spi_busy" type="logic" db_ref_id="1">

<obj_property name="ElementShortName">spi_busy</obj_property>

<obj_property name="ObjectShortName">spi_busy</obj_property>

</wvobject>

<wvobject fp_name="/data_io_tb/spi_enable" type="logic" db_ref_id="1">

<obj_property name="ElementShortName">spi_enable</obj_property>

<obj_property name="ObjectShortName">spi_enable</obj_property>

</wvobject>

<wvobject fp_name="/data_io_tb/data_io/cmd_reg" type="array" db_ref_id="1">

<obj_property name="ElementShortName">cmd_reg[7:0]</obj_property>

<obj_property name="ObjectShortName">cmd_reg[7:0]</obj_property>

<obj_property name="Radix">HEXRADIX</obj_property>

</wvobject>

<wvobject fp_name="/data_io_tb/data_io/cnt_reg" type="array" db_ref_id="1">

<obj_property name="ElementShortName">cnt_reg[15:0]</obj_property>

<obj_property name="ObjectShortName">cnt_reg[15:0]</obj_property>

<obj_property name="Radix">HEXRADIX</obj_property>

</wvobject>

<wvobject fp_name="/data_io_tb/data_io/sbuf_reg" type="array" db_ref_id="1">

<obj_property name="ElementShortName">sbuf_reg[6:0]</obj_property>

<obj_property name="ObjectShortName">sbuf_reg[6:0]</obj_property>

<obj_property name="Radix">HEXRADIX</obj_property>

</wvobject>

<wvobject fp_name="/data_io_tb/addr" type="array" db_ref_id="1">

<obj_property name="ElementShortName">addr[8:0]</obj_property>

<obj_property name="ObjectShortName">addr[8:0]</obj_property>

<obj_property name="Radix">HEXRADIX</obj_property>

</wvobject>

<wvobject fp_name="/data_io_tb/data_out" type="array" db_ref_id="1">

<obj_property name="ElementShortName">data_out[7:0]</obj_property>

<obj_property name="ObjectShortName">data_out[7:0]</obj_property>

<obj_property name="Radix">HEXRADIX</obj_property>

</wvobject>

<wvobject fp_name="/data_io_tb/data_in" type="array" db_ref_id="1">

<obj_property name="ElementShortName">data_in[7:0]</obj_property>

<obj_property name="ObjectShortName">data_in[7:0]</obj_property>

<obj_property name="Radix">HEXRADIX</obj_property>

</wvobject>

<wvobject fp_name="/data_io_tb/wr_en" type="logic" db_ref_id="1">

<obj_property name="ElementShortName">wr_en</obj_property>

<obj_property name="ObjectShortName">wr_en</obj_property>

</wvobject>

<wvobject fp_name="/data_io_tb/spi_ss_io" type="array" db_ref_id="1">

<obj_property name="ElementShortName">spi_ss_io[1:0]</obj_property>

<obj_property name="ObjectShortName">spi_ss_io[1:0]</obj_property>

</wvobject>

</wave_config>

# -------------------------------------------------------------------------- #

#

# Copyright (C) 1991-2012 Altera Corporation

# Your use of Altera Corporation's design tools, logic functions

# and other software and tools, and its AMPP partner logic

# functions, and any output files from any of the foregoing

# (including device programming or simulation files), and any

# associated documentation or information are expressly subject

# to the terms and conditions of the Altera Program License

# Subscription Agreement, Altera MegaCore Function License

# Agreement, or other applicable license agreement, including,

# without limitation, that your use is for the sole purpose of

# programming logic devices manufactured by Altera and sold by

# Altera or its authorized distributors. Please refer to the

# applicable agreement for further details.

#

# -------------------------------------------------------------------------- #

#

# Quartus II 64-Bit

# Version 12.1 Build 243 01/31/2013 Service Pack 1 SJ Web Edition

# Date created = 13:58:38 April 11, 2013

#

# -------------------------------------------------------------------------- #

QUARTUS_VERSION = "12.1"

DATE = "13:58:38 April 11, 2013"

# Revisions

PROJECT_REVISION = "atari800core"

--Copyright (C) 1991-2013 Altera Corporation

--Your use of Altera Corporation's design tools, logic functions

--and other software and tools, and its AMPP partner logic

--functions, and any output files from any of the foregoing

--(including device programming or simulation files), and any

--associated documentation or information are expressly subject

--to the terms and conditions of the Altera Program License

--Subscription Agreement, Altera MegaCore Function License

--Agreement, or other applicable license agreement, including,

--without limitation, that your use is for the sole purpose of

--programming logic devices manufactured by Altera and sold by

--Altera or its authorized distributors. Please refer to the

--applicable agreement for further details.

component pll_ntsc

PORT

(

inclk0 : IN STD_LOGIC := '0';

c0 : OUT STD_LOGIC ;

c1 : OUT STD_LOGIC ;

c2 : OUT STD_LOGIC ;

c3 : OUT STD_LOGIC ;

locked : OUT STD_LOGIC

);

end component;

#onerror {resume}

# GAME

#=====================

#run 18871970 ns

#isim force add {/replay_tb/uut/tpp2/cpu/dd_s} 11111111 -radix bin -cancel 250 ns

#run 200 ms

-- megafunction wizard: %RAM: 2-PORT%

-- GENERATION: STANDARD

-- VERSION: WM1.0

-- MODULE: altsyncram

-- ============================================================

-- File Name: mist_sector_buffer.vhd

-- Megafunction Name(s):

-- altsyncram

--

-- Simulation Library Files(s):

-- altera_mf

-- ============================================================

-- ************************************************************

-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!

--

-- 12.1 Build 243 01/31/2013 SP 1.33 SJ Web Edition

-- ************************************************************

--Copyright (C) 1991-2012 Altera Corporation

--Your use of Altera Corporation's design tools, logic functions

--and other software and tools, and its AMPP partner logic

--functions, and any output files from any of the foregoing

--(including device programming or simulation files), and any

--associated documentation or information are expressly subject

--to the terms and conditions of the Altera Program License

--Subscription Agreement, Altera MegaCore Function License

--Agreement, or other applicable license agreement, including,

--without limitation, that your use is for the sole purpose of

--programming logic devices manufactured by Altera and sold by

--Altera or its authorized distributors. Please refer to the

--applicable agreement for further details.

LIBRARY ieee;

USE ieee.std_logic_1164.all;

LIBRARY altera_mf;

USE altera_mf.all;

ENTITY mist_sector_buffer IS

PORT

(

address_a : IN STD_LOGIC_VECTOR (8 DOWNTO 0);

address_b : IN STD_LOGIC_VECTOR (6 DOWNTO 0);

clock_a : IN STD_LOGIC := '1';

clock_b : IN STD_LOGIC ;

data_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0);

data_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);

wren_a : IN STD_LOGIC := '0';

wren_b : IN STD_LOGIC := '0';

q_a : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);

q_b : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)

);

END mist_sector_buffer;

ARCHITECTURE SYN OF mist_sector_buffer IS

SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0);

SIGNAL sub_wire1 : STD_LOGIC_VECTOR (31 DOWNTO 0);

COMPONENT altsyncram

GENERIC (

address_reg_b : STRING;

clock_enable_input_a : STRING;

clock_enable_input_b : STRING;

clock_enable_output_a : STRING;

clock_enable_output_b : STRING;

indata_reg_b : STRING;

intended_device_family : STRING;

lpm_type : STRING;

numwords_a : NATURAL;

numwords_b : NATURAL;

operation_mode : STRING;

outdata_aclr_a : STRING;

outdata_aclr_b : STRING;

outdata_reg_a : STRING;

outdata_reg_b : STRING;

power_up_uninitialized : STRING;

read_during_write_mode_port_a : STRING;

read_during_write_mode_port_b : STRING;

widthad_a : NATURAL;

widthad_b : NATURAL;

width_a : NATURAL;

width_b : NATURAL;

width_byteena_a : NATURAL;

width_byteena_b : NATURAL;

wrcontrol_wraddress_reg_b : STRING

);

PORT (

clock0 : IN STD_LOGIC ;

wren_a : IN STD_LOGIC ;

address_b : IN STD_LOGIC_VECTOR (6 DOWNTO 0);

clock1 : IN STD_LOGIC ;

data_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);

q_a : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);

wren_b : IN STD_LOGIC ;

address_a : IN STD_LOGIC_VECTOR (8 DOWNTO 0);

data_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0);

q_b : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)

);

END COMPONENT;

BEGIN

q_a <= sub_wire0(7 DOWNTO 0);

q_b <= sub_wire1(31 DOWNTO 0);

altsyncram_component : altsyncram

GENERIC MAP (

address_reg_b => "CLOCK1",

clock_enable_input_a => "BYPASS",

clock_enable_input_b => "BYPASS",

clock_enable_output_a => "BYPASS",

clock_enable_output_b => "BYPASS",

indata_reg_b => "CLOCK1",

intended_device_family => "Cyclone III",

lpm_type => "altsyncram",

numwords_a => 512,

numwords_b => 128,

operation_mode => "BIDIR_DUAL_PORT",

outdata_aclr_a => "NONE",

outdata_aclr_b => "NONE",

outdata_reg_a => "UNREGISTERED",

outdata_reg_b => "UNREGISTERED",

power_up_uninitialized => "FALSE",

read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",

read_during_write_mode_port_b => "NEW_DATA_NO_NBE_READ",

widthad_a => 9,

widthad_b => 7,

width_a => 8,

width_b => 32,

width_byteena_a => 1,

width_byteena_b => 1,

wrcontrol_wraddress_reg_b => "CLOCK1"

)

PORT MAP (

clock0 => clock_a,

wren_a => wren_a,

address_b => address_b,

clock1 => clock_b,

data_b => data_b,

wren_b => wren_b,

address_a => address_a,

data_a => data_a,

q_a => sub_wire0,

q_b => sub_wire1

);

END SYN;

-- ============================================================

-- CNX file retrieval info

-- ============================================================

-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"

-- Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"

-- Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"

-- Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"

-- Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"

-- Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"

-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"

-- Retrieval info: PRIVATE: BlankMemory NUMERIC "1"

-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"

-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"

-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"

-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"

-- Retrieval info: PRIVATE: CLRdata NUMERIC "0"

-- Retrieval info: PRIVATE: CLRq NUMERIC "0"

-- Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"

-- Retrieval info: PRIVATE: CLRrren NUMERIC "0"

-- Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"

-- Retrieval info: PRIVATE: CLRwren NUMERIC "0"

-- Retrieval info: PRIVATE: Clock NUMERIC "5"

-- Retrieval info: PRIVATE: Clock_A NUMERIC "0"

-- Retrieval info: PRIVATE: Clock_B NUMERIC "0"

-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"

-- Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"

-- Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1"

-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"

-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"

-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"

-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"

-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"

-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"

-- Retrieval info: PRIVATE: MEMSIZE NUMERIC "4096"

-- Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"

-- Retrieval info: PRIVATE: MIFfilename STRING ""

-- Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3"

-- Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"

-- Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"

-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"

-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"

-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"

-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"

-- Retrieval info: PRIVATE: REGdata NUMERIC "1"

-- Retrieval info: PRIVATE: REGq NUMERIC "0"

-- Retrieval info: PRIVATE: REGrdaddress NUMERIC "0"

-- Retrieval info: PRIVATE: REGrren NUMERIC "0"

-- Retrieval info: PRIVATE: REGwraddress NUMERIC "1"

-- Retrieval info: PRIVATE: REGwren NUMERIC "1"

-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"

-- Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"

-- Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"

-- Retrieval info: PRIVATE: VarWidth NUMERIC "1"

-- Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "8"

-- Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "32"

-- Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "8"

-- Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "32"

-- Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"

-- Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1"

-- Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"

-- Retrieval info: PRIVATE: enable NUMERIC "0"

-- Retrieval info: PRIVATE: rden NUMERIC "0"

-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all

-- Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1"

-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"

-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"

-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"

-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"

-- Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK1"

-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"

-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"

-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "512"

-- Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "128"

-- Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT"

-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"

-- Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"

-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"

-- Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"

-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"

-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"

-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_B STRING "NEW_DATA_NO_NBE_READ"

-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "9"

-- Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "7"

-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"

-- Retrieval info: CONSTANT: WIDTH_B NUMERIC "32"

-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"

-- Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1"

-- Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK1"

-- Retrieval info: USED_PORT: address_a 0 0 9 0 INPUT NODEFVAL "address_a[8..0]"

-- Retrieval info: USED_PORT: address_b 0 0 7 0 INPUT NODEFVAL "address_b[6..0]"

-- Retrieval info: USED_PORT: clock_a 0 0 0 0 INPUT VCC "clock_a"

-- Retrieval info: USED_PORT: clock_b 0 0 0 0 INPUT NODEFVAL "clock_b"

-- Retrieval info: USED_PORT: data_a 0 0 8 0 INPUT NODEFVAL "data_a[7..0]"

-- Retrieval info: USED_PORT: data_b 0 0 32 0 INPUT NODEFVAL "data_b[31..0]"

-- Retrieval info: USED_PORT: q_a 0 0 8 0 OUTPUT NODEFVAL "q_a[7..0]"

-- Retrieval info: USED_PORT: q_b 0 0 32 0 OUTPUT NODEFVAL "q_b[31..0]"

-- Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT GND "wren_a"

-- Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT GND "wren_b"

-- Retrieval info: CONNECT: @address_a 0 0 9 0 address_a 0 0 9 0

-- Retrieval info: CONNECT: @address_b 0 0 7 0 address_b 0 0 7 0

-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock_a 0 0 0 0

-- Retrieval info: CONNECT: @clock1 0 0 0 0 clock_b 0 0 0 0

-- Retrieval info: CONNECT: @data_a 0 0 8 0 data_a 0 0 8 0

-- Retrieval info: CONNECT: @data_b 0 0 32 0 data_b 0 0 32 0

-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0

-- Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0

-- Retrieval info: CONNECT: q_a 0 0 8 0 @q_a 0 0 8 0

-- Retrieval info: CONNECT: q_b 0 0 32 0 @q_b 0 0 32 0

-- Retrieval info: GEN_FILE: TYPE_NORMAL mist_sector_buffer.vhd TRUE

-- Retrieval info: GEN_FILE: TYPE_NORMAL mist_sector_buffer.inc FALSE

-- Retrieval info: GEN_FILE: TYPE_NORMAL mist_sector_buffer.cmp TRUE

-- Retrieval info: GEN_FILE: TYPE_NORMAL mist_sector_buffer.bsf FALSE

-- Retrieval info: GEN_FILE: TYPE_NORMAL mist_sector_buffer_inst.vhd FALSE

-- Retrieval info: LIB_FILE: altera_mf

set_global_assignment -name IP_TOOL_NAME "ALTPLL"

set_global_assignment -name IP_TOOL_VERSION "13.0"

set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll_ntsc.vhd"]

set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_ntsc.cmp"]

set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_ntsc.ppf"]

--Copyright (C) 1991-2013 Altera Corporation

--Your use of Altera Corporation's design tools, logic functions

--and other software and tools, and its AMPP partner logic

--functions, and any output files from any of the foregoing

--(including device programming or simulation files), and any

--associated documentation or information are expressly subject

--to the terms and conditions of the Altera Program License

--Subscription Agreement, Altera MegaCore Function License

--Agreement, or other applicable license agreement, including,

--without limitation, that your use is for the sole purpose of

--programming logic devices manufactured by Altera and sold by

--Altera or its authorized distributors. Please refer to the

--applicable agreement for further details.

component pll_pal_pre

PORT

(

inclk0 : IN STD_LOGIC := '0';

c0 : OUT STD_LOGIC ;

locked : OUT STD_LOGIC

);

end component;

-- megafunction wizard: %ALTPLL%

-- GENERATION: STANDARD

-- VERSION: WM1.0

-- MODULE: altpll

-- ============================================================

-- File Name: pll_pal_post.vhd

-- Megafunction Name(s):

-- altpll

--

-- Simulation Library Files(s):

-- altera_mf

-- ============================================================

-- ************************************************************

-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!

--

-- 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition

-- ************************************************************

--Copyright (C) 1991-2013 Altera Corporation

--Your use of Altera Corporation's design tools, logic functions

--and other software and tools, and its AMPP partner logic

--functions, and any output files from any of the foregoing

--(including device programming or simulation files), and any

--associated documentation or information are expressly subject

--to the terms and conditions of the Altera Program License

--Subscription Agreement, Altera MegaCore Function License

--Agreement, or other applicable license agreement, including,

--without limitation, that your use is for the sole purpose of

--programming logic devices manufactured by Altera and sold by

--Altera or its authorized distributors. Please refer to the

--applicable agreement for further details.

LIBRARY ieee;

USE ieee.std_logic_1164.all;

LIBRARY altera_mf;

USE altera_mf.all;

ENTITY pll_pal_post IS

PORT

(

areset : IN STD_LOGIC := '0';

inclk0 : IN STD_LOGIC := '0';

c0 : OUT STD_LOGIC ;

c1 : OUT STD_LOGIC ;

c2 : OUT STD_LOGIC ;

c3 : OUT STD_LOGIC ;

locked : OUT STD_LOGIC

);

END pll_pal_post;

ARCHITECTURE SYN OF pll_pal_post IS

SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0);

SIGNAL sub_wire1 : STD_LOGIC ;

SIGNAL sub_wire2 : STD_LOGIC ;

SIGNAL sub_wire3 : STD_LOGIC ;

SIGNAL sub_wire4 : STD_LOGIC ;

SIGNAL sub_wire5 : STD_LOGIC ;

SIGNAL sub_wire6 : STD_LOGIC ;

SIGNAL sub_wire7 : STD_LOGIC_VECTOR (1 DOWNTO 0);

SIGNAL sub_wire8_bv : BIT_VECTOR (0 DOWNTO 0);

SIGNAL sub_wire8 : STD_LOGIC_VECTOR (0 DOWNTO 0);

COMPONENT altpll

GENERIC (

bandwidth_type : STRING;

clk0_divide_by : NATURAL;

clk0_duty_cycle : NATURAL;

clk0_multiply_by : NATURAL;

clk0_phase_shift : STRING;

clk1_divide_by : NATURAL;

clk1_duty_cycle : NATURAL;

clk1_multiply_by : NATURAL;

clk1_phase_shift : STRING;

clk2_divide_by : NATURAL;

clk2_duty_cycle : NATURAL;

clk2_multiply_by : NATURAL;

clk2_phase_shift : STRING;

clk3_divide_by : NATURAL;

clk3_duty_cycle : NATURAL;

clk3_multiply_by : NATURAL;

clk3_phase_shift : STRING;

compensate_clock : STRING;

inclk0_input_frequency : NATURAL;

intended_device_family : STRING;

lpm_hint : STRING;

lpm_type : STRING;

operation_mode : STRING;

pll_type : STRING;

port_activeclock : STRING;

port_areset : STRING;

port_clkbad0 : STRING;

port_clkbad1 : STRING;

port_clkloss : STRING;

port_clkswitch : STRING;

port_configupdate : STRING;

port_fbin : STRING;

port_inclk0 : STRING;

port_inclk1 : STRING;

port_locked : STRING;

port_pfdena : STRING;

port_phasecounterselect : STRING;

port_phasedone : STRING;

port_phasestep : STRING;

port_phaseupdown : STRING;

port_pllena : STRING;

port_scanaclr : STRING;

port_scanclk : STRING;

port_scanclkena : STRING;

port_scandata : STRING;

port_scandataout : STRING;

port_scandone : STRING;

port_scanread : STRING;

port_scanwrite : STRING;

port_clk0 : STRING;

port_clk1 : STRING;

port_clk2 : STRING;

port_clk3 : STRING;

port_clk4 : STRING;

port_clk5 : STRING;

port_clkena0 : STRING;

port_clkena1 : STRING;

port_clkena2 : STRING;

port_clkena3 : STRING;

port_clkena4 : STRING;

port_clkena5 : STRING;

port_extclk0 : STRING;

port_extclk1 : STRING;

port_extclk2 : STRING;

port_extclk3 : STRING;

self_reset_on_loss_lock : STRING;