Revision 23
Added by markw over 11 years ago
| mist/atari800core.sdc | ||
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create_clock -period 27MHz [get_ports CLOCK_27[0]]
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derive_pll_clocks
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derive_clock_uncertainty
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create_generated_clock -name sdclk_pin -source [get_pins {clock|altpll_component|auto_generated|pll1|clk[2]}] [get_ports {SDRAM_CLK}]
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derive_clock_uncertainty
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set_input_delay -clock sdclk_pin -max 6.4 [get_ports SDRAM_DQ*]
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set_input_delay -clock sdclk_pin -min 3.2 [get_ports SDRAM_DQ*]
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set_output_delay -clock sdclk_pin -max 1.5 [get_ports SDRAM_*]
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set_output_delay -clock sdclk_pin -min -0.8 [get_ports SDRAM_*]
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set_multicycle_path -from [get_clocks {sdclk_pin}] -to [get_clocks {clock|altpll_component|auto_generated|pll1|clk[0]}] -setup -end 2
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Also available in: Unified diff
Adjusted this based on mist settings - in the hope this will mean I need to tweak the phase offset less...