Revision 223
Added by markw about 11 years ago
| gpio.vhd | ||
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signal bus_addr_out : std_logic_vector(15 downto 0);
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signal bus_addr_oe : std_logic;
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signal bus_write_n : std_logic;
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signal bus_s4_n : std_logic;
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signal bus_s5_n : std_logic;
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signal bus_cctl_n : std_logic;
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signal bus_control_oe : std_logic;
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signal phi2 : std_logic;
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signal rd4_async : std_logic;
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| ... | ... | |
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GPIO_0_OUT(23) <= bus_addr_out(4);
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GPIO_0_DIR_OUT(22) <= '0'; -- RD4 rom present
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GPIO_0_OUT(22) <= '0'; -- RD4 rom present
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GPIO_0_DIR_OUT(21) <= gpio_enable;
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GPIO_0_OUT(21) <= S4_n;
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GPIO_0_DIR_OUT(21) <= gpio_enable and bus_control_oe;
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GPIO_0_OUT(21) <= bus_s4_n;
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GPIO_0_DIR_OUT(20) <= gpio_enable and bus_addr_oe;
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GPIO_0_OUT(20) <= bus_addr_out(3);
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GPIO_0_DIR_OUT(19) <= gpio_enable and bus_addr_oe;
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| ... | ... | |
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GPIO_0_OUT(12) <= bus_data_out(0); -- d0
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GPIO_0_DIR_OUT(11) <= gpio_enable and bus_data_oe; -- d6
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GPIO_0_OUT(11) <= bus_data_out(6); -- d6
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GPIO_0_DIR_OUT(10) <= gpio_enable;
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GPIO_0_OUT(10) <= S5_n;
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GPIO_0_DIR_OUT(10) <= gpio_enable and bus_control_oe;
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GPIO_0_OUT(10) <= bus_s5_n;
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GPIO_0_DIR_OUT(9) <= '0'; -- RD5 rom present
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GPIO_0_OUT(9) <= '0'; -- RD5 rom present
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GPIO_0_DIR_OUT(8) <= gpio_enable; -- cart control
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GPIO_0_OUT(8) <= CCTL_n; -- cart control
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GPIO_0_DIR_OUT(8) <= gpio_enable and bus_control_oe; -- cart control
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GPIO_0_OUT(8) <= bus_cctl_n; -- cart control
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-- PBI: A13-A15
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GPIO_0_DIR_OUT(7) <= gpio_enable and bus_addr_oe;
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| ... | ... | |
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bus_adaptor : ENTITY work.timing6502
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GENERIC MAP
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(
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CYCLE_LENGTH => cartridge_cycle_length
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CYCLE_LENGTH => cartridge_cycle_length,
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CONTROl_BITS => 3
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)
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PORT MAP
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(
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| ... | ... | |
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ADDR_IN => pbi_addr_out,
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DATA_IN => cart_data_write,
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WRITE_IN => pbi_write_enable,
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CONTROL_N_IN => s4_n&s5_n&cctl_n,
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DATA_OUT => cart_data_read,
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COMPLETE => cart_complete,
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| ... | ... | |
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BUS_ADDR_OE => bus_addr_oe,
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BUS_DATA_OUT => bus_data_out,
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BUS_DATA_OE => bus_data_oe,
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BUS_WRITE_N => bus_write_n
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BUS_WRITE_N => bus_write_n,
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BUS_CONTROL_N(2) => bus_s4_n,
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BUS_CONTROL_N(1) => bus_s5_n,
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BUS_CONTROL_N(0) => bus_cctl_n,
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BUS_CONTROL_OE => bus_control_oe
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);
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rd4_async <= gpio_enable and GPIO_0_IN(22);
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Pass s4_n,s5_n and cctl_n through 6502 timing adaptor. Only accept request at start of cycle.