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Revision 223

Added by markw almost 11 years ago

Pass s4_n,s5_n and cctl_n through 6502 timing adaptor. Only accept request at start of cycle.

View differences:

common/a8core/timing6502.vhd
ENTITY timing6502 IS
GENERIC
(
CYCLE_LENGTH : INTEGER :=32
CYCLE_LENGTH : INTEGER :=32;
CONTROL_BITS : INTEGER :=0
);
PORT
(
......
ADDR_IN : IN STD_LOGIC_VECTOR(15 downto 0);
DATA_IN : IN STD_LOGIC_VECTOR(7 downto 0);
WRITE_IN : IN STD_LOGIC;
CONTROL_N_IN : IN STD_LOGIC_VECTOR(CONTROL_BITS-1 downto 0);
DATA_OUT : OUT STD_LOGIC_VECTOR(7 downto 0);
COMPLETE : OUT STD_LOGIC;
......
BUS_ADDR_OE : OUT STD_LOGIC;
BUS_DATA_OUT : OUT STD_LOGIC_VECTOR(7 downto 0);
BUS_DATA_OE : OUT STD_LOGIC;
BUS_WRITE_N : OUT STD_LOGIC
BUS_WRITE_N : OUT STD_LOGIC;
BUS_CONTROL_N : OUT STD_LOGIC_VECTOR(CONTROL_BITS-1 downto 0);
BUS_CONTROL_OE : OUT STD_LOGIC
);
END timing6502;
......
signal write_n_next : std_logic;
signal write_n_reg : std_logic;
signal control_n_next : std_logic_vector(CONTROL_BITS-1 downto 0);
signal control_n_reg : std_logic_vector(CONTROL_BITS-1 downto 0);
signal control_oe_next : std_logic;
signal control_oe_reg : std_logic;
signal complete_next : std_logic;
signal complete_reg : std_logic;
signal request_pending_next : std_logic;
signal request_pending_reg : std_logic;
signal request_handling_next : std_logic;
signal request_handling_reg : std_logic;
BEGIN
-- regs
......
phi1_reg <= '0';
phi2_reg <= '0';
write_n_reg <= '1';
control_n_reg <= (others=>'1');
control_oe_reg <= '0';
complete_reg <= '0';
request_pending_reg <= '0';
request_handling_reg <= '0';
elsif (clk'event and clk='1') then
state_reg <= state_next;
odd_reg <= odd_next;
......
phi1_reg <= phi1_next;
phi2_reg <= phi2_next;
write_n_reg <= write_n_next;
control_n_reg <= control_n_next;
control_oe_reg <= control_oe_next;
complete_reg <= complete_next;
request_pending_reg <= request_pending_next;
request_handling_reg <= request_handling_next;
end if;
end process;
-- next state
process(enable_179_early, state_reg, odd_reg, phi1_reg, phi2_reg, request, addr_in, data_in, addr_reg, addr_oe_reg, data_reg, data_oe_reg, data_read_reg, bus_data_in, write_n_reg, write_in)
process(enable_179_early, state_reg, odd_reg, phi1_reg, phi2_reg, request, addr_in, data_in, addr_reg, addr_oe_reg, data_reg, data_oe_reg, data_read_reg, bus_data_in, write_n_reg, write_in, request_pending_reg, request_handling_reg, control_n_reg, control_oe_reg)
begin
state_next <= state_reg;
odd_next <= not(odd_reg);
......
complete_next <= '0';
data_read_next <= data_read_reg;
write_n_next <= write_n_reg;
request_pending_next <= request_pending_reg;
request_handling_next <= request_handling_reg;
control_n_next <= control_n_reg;
control_oe_next <= control_oe_reg;
if (enable_179_early = '1') then
state_next <= (others=>'0'); -- re-sync
......
state_next <= std_logic_vector(unsigned(state_reg)+1);
end if;
if (request = '1') then
addr_next <= addr_in;
data_next <= data_in;
write_n_next <= not(write_in);
end if;
request_pending_next <= request_pending_reg or request;
case state_reg is
when x"0" =>
if ((request or request_pending_reg)='1') then
addr_next <= addr_in;
data_next <= data_in;
write_n_next <= not(write_in);
control_n_next <= control_n_in;
request_pending_next <= '0';
request_handling_next <= '1';
end if;
when x"1"=>
addr_oe_next <= '1';
control_oe_next <= '1';
when x"2"|x"3"|x"4"|x"5" =>
when x"6" =>
phi1_next <= '0';
......
end if;
when x"c" =>
when x"d" =>
complete_next <= '1';
complete_next <= request_handling_reg;
request_handling_next <= '0';
data_read_next <= bus_data_in;
when x"e" =>
phi2_next <= '0';
when x"f" =>
addr_next <= (others=>'0');
addr_oe_next <= '0';
control_n_next <= (others=>'1');
control_oe_next <= '0';
data_oe_next <= '0';
write_n_next <= '1';
phi1_next <= '1';
......
BUS_DATA_OUT <= data_reg;
BUS_DATA_OE <= data_oe_reg;
BUS_WRITE_N <= write_n_reg;
BUS_CONTROL_N <= control_n_reg;
BUS_CONTROL_OE <= control_oe_reg;
DATA_OUT <= data_read_reg;
COMPLETE <= complete_reg;
de1/gpio.vhd
signal bus_addr_out : std_logic_vector(15 downto 0);
signal bus_addr_oe : std_logic;
signal bus_write_n : std_logic;
signal bus_s4_n : std_logic;
signal bus_s5_n : std_logic;
signal bus_cctl_n : std_logic;
signal bus_control_oe : std_logic;
signal phi2 : std_logic;
signal rd4_async : std_logic;
......
GPIO_0_OUT(23) <= bus_addr_out(4);
GPIO_0_DIR_OUT(22) <= '0'; -- RD4 rom present
GPIO_0_OUT(22) <= '0'; -- RD4 rom present
GPIO_0_DIR_OUT(21) <= gpio_enable;
GPIO_0_OUT(21) <= S4_n;
GPIO_0_DIR_OUT(21) <= gpio_enable and bus_control_oe;
GPIO_0_OUT(21) <= bus_s4_n;
GPIO_0_DIR_OUT(20) <= gpio_enable and bus_addr_oe;
GPIO_0_OUT(20) <= bus_addr_out(3);
GPIO_0_DIR_OUT(19) <= gpio_enable and bus_addr_oe;
......
GPIO_0_OUT(12) <= bus_data_out(0); -- d0
GPIO_0_DIR_OUT(11) <= gpio_enable and bus_data_oe; -- d6
GPIO_0_OUT(11) <= bus_data_out(6); -- d6
GPIO_0_DIR_OUT(10) <= gpio_enable;
GPIO_0_OUT(10) <= S5_n;
GPIO_0_DIR_OUT(10) <= gpio_enable and bus_control_oe;
GPIO_0_OUT(10) <= bus_s5_n;
GPIO_0_DIR_OUT(9) <= '0'; -- RD5 rom present
GPIO_0_OUT(9) <= '0'; -- RD5 rom present
GPIO_0_DIR_OUT(8) <= gpio_enable; -- cart control
GPIO_0_OUT(8) <= CCTL_n; -- cart control
GPIO_0_DIR_OUT(8) <= gpio_enable and bus_control_oe; -- cart control
GPIO_0_OUT(8) <= bus_cctl_n; -- cart control
-- PBI: A13-A15
GPIO_0_DIR_OUT(7) <= gpio_enable and bus_addr_oe;
......
bus_adaptor : ENTITY work.timing6502
GENERIC MAP
(
CYCLE_LENGTH => cartridge_cycle_length
CYCLE_LENGTH => cartridge_cycle_length,
CONTROl_BITS => 3
)
PORT MAP
(
......
ADDR_IN => pbi_addr_out,
DATA_IN => cart_data_write,
WRITE_IN => pbi_write_enable,
CONTROL_N_IN => s4_n&s5_n&cctl_n,
DATA_OUT => cart_data_read,
COMPLETE => cart_complete,
......
BUS_ADDR_OE => bus_addr_oe,
BUS_DATA_OUT => bus_data_out,
BUS_DATA_OE => bus_data_oe,
BUS_WRITE_N => bus_write_n
BUS_WRITE_N => bus_write_n,
BUS_CONTROL_N(2) => bus_s4_n,
BUS_CONTROL_N(1) => bus_s5_n,
BUS_CONTROL_N(0) => bus_cctl_n,
BUS_CONTROL_OE => bus_control_oe
);
rd4_async <= gpio_enable and GPIO_0_IN(22);

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