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Revision 221

Added by markw about 11 years ago

Patches from Hias. Fix timing to allow The!Cart to work. Start of PBI work.

View differences:

common/a8core/address_decoder.vhdl
freezer_enable: in std_logic;
freezer_activate: in std_logic;
freezer_state_out: out std_logic_vector(2 downto 0)
freezer_state_out: out std_logic_vector(2 downto 0);
pbi_enable: in std_logic := '0'
);
END address_decoder;
......
--cart_s4_n <= emu_cart_s4_n_out;
--cart_s5_n <= emu_cart_s5_n_out;
CART_TRIG3_OUT <= CART_RD5 or emu_cart_rd5;
CART_TRIG3_OUT <= (pbi_enable and CART_RD5) or emu_cart_rd5;
-- ANTIC FETCH
......
request_complete <= '1';
end if;
else
if ((CART_RD4 or CART_RD5) = '1') then
if (pbi_enable = '1') then
PBI_WR_ENABLE <= write_enable_next;
MEMORY_DATA(7 downto 0) <= CART_ROM_DATA;
cart_request <= start_request;
......
sdram_chip_select <= '0';
ram_chip_select <= '0';
end if;
elsif (cart_rd4 = '1') then
elsif (pbi_enable = '1' and cart_rd4 = '1') then
PBI_WR_ENABLE <= write_enable_next;
MEMORY_DATA(7 downto 0) <= CART_ROM_DATA;
cart_request <= start_request;
CART_S4_n <= '0';
......
sdram_chip_select <= '0';
ram_chip_select <= '0';
end if;
elsif (cart_rd5 = '1') then
elsif (pbi_enable = '1' and cart_rd5 = '1') then
PBI_WR_ENABLE <= write_enable_next;
MEMORY_DATA(7 downto 0) <= CART_ROM_DATA;
cart_request <= start_request;
CART_S5_n <= '0';
common/a8core/atari800core.vhd
HALT : in std_logic;
freezer_enable: in std_logic;
freezer_activate: in std_logic;
freezer_state_out: out std_logic_vector(2 downto 0)
freezer_state_out: out std_logic_vector(2 downto 0);
pbi_enable: in std_logic := '0'
);
END atari800core;
......
rom_in_ram => ROM_IN_RAM,
freezer_enable => freezer_enable,
freezer_activate => freezer_activate,
freezer_state_out => freezer_state_out);
freezer_state_out => freezer_state_out,
pbi_enable => pbi_enable);
pokey1 : entity work.pokey
PORT MAP(CLK => CLK,
common/a8core/timing6502.vhd
case state_reg is
when x"0" =>
phi1_next <= '1';
when x"1"=>
addr_oe_next <= '1';
when x"2"|x"3"|x"4"|x"5" =>
when x"6" =>
phi1_next <= '0';
when x"7" =>
phi2_next <= '1';
when x"8" =>
phi2_next <= '1';
when x"9"|x"a" =>
when x"b" =>
if (write_in = '1') then
......
addr_oe_next <= '0';
data_oe_next <= '0';
write_n_next <= '1';
phi1_next <= '1';
end case;
end process;
de1/atari800core_de1.vhd
signal freezer_state: std_logic_vector(2 downto 0);
signal pbi_enable: std_logic;
BEGIN
pbi_enable <= SW(4);
-- ANYTHING NOT CONNECTED...
--GPIO_0(0) <= 'Z';
--GPIO_0(35 downto 2) <= (others=>'Z');
......
)
PORT MAP(clk => CLK,
reset_n => reset_n,
gpio_enable => SW(4),
gpio_enable => pbi_enable,
pot_reset => pot_reset,
pbi_write_enable => pbi_write_enable,
enable_179_early => enable_179_early,
......
freezer_enable => freezer_enable,
freezer_activate => freezer_activate,
freezer_state_out => freezer_state
freezer_state_out => freezer_state,
pbi_enable => pbi_enable
);
zpu: entity work.zpucore
de1/gpio.vhd
GPIO_1_DIR_OUT(18 downto 8) <= (others=>'0');
GPIO_1_OUT(18 downto 8) <= (others=>'0');
GPIO_0_DIR_OUT(7 downto 5) <= (others=>'0');
GPIO_0_OUT(7 downto 5) <= (others=>'0');
-- sio
GPIO_0_DIR_OUT(0) <= CA2_dir_out;
GPIO_0_OUT(0) <= CA2_out;
......
GPIO_0_OUT(9) <= '0'; -- RD5 rom present
GPIO_0_DIR_OUT(8) <= gpio_enable; -- cart control
GPIO_0_OUT(8) <= CCTL_n; -- cart control
GPIO_0_DIR_OUT(7 downto 5) <= (others=>'0'); -- unused
GPIO_0_OUT(7 downto 5) <= (others=>'0'); -- unused
-- PBI: A13-A15
GPIO_0_DIR_OUT(7) <= gpio_enable and bus_addr_oe;
GPIO_0_OUT(7) <= bus_addr_out(15);
GPIO_0_DIR_OUT(6) <= gpio_enable and bus_addr_oe;
GPIO_0_OUT(6) <= bus_addr_out(14);
GPIO_0_DIR_OUT(5) <= gpio_enable and bus_addr_oe;
GPIO_0_OUT(5) <= bus_addr_out(13);
-- INPUTS FROM GPIO
-- sticks

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