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Revision 22

Added by markw over 11 years ago

Connected up SDRAM. Make 800XL core wait for SDRAM reset to complete. Also had to adjust phase offset to make it work - need to get a proper setup for mist

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mist/atari800core.qsf
set_global_assignment -name VHDL_FILE data_io.vhdl
set_global_assignment -name SDC_FILE atari800core.sdc
set_global_assignment -name QIP_FILE mist_sector_buffer.qip
set_global_assignment -name VHDL_FILE sdram_statemachine.vhdl
set_global_assignment -name VHDL_FILE atari800core_mist.vhd
set_global_assignment -name VERILOG_FILE user_io.v
set_global_assignment -name QIP_FILE pll.qip
mist/atari800core_mist.vhd
SIGNAL THROTTLE_COUNT_6502 : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL PAL : std_logic;
signal SDRAM_REQUEST : std_logic;
signal SDRAM_REQUEST_COMPLETE : std_logic;
signal SDRAM_READ_ENABLE : STD_LOGIC;
signal SDRAM_WRITE_ENABLE : std_logic;
signal SDRAM_ADDR : STD_LOGIC_VECTOR(22 DOWNTO 0);
signal SDRAM_DO : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal SDRAM_DI : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal SDRAM_WIDTH_8bit_ACCESS : std_logic;
signal SDRAM_WIDTH_16bit_ACCESS : std_logic;
signal SDRAM_WIDTH_32bit_ACCESS : std_logic;
signal SDRAM_REFRESH : std_logic;
signal SYSTEM_RESET_REQUEST: std_logic;
signal SDRAM_RESET_N : std_logic;
BEGIN
pal <= '1'; -- TODO, two builds, with appropriate pll settings
......
--HOT KEYS! Connect to ZPU when present...
--virtual_keys <= keyboard(65)&keyboard(66)&keyboard(67)&keyboard(68);
--SYSTEM_RESET_REQUEST <= keyboard(63);
SYSTEM_RESET_REQUEST <= keyboard(63);
-- TODO this should be common, same for PS2 after mapping...
process(keyboard_scan, atari_keyboard, control_pressed, shift_pressed, break_pressed)
......
(
cycle_length => 32,
internal_rom => 1,
internal_ram => 16384
internal_ram => 0
)
PORT MAP
(
CLK => CLK,
RESET_N => RESET_N,
RESET_N => RESET_N and SDRAM_RESET_N and not(SYSTEM_RESET_REQUEST),
VGA_VS => VGA_VS_RAW,
VGA_HS => VGA_HS_RAW,
......
CONSOL_SELECT => CONSOL_SELECT,
CONSOL_START => CONSOL_START,
SDRAM_REQUEST => open,
SDRAM_REQUEST_COMPLETE => '1',
SDRAM_READ_ENABLE => open,
SDRAM_WRITE_ENABLE => open,
SDRAM_ADDR => open,
SDRAM_DO => (others=>'1'),
SDRAM_REQUEST => SDRAM_REQUEST,
SDRAM_REQUEST_COMPLETE => SDRAM_REQUEST_COMPLETE,
SDRAM_READ_ENABLE => SDRAM_READ_ENABLE,
SDRAM_WRITE_ENABLE => SDRAM_WRITE_ENABLE,
SDRAM_ADDR => SDRAM_ADDR,
SDRAM_DO => SDRAM_DO,
SDRAM_DI => SDRAM_DI,
SDRAM_32BIT_WRITE_ENABLE => SDRAM_WIDTH_32bit_ACCESS,
SDRAM_16BIT_WRITE_ENABLE => SDRAM_WIDTH_16bit_ACCESS,
SDRAM_8BIT_WRITE_ENABLE => SDRAM_WIDTH_8bit_ACCESS,
DMA_FETCH => '0',
DMA_READ_ENABLE => '0',
......
THROTTLE_COUNT_6502 => THROTTLE_COUNT_6502
);
--b2v_inst20 : sdram_statemachine
--GENERIC MAP(ADDRESS_WIDTH => 22,
-- AP_BIT => 10,
-- COLUMN_WIDTH => 8,
-- ROW_WIDTH => 12
-- )
--PORT MAP(CLK_SYSTEM => CLK,
-- CLK_SDRAM => CLK_SDRAM,
-- RESET_N => RESET_N,
-- READ_EN => SDRAM_READ_ENABLE,
-- WRITE_EN => SDRAM_WRITE_ENABLE,
-- REQUEST => SDRAM_REQUEST,
-- BYTE_ACCESS => WIDTH_8BIT_ACCESS,
-- WORD_ACCESS => WIDTH_16BIT_ACCESS,
-- LONGWORD_ACCESS => WIDTH_32BIT_ACCESS,
-- REFRESH => SDRAM_REFRESH,
-- ADDRESS_IN => SDRAM_ADDR,
-- DATA_IN => WRITE_DATA,
-- SDRAM_DQ => SDRAM_DQ,
-- COMPLETE => SDRAM_REQUEST_COMPLETE,
-- SDRAM_BA0 => SDRAM_BA(0),
-- SDRAM_BA1 => SDRAM_BA(1),
-- SDRAM_CKE => SDRAM_CKE,
-- SDRAM_CS_N => SDRAM_nCS,
-- SDRAM_RAS_N => SDRAM_nRAS,
-- SDRAM_CAS_N => SDRAM_nCAS,
-- SDRAM_WE_N => SDRAM_nWE,
-- SDRAM_ldqm => SDRAM_DQML,
-- SDRAM_udqm => SDRAM_DQMH,
-- DATA_OUT => SDRAM_DO,
-- SDRAM_ADDR => SDRAM_A(11 downto 0));
--
--SDRAM_A(12) <= '0';
sdram_adaptor : entity work.sdram_statemachine
GENERIC MAP(ADDRESS_WIDTH => 22,
AP_BIT => 10,
COLUMN_WIDTH => 8,
ROW_WIDTH => 12
)
PORT MAP(CLK_SYSTEM => CLK,
CLK_SDRAM => CLK_SDRAM,
RESET_N => RESET_N and not(SYSTEM_RESET_REQUEST),
READ_EN => SDRAM_READ_ENABLE,
WRITE_EN => SDRAM_WRITE_ENABLE,
REQUEST => SDRAM_REQUEST,
BYTE_ACCESS => SDRAM_WIDTH_8BIT_ACCESS,
WORD_ACCESS => SDRAM_WIDTH_16BIT_ACCESS,
LONGWORD_ACCESS => SDRAM_WIDTH_32BIT_ACCESS,
REFRESH => SDRAM_REFRESH,
ADDRESS_IN => SDRAM_ADDR,
DATA_IN => SDRAM_DI,
SDRAM_DQ => SDRAM_DQ,
COMPLETE => SDRAM_REQUEST_COMPLETE,
SDRAM_BA0 => SDRAM_BA(0),
SDRAM_BA1 => SDRAM_BA(1),
SDRAM_CKE => SDRAM_CKE,
SDRAM_CS_N => SDRAM_nCS,
SDRAM_RAS_N => SDRAM_nRAS,
SDRAM_CAS_N => SDRAM_nCAS,
SDRAM_WE_N => SDRAM_nWE,
SDRAM_ldqm => SDRAM_DQML,
SDRAM_udqm => SDRAM_DQMH,
DATA_OUT => SDRAM_DO,
SDRAM_ADDR => SDRAM_A(11 downto 0),
reset_client_n => SDRAM_RESET_N
);
SDRAM_A(12) <= '0';
SDRAM_REFRESH <= '0'; -- TODO
-- Until SDRAM enabled... TODO
SDRAM_nCS <= '1';
SDRAM_DQ <= (others=>'Z');
--SDRAM_nCS <= '1';
--SDRAM_DQ <= (others=>'Z');
--SDRAM_CKE <= '1';
LED <= '0';
mist/build.sh
rm -rf build
mkdir build
cp atari800core_mist.vhd build
cp sdram_statemachine.vhdl build
cp pll.* build
cp atari800core.sdc build
cp data_io.vhdl build
cp user_io.v build
cp mist_sector_buffer.* build
mkdir build/common
mkdir build/common/a8core
mkdir build/common/components
cp ../common/a8core/* ./build/common/a8core
cp ../common/components/* ./build/common/components
cd build
../makeqsf ../atari800core.qsf ../../common/a8core ../../common/components
../makeqsf ../atari800core.qsf ./common/a8core ./common/components
quartus_sh --flow compile atari800core
mist/pll.bsf
(text "Clk " (rect 51 93 116 197)(font "Arial" ))
(text "Ratio" (rect 72 93 164 197)(font "Arial" ))
(text "Ph (dg)" (rect 99 93 227 197)(font "Arial" ))
(text "DC (%)" (rect 133 93 296 197)(font "Arial" ))
(text "DC (%)" (rect 134 93 298 197)(font "Arial" ))
(text "c0" (rect 54 107 116 225)(font "Arial" ))
(text "69/16" (rect 72 107 165 225)(font "Arial" ))
(text "0.00" (rect 105 107 226 225)(font "Arial" ))
(text "50.00" (rect 137 107 295 225)(font "Arial" ))
(text "50.00" (rect 138 107 297 225)(font "Arial" ))
(text "c1" (rect 54 121 115 253)(font "Arial" ))
(text "69/32" (rect 72 121 165 253)(font "Arial" ))
(text "0.00" (rect 105 121 226 253)(font "Arial" ))
(text "50.00" (rect 137 121 295 253)(font "Arial" ))
(text "50.00" (rect 138 121 297 253)(font "Arial" ))
(text "c2" (rect 54 135 116 281)(font "Arial" ))
(text "69/16" (rect 72 135 165 281)(font "Arial" ))
(text "-67.06" (rect 101 135 226 281)(font "Arial" ))
(text "50.00" (rect 137 135 295 281)(font "Arial" ))
(text "-100.60" (rect 99 135 227 281)(font "Arial" ))
(text "50.00" (rect 138 135 297 281)(font "Arial" ))
(line (pt 0 0)(pt 257 0))
(line (pt 257 0)(pt 257 185))
(line (pt 0 185)(pt 257 185))
(line (pt 0 0)(pt 0 185))
(line (pt 48 91)(pt 165 91))
(line (pt 48 104)(pt 165 104))
(line (pt 48 118)(pt 165 118))
(line (pt 48 132)(pt 165 132))
(line (pt 48 146)(pt 165 146))
(line (pt 48 91)(pt 166 91))
(line (pt 48 104)(pt 166 104))
(line (pt 48 118)(pt 166 118))
(line (pt 48 132)(pt 166 132))
(line (pt 48 146)(pt 166 146))
(line (pt 48 91)(pt 48 146))
(line (pt 69 91)(pt 69 146)(line_width 3))
(line (pt 96 91)(pt 96 146)(line_width 3))
(line (pt 130 91)(pt 130 146)(line_width 3))
(line (pt 164 91)(pt 164 146))
(line (pt 131 91)(pt 131 146)(line_width 3))
(line (pt 165 91)(pt 165 146))
(line (pt 40 48)(pt 207 48))
(line (pt 207 48)(pt 207 167))
(line (pt 40 167)(pt 207 167))
mist/pll.vhd
clk2_divide_by => 16,
clk2_duty_cycle => 50,
clk2_multiply_by => 69,
clk2_phase_shift => "-1600",
clk2_phase_shift => "-2400",
compensate_clock => "CLK0",
inclk0_input_frequency => 37037,
intended_device_family => "Cyclone III",
......
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "-1.60000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "-2.40000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ns"
......
-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "16"
-- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "69"
-- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "-1600"
-- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "-2400"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
mist/sdram_statemachine.vhdl
SDRAM_WE_N : out std_logic;
SDRAM_ldqm : out std_logic; -- low enable, high disable - for byte addressing - NB, cas latency applies to reads
SDRAM_udqm : out std_logic
SDRAM_udqm : out std_logic;
reset_client_n : out std_logic
);
END sdram_statemachine;
......
signal sdram_request_reg : std_logic;
signal sdram_request_next : std_logic;
signal reset_client_n_reg : std_logic;
signal reset_client_n_next : std_logic;
BEGIN
-- register
process(CLK_SDRAM,reset_n)
......
reply_sreg <= '0';
sdram_request_reg <= '0';
reset_client_n_reg <= '0';
elsif (CLK_SYSTEM'event and CLK_SYSTEM='1') then
data_in_sreg <= data_in_snext;
address_in_sreg <= address_in_snext;
......
reply_sreg <= reply_snext;
sdram_request_reg <= sdram_request_next;
reset_client_n_reg <= reset_client_n_next;
end if;
end process;
......
end process;
--
process(sdram_state_reg,delay_reg, idle_priority, data_out_reg, read_en_sreg, write_en_sreg, address_in_sreg, data_in_sreg, reply_reg, require_refresh, dq_in_next, dqm_mask_sreg, request_sreg)
process(reset_client_n_reg,sdram_state_reg,delay_reg, idle_priority, data_out_reg, read_en_sreg, write_en_sreg, address_in_sreg, data_in_sreg, reply_reg, require_refresh, dq_in_next, dqm_mask_sreg, request_sreg)
begin
idle_priority <= (others=>'0');
refreshing_now <= '0';
reset_client_n_next <= reset_client_n_reg;
sdram_state_next <= sdram_state_reg;
command_next <= sdram_command_no_operation;
......
-- nop
end case;
when sdram_state_idle =>
reset_client_n_next <= '1';
delay_next <= (others=>'0');
idle_priority <= (request_sreg xor reply_reg)&require_refresh&write_en_sreg&read_en_sreg;
......
COMPLETE <= (reply_sreg xnor sdram_request_reg) and not(request);
sdram_request_next <= sdram_request_reg xor request;
reset_client_n <= reset_client_n_reg;
END vhdl;

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