Revision 212
Added by markw about 11 years ago
| common/a8core/freezer_logic.vhd | ||
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-- shadow writes to D0xx, D2xx, D4xx
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if (rw = '0') then
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case a(15 downto 8) is
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when x"D0" | x"D2" | x"D4" =>
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when x"D0" | x"D2" | x"D3" | x"D4" =>
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output.shadow_enable <= true;
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output.adr(16 downto 8) <= freezer_def_ram_bank & a(11 downto 8);
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-- GTIA/D000 needs 32 bytes, others 16 bytes
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| ... | ... | |
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bram_request <= '0';
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if (output.shadow_enable) then
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bram_adr <= output.adr(10 downto 9) & output.adr(4 downto 0);
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bram_adr <= output.adr(9)&(output.adr(8) or output.adr(10))&output.adr(4 downto 0);
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bram_we <= '1';
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elsif (output.dout_enable) then
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access_type <= access_type_data;
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| ... | ... | |
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-- map shadow ram access to blockram
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if (output.adr(16 downto 12) = freezer_def_ram_bank) and (output.adr(7 downto 5) = "000") then
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case output.adr(11 downto 8) is
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when x"0" | x"2" | x"4" =>
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when x"0" | x"2" | x"3" | x"4" =>
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access_type <= access_type_data;
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bram_adr <= output.adr(10 downto 9) & output.adr(4 downto 0);
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bram_adr <= output.adr(9)&(output.adr(8) or output.adr(10))&output.adr(4 downto 0);
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bram_we <= request and not rw;
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bram_request <= request;
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request_complete <= bram_request_complete;
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| ... | ... | |
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generic map
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(
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ADDRESS_WIDTH => 7,
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SPACE => 96,
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SPACE => 128,
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DATA_WIDTH =>8
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)
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PORT MAP(clock => clk,
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Fix PIA store. Checked freezer source, it expects it