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Revision 209

Added by markw almost 11 years ago

Added some glue to talk to 6502 style bus with phi1/phi2 etc. Connected to GPIO including phi2 out. VBXE carts not running more reliably. In theory other carts such as The!Cart etc should work now, need to test...

View differences:

common/a8core/atari800core.vhd
POT_RESET : OUT STD_LOGIC;
-- PBI
ENABLE_179_EARLY : out std_logic; -- used for phi2 generation - 1 cycle before orig cpu runs
PBI_ADDR : out STD_LOGIC_VECTOR(15 DOWNTO 0);
PBI_WRITE_ENABLE : out STD_LOGIC; -- currently only for CART config...
PBI_SNOOP_DATA : out std_logic_vector(31 downto 0); -- snoop the bus (i.e. what gets feed to the CPU data in)
......
-- outputs
PBI_ADDR <= PBI_ADDR_INT;
ENABLE_179_EARLY <= ANTIC_ENABLE_179;
PORTB_OUT <= PORTB_OUT_INT;
ANTIC_REFRESH <= ANTIC_REFRESH_CYCLE;
common/a8core/timing6502.vhd
---------------------------------------------------------------------------
-- (c) 2013 mark watson
-- I am happy for anyone to use this for non-commercial use.
-- If my vhdl files are used commercially or otherwise sold,
-- please contact me for explicit permission at scrameta (gmail).
-- This applies for source and binary form and derived works.
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.numeric_std.all;
ENTITY timing6502 IS
GENERIC
(
CYCLE_LENGTH : INTEGER :=32
);
PORT
(
CLK : IN STD_LOGIC;
RESET_N : IN STD_LOGIC;
-- FPGA side
ENABLE_179_EARLY : IN STD_LOGIC;
REQUEST : IN STD_LOGIC;
ADDR_IN : IN STD_LOGIC_VECTOR(15 downto 0);
DATA_IN : IN STD_LOGIC_VECTOR(7 downto 0);
WRITE_IN : IN STD_LOGIC;
DATA_OUT : OUT STD_LOGIC_VECTOR(7 downto 0);
COMPLETE : OUT STD_LOGIC;
-- 6502 side
BUS_DATA_IN : IN STD_LOGIC_VECTOR(7 downto 0);
BUS_PHI1 : OUT STD_LOGIC;
BUS_PHI2 : OUT STD_LOGIC;
BUS_SUBCYCLE : OUT STD_LOGIC_VECTOR(3 downto 0);
BUS_ADDR_OUT : OUT STD_LOGIC_VECTOR(15 downto 0);
BUS_ADDR_OE : OUT STD_LOGIC;
BUS_DATA_OUT : OUT STD_LOGIC_VECTOR(7 downto 0);
BUS_DATA_OE : OUT STD_LOGIC;
BUS_WRITE_N : OUT STD_LOGIC
);
END timing6502;
ARCHITECTURE vhdl OF timing6502 IS
signal state_next : std_logic_vector(3 downto 0);
signal state_reg : STD_LOGIC_VECTOR(3 DOWNTO 0);
signal odd_next : std_logic;
signal odd_reg : std_logic;
signal addr_next : std_logic_vector(15 downto 0);
signal addr_reg : std_logic_vector(15 downto 0);
signal addr_oe_next : std_logic;
signal addr_oe_reg : std_logic;
signal data_next : std_logic_vector(7 downto 0);
signal data_reg : std_logic_vector(7 downto 0);
signal data_oe_next : std_logic;
signal data_oe_reg : std_logic;
signal data_read_next : std_logic_vector(7 downto 0);
signal data_read_reg : std_logic_vector(7 downto 0);
signal phi1_next : std_logic;
signal phi1_reg : std_logic;
signal phi2_next : std_logic;
signal phi2_reg : std_logic;
signal write_n_next : std_logic;
signal write_n_reg : std_logic;
signal complete_next : std_logic;
signal complete_reg : std_logic;
BEGIN
-- regs
process(clk, reset_n)
begin
if (reset_n='0') then
state_reg <= (others=>'0');
odd_reg <= '0';
addr_reg <= (others=>'0');
addr_oe_reg <= '0';
data_reg <= (others=>'0');
data_read_reg <= (others=>'0');
data_oe_reg <= '0';
phi1_reg <= '0';
phi2_reg <= '0';
write_n_reg <= '1';
complete_reg <= '0';
elsif (clk'event and clk='1') then
state_reg <= state_next;
odd_reg <= odd_next;
addr_reg <= addr_next;
addr_oe_reg <= addr_oe_next;
data_reg <= data_next;
data_read_reg <= data_read_next;
data_oe_reg <= data_oe_next;
phi1_reg <= phi1_next;
phi2_reg <= phi2_next;
write_n_reg <= write_n_next;
complete_reg <= complete_next;
end if;
end process;
-- next state
process(enable_179_early, state_reg, odd_reg, phi1_reg, phi2_reg, request, addr_in, data_in, addr_reg, addr_oe_reg, data_reg, data_oe_reg, data_read_reg, bus_data_in, write_n_reg, write_in)
begin
state_next <= state_reg;
odd_next <= not(odd_reg);
phi1_next <= phi1_reg;
phi2_next <= phi2_reg;
addr_next <= addr_reg;
addr_oe_next <= addr_oe_reg;
data_next <= data_reg;
data_oe_next <= data_oe_reg;
complete_next <= '0';
data_read_next <= data_read_reg;
write_n_next <= write_n_reg;
if (enable_179_early = '1') then
state_next <= (others=>'0'); -- re-sync
odd_next <= '1';
end if;
if (odd_reg = '1' or cycle_length = 16) then
state_next <= std_logic_vector(unsigned(state_reg)+1);
end if;
if (request = '1') then
addr_next <= addr_in;
data_next <= data_in;
write_n_next <= not(write_in);
end if;
case state_reg is
when x"0" =>
phi1_next <= '1';
when x"1"=>
addr_oe_next <= '1';
when x"2"|x"3"|x"4"|x"5" =>
when x"6" =>
phi1_next <= '0';
when x"7" =>
when x"8" =>
phi2_next <= '1';
when x"9"|x"a" =>
when x"b" =>
if (write_in = '1') then
data_oe_next <= '1';
end if;
when x"c" =>
when x"d" =>
complete_next <= '1';
data_read_next <= bus_data_in;
when x"e" =>
phi2_next <= '0';
when x"f" =>
addr_oe_next <= '0';
data_oe_next <= '0';
write_n_next <= '1';
end case;
end process;
-- outputs
BUS_SUBCYCLE <= state_reg;
BUS_PHI1 <= phi1_reg;
BUS_PHI2 <= phi2_reg;
BUS_ADDR_OUT <= addr_reg;
BUS_ADDR_OE <= addr_oe_reg;
BUS_DATA_OUT <= data_reg;
BUS_DATA_OE <= data_oe_reg;
BUS_WRITE_N <= write_n_reg;
DATA_OUT <= data_read_reg;
COMPLETE <= complete_reg;
END vhdl;
de1/atari800core_de1.vhd
signal pbi_addr : std_logic_vector(15 downto 0);
signal enable_179_early : std_logic;
-- scandoubler
signal half_scandouble_enable_reg : std_logic;
signal half_scandouble_enable_next : std_logic;
......
gpio_enable => SW(4),
pot_reset => pot_reset,
pbi_write_enable => pbi_write_enable,
enable_179_early => enable_179_early,
cart_request => cart_request,
cart_complete => cart_request_complete,
cart_data_read => cart_data,
......
POT_IN => POT_IN,
POT_RESET => POT_RESET,
ENABLE_179_EARLY => ENABLE_179_EARLY,
PBI_ADDR => PBI_ADDR,
PBI_WRITE_ENABLE => PBI_WRITE_ENABLE,
PBI_SNOOP_DATA => open,
de1/gpio.vhd
SIO_OUT : IN STD_LOGIC;
-- cartridge
enable_179_early : in std_logic;
pbi_addr_out : in std_logic_vector(15 downto 0);
pbi_write_enable : in std_logic;
cart_data_read : out std_logic_vector(7 downto 0);
......
signal trig_in_async : std_logic_vector(3 downto 0);
signal trig_in_sync : std_logic_vector(3 downto 0);
signal read_write_n : std_logic;
signal cart_data_read_async : std_logic_vector(7 downto 0);
signal bus_data_in : std_logic_vector(7 downto 0);
signal bus_data_out : std_logic_vector(7 downto 0);
signal bus_data_oe : std_logic;
signal bus_addr_out : std_logic_vector(15 downto 0);
signal bus_addr_oe : std_logic;
signal bus_write_n : std_logic;
signal phi2 : std_logic;
signal rd4_async : std_logic;
signal rd5_async : std_logic;
signal cart_complete_early : std_logic;
signal read_write_next : std_logic;
signal read_write_reg : std_logic;
signal keyboard_response_async : std_logic_vector(1 downto 0);
signal keyboard_response_gpio : std_logic_vector(1 downto 0);
......
GPIO_1_DIR_OUT(0) <= gpio_enable and not(keyboard_scan(0)); -- keyboard scan 0
-- cart
GPIO_0_DIR_OUT(35) <= '0'; -- clock - TODO
GPIO_0_OUT(35) <= '0'; -- clock - TODO
GPIO_0_DIR_OUT(35) <= '1';
GPIO_0_OUT(35) <= phi2;
GPIO_0_DIR_OUT(34) <= gpio_enable;
GPIO_0_OUT(34) <= read_write_n;
GPIO_0_DIR_OUT(33) <= gpio_enable;
GPIO_0_OUT(33) <= pbi_addr_out(10);
GPIO_0_DIR_OUT(32) <= gpio_enable;
GPIO_0_OUT(32) <= pbi_addr_out(11);
GPIO_0_DIR_OUT(31) <= gpio_enable and pbi_write_enable; -- d7
GPIO_0_OUT(31) <= cart_data_write(7); -- d7
GPIO_0_DIR_OUT(30) <= gpio_enable and pbi_write_enable; -- d3
GPIO_0_OUT(30) <= cart_data_write(3); -- d3
GPIO_0_DIR_OUT(29) <= gpio_enable;
GPIO_0_OUT(29) <= pbi_addr_out(12);
GPIO_0_DIR_OUT(28) <= gpio_enable;
GPIO_0_OUT(28) <= pbi_addr_out(9);
GPIO_0_DIR_OUT(27) <= gpio_enable;
GPIO_0_OUT(27) <= pbi_addr_out(8);
GPIO_0_DIR_OUT(26) <= gpio_enable;
GPIO_0_OUT(26) <= pbi_addr_out(7);
GPIO_0_DIR_OUT(25) <= gpio_enable;
GPIO_0_OUT(25) <= pbi_addr_out(6);
GPIO_0_DIR_OUT(24) <= gpio_enable;
GPIO_0_OUT(24) <= pbi_addr_out(5);
GPIO_0_DIR_OUT(23) <= gpio_enable;
GPIO_0_OUT(23) <= pbi_addr_out(4);
GPIO_0_OUT(34) <= bus_write_n;
GPIO_0_DIR_OUT(33) <= gpio_enable and bus_addr_oe;
GPIO_0_OUT(33) <= bus_addr_out(10);
GPIO_0_DIR_OUT(32) <= gpio_enable and bus_addr_oe;
GPIO_0_OUT(32) <= bus_addr_out(11);
GPIO_0_DIR_OUT(31) <= gpio_enable and bus_data_oe; -- d7
GPIO_0_OUT(31) <= bus_data_out(7); -- d7
GPIO_0_DIR_OUT(30) <= gpio_enable and bus_data_oe; -- d3
GPIO_0_OUT(30) <= bus_data_out(3); -- d3
GPIO_0_DIR_OUT(29) <= gpio_enable and bus_addr_oe;
GPIO_0_OUT(29) <= bus_addr_out(12);
GPIO_0_DIR_OUT(28) <= gpio_enable and bus_addr_oe;
GPIO_0_OUT(28) <= bus_addr_out(9);
GPIO_0_DIR_OUT(27) <= gpio_enable and bus_addr_oe;
GPIO_0_OUT(27) <= bus_addr_out(8);
GPIO_0_DIR_OUT(26) <= gpio_enable and bus_addr_oe;
GPIO_0_OUT(26) <= bus_addr_out(7);
GPIO_0_DIR_OUT(25) <= gpio_enable and bus_addr_oe;
GPIO_0_OUT(25) <= bus_addr_out(6);
GPIO_0_DIR_OUT(24) <= gpio_enable and bus_addr_oe;
GPIO_0_OUT(24) <= bus_addr_out(5);
GPIO_0_DIR_OUT(23) <= gpio_enable and bus_addr_oe;
GPIO_0_OUT(23) <= bus_addr_out(4);
GPIO_0_DIR_OUT(22) <= '0'; -- RD4 rom present
GPIO_0_OUT(22) <= '0'; -- RD4 rom present
GPIO_0_DIR_OUT(21) <= gpio_enable;
GPIO_0_OUT(21) <= S4_n;
GPIO_0_DIR_OUT(20) <= gpio_enable;
GPIO_0_OUT(20) <= pbi_addr_out(3);
GPIO_0_DIR_OUT(19) <= gpio_enable;
GPIO_0_OUT(19) <= pbi_addr_out(2);
GPIO_0_DIR_OUT(18) <= gpio_enable;
GPIO_0_OUT(18) <= pbi_addr_out(1);
GPIO_0_DIR_OUT(17) <= gpio_enable;
GPIO_0_OUT(17) <= pbi_addr_out(0);
GPIO_0_DIR_OUT(16) <= gpio_enable and pbi_write_enable; -- d4
GPIO_0_OUT(16) <= cart_data_write(4); -- d4
GPIO_0_DIR_OUT(15) <= gpio_enable and pbi_write_enable; -- d5
GPIO_0_OUT(15) <= cart_data_write(5); -- d5
GPIO_0_DIR_OUT(14) <= gpio_enable and pbi_write_enable; -- d2
GPIO_0_OUT(14) <= cart_data_write(2); -- d2
GPIO_0_DIR_OUT(13) <= gpio_enable and pbi_write_enable; -- d1
GPIO_0_OUT(13) <= cart_data_write(1); -- d1
GPIO_0_DIR_OUT(12) <= gpio_enable and pbi_write_enable; -- d0
GPIO_0_OUT(12) <= cart_data_write(0); -- d0
GPIO_0_DIR_OUT(11) <= gpio_enable and pbi_write_enable; -- d6
GPIO_0_OUT(11) <= cart_data_write(6); -- d6
GPIO_0_DIR_OUT(20) <= gpio_enable and bus_addr_oe;
GPIO_0_OUT(20) <= bus_addr_out(3);
GPIO_0_DIR_OUT(19) <= gpio_enable and bus_addr_oe;
GPIO_0_OUT(19) <= bus_addr_out(2);
GPIO_0_DIR_OUT(18) <= gpio_enable and bus_addr_oe;
GPIO_0_OUT(18) <= bus_addr_out(1);
GPIO_0_DIR_OUT(17) <= gpio_enable and bus_addr_oe;
GPIO_0_OUT(17) <= bus_addr_out(0);
GPIO_0_DIR_OUT(16) <= gpio_enable and bus_data_oe; -- d4
GPIO_0_OUT(16) <= bus_data_out(4); -- d4
GPIO_0_DIR_OUT(15) <= gpio_enable and bus_data_oe; -- d5
GPIO_0_OUT(15) <= bus_data_out(5); -- d5
GPIO_0_DIR_OUT(14) <= gpio_enable and bus_data_oe; -- d2
GPIO_0_OUT(14) <= bus_data_out(2); -- d2
GPIO_0_DIR_OUT(13) <= gpio_enable and bus_data_oe; -- d1
GPIO_0_OUT(13) <= bus_data_out(1); -- d1
GPIO_0_DIR_OUT(12) <= gpio_enable and bus_data_oe; -- d0
GPIO_0_OUT(12) <= bus_data_out(0); -- d0
GPIO_0_DIR_OUT(11) <= gpio_enable and bus_data_oe; -- d6
GPIO_0_OUT(11) <= bus_data_out(6); -- d6
GPIO_0_DIR_OUT(10) <= gpio_enable;
GPIO_0_OUT(10) <= S5_n;
GPIO_0_DIR_OUT(9) <= '0'; -- RD5 rom present
......
-- clock (not needed for rom?)
-- RD5 ROM present (in)
-- RD4 ROM present (in)
read_write_n <= read_write_reg;
process(clk)
begin
if (clk'event and clk='1') then
read_write_reg <= read_write_next;
end if;
end process;
process(pbi_write_enable, cart_request, cart_complete_early)
begin
read_write_next <= '1';
bus_adaptor : ENTITY work.timing6502
GENERIC MAP
(
CYCLE_LENGTH => cartridge_cycle_length
)
PORT MAP
(
CLK => clk,
RESET_N => reset_n,
if (pbi_write_enable = '1' and cart_request = '1') then
read_write_next <= '0';
end if;
-- FPGA side
ENABLE_179_EARLY =>enable_179_early,
if (cart_complete_early = '1') then
read_write_next <= '1';
end if;
end process;
REQUEST => cart_request,
ADDR_IN => pbi_addr_out,
DATA_IN => cart_data_write,
WRITE_IN => pbi_write_enable,
cart_delay2 : entity work.delay_line
generic map (COUNT=>cartridge_cycle_length-4)
port map(clk=>clk,sync_reset=>'0',data_in=>cart_request,enable=>'1',reset_n=>reset_n,data_out=>cart_complete_early);
DATA_OUT => cart_data_read,
COMPLETE => cart_complete,
-- 6502 side
BUS_DATA_IN => bus_data_in,
cart_delay : entity work.delay_line
generic map (COUNT=>cartridge_cycle_length-1)
port map(clk=>clk,sync_reset=>'0',data_in=>cart_request,enable=>'1',reset_n=>reset_n,data_out=>cart_complete);
BUS_PHI1 => open,
BUS_PHI2 => phi2,
BUS_SUBCYCLE => open,
BUS_ADDR_OUT => bus_addr_out,
BUS_ADDR_OE => bus_addr_oe,
BUS_DATA_OUT => bus_data_out,
BUS_DATA_OE => bus_data_oe,
BUS_WRITE_N => bus_write_n
);
rd4_async <= gpio_enable and GPIO_0_IN(22);
cart_rd4_synchronizer : synchronizer
port map (clk=>clk, raw=>rd4_async, sync=>rd4);
......
cart_rd5_synchronizer : synchronizer
port map (clk=>clk, raw=>rd5_async, sync=>rd5);
cart_data_read_async <= GPIO_0_IN(31)&GPIO_0_IN(11)&GPIO_0_IN(15)&GPIO_0_IN(16)&GPIO_0_IN(30)&GPIO_0_IN(14)&GPIO_0_IN(13)&GPIO_0_IN(12);
cart_data0_synchronizer : synchronizer
port map (clk=>clk, raw=>cart_data_read_async(0), sync=>cart_data_read(0));
cart_data1_synchronizer : synchronizer
port map (clk=>clk, raw=>cart_data_read_async(1), sync=>cart_data_read(1));
cart_data2_synchronizer : synchronizer
port map (clk=>clk, raw=>cart_data_read_async(2), sync=>cart_data_read(2));
cart_data3_synchronizer : synchronizer
port map (clk=>clk, raw=>cart_data_read_async(3), sync=>cart_data_read(3));
cart_data4_synchronizer : synchronizer
port map (clk=>clk, raw=>cart_data_read_async(4), sync=>cart_data_read(4));
cart_data5_synchronizer : synchronizer
port map (clk=>clk, raw=>cart_data_read_async(5), sync=>cart_data_read(5));
cart_data6_synchronizer : synchronizer
port map (clk=>clk, raw=>cart_data_read_async(6), sync=>cart_data_read(6));
cart_data7_synchronizer : synchronizer
port map (clk=>clk, raw=>cart_data_read_async(7), sync=>cart_data_read(7));
bus_data_in <= GPIO_0_IN(31)&GPIO_0_IN(11)&GPIO_0_IN(15)&GPIO_0_IN(16)&GPIO_0_IN(30)&GPIO_0_IN(14)&GPIO_0_IN(13)&GPIO_0_IN(12);
-- cart_data0_synchronizer : synchronizer
-- port map (clk=>clk, raw=>cart_data_read_async(0), sync=>cart_data_read(0));
-- cart_data1_synchronizer : synchronizer
-- port map (clk=>clk, raw=>cart_data_read_async(1), sync=>cart_data_read(1));
-- cart_data2_synchronizer : synchronizer
-- port map (clk=>clk, raw=>cart_data_read_async(2), sync=>cart_data_read(2));
-- cart_data3_synchronizer : synchronizer
-- port map (clk=>clk, raw=>cart_data_read_async(3), sync=>cart_data_read(3));
-- cart_data4_synchronizer : synchronizer
-- port map (clk=>clk, raw=>cart_data_read_async(4), sync=>cart_data_read(4));
-- cart_data5_synchronizer : synchronizer
-- port map (clk=>clk, raw=>cart_data_read_async(5), sync=>cart_data_read(5));
-- cart_data6_synchronizer : synchronizer
-- port map (clk=>clk, raw=>cart_data_read_async(6), sync=>cart_data_read(6));
-- cart_data7_synchronizer : synchronizer
-- port map (clk=>clk, raw=>cart_data_read_async(7), sync=>cart_data_read(7));
--GPIO_1(25) <= GPIO_1(29);

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