Revision 2
Added by markw over 11 years ago
| common/a8core/antic.vhdl | ||
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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USE ieee.math_real.ceil;
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USE ieee.math_real.log2;
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USE ieee.math_real.ceil;
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use IEEE.STD_LOGIC_MISC.all;
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ENTITY antic IS
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GENERIC
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(
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cycle_length : integer := 16; -- or 32...
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)
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cycle_length : integer := 16 -- or 32...
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);
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PORT
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(
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CLK : IN STD_LOGIC;
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| ... | ... | |
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signal colour_clock_selected : std_logic;
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signal colour_clock_selected_highres : std_logic;
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CONSTANT cycle_length_bits: integer = integer(ceil(log2(1.0*cycle_length)));
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constant cycle_length_bits: integer := integer(ceil(log2(real(cycle_length))));
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signal colour_clock_count_next : std_logic_vector(cycle_length_bits-1 downto 0);
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signal colour_clock_count_reg : std_logic_vector(cycle_length_bits-1 downto 0);
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signal colour_clock_count_reg_topthree : std_logic_vector(2 downto 0);
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signal memory_ready_both : std_logic;
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| ... | ... | |
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--enable_colour_clock_div : enable_divider
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--generic map (COUNT=>7)
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--port map(clk=>clk,reset_n=>reset_n,enable_in=>'1',enable_out=>enable_colour_clock);
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process(colour_clock_count_reg, ANTIC_ENABLE_179)
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colour_clock_count_reg_topthree <= colour_clock_count_reg(cycle_length_bits-1 downto cycle_length_bits-3);
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process(colour_clock_count_reg, colour_clock_count_reg_topthree, ANTIC_ENABLE_179)
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begin
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colour_clock_half_x <= '0';
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colour_clock_1x<='0';
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| ... | ... | |
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colour_clock_8x <= '1';
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if (or_reduce(colour_clock_count_reg( cycle_count_bits-4 downto 0) = '0') then
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case colour_clock_count_reg(cycle_count_bits-1 downto cycle_count_bits-3) is
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if (or_reduce(colour_clock_count_reg( cycle_length_bits-4 downto 0)) = '0') then
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case colour_clock_count_reg_topthree is
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when "000" =>
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colour_clock_half_x <= '1';
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colour_clock_1x <= '1';
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| common/a8core/shared_enable.vhdl | ||
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ENTITY shared_enable IS
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GENERIC
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(
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cycle_length : integer := 16; -- or 32...
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)
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cycle_length : integer := 16 -- or 32...
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);
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PORT
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(
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CLK : IN STD_LOGIC;
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Also available in: Unified diff
Make these generic to support Replay (28MHz) and the rest (57MHz)