EclaireXL

<?xml version="1.0" encoding="UTF-8" ?>

<!DOCTYPE pinplan>

<pinplan intended_family="Cyclone III" variation_name="pll_pal_pre" megafunction_name="ALTPLL" specifies="all_ports">

<global>

<pin name="inclk0" direction="input" scope="external" source="clock" />

<pin name="c0" direction="output" scope="external" source="clock" />

<pin name="locked" direction="output" scope="external" />

</global>

</pinplan>

-- megafunction wizard: %ALTPLL%

-- GENERATION: STANDARD

-- VERSION: WM1.0

-- MODULE: altpll

-- ============================================================

-- File Name: pll_pal_pre.vhd

-- Megafunction Name(s):

-- altpll

--

-- Simulation Library Files(s):

-- altera_mf

-- ============================================================

-- ************************************************************

-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!

--

-- 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition

-- ************************************************************

--Copyright (C) 1991-2013 Altera Corporation

--Your use of Altera Corporation's design tools, logic functions

--and other software and tools, and its AMPP partner logic

--functions, and any output files from any of the foregoing

--(including device programming or simulation files), and any

--associated documentation or information are expressly subject

--to the terms and conditions of the Altera Program License

--Subscription Agreement, Altera MegaCore Function License

--Agreement, or other applicable license agreement, including,

--without limitation, that your use is for the sole purpose of

--programming logic devices manufactured by Altera and sold by

--Altera or its authorized distributors. Please refer to the

--applicable agreement for further details.

LIBRARY ieee;

USE ieee.std_logic_1164.all;

LIBRARY altera_mf;

USE altera_mf.all;

ENTITY pll_pal_pre IS

PORT

(

inclk0 : IN STD_LOGIC := '0';

c0 : OUT STD_LOGIC ;

locked : OUT STD_LOGIC

);

END pll_pal_pre;

ARCHITECTURE SYN OF pll_pal_pre IS

SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0);

SIGNAL sub_wire1 : STD_LOGIC ;

SIGNAL sub_wire2 : STD_LOGIC ;

SIGNAL sub_wire3 : STD_LOGIC ;

SIGNAL sub_wire4 : STD_LOGIC_VECTOR (1 DOWNTO 0);

SIGNAL sub_wire5_bv : BIT_VECTOR (0 DOWNTO 0);

SIGNAL sub_wire5 : STD_LOGIC_VECTOR (0 DOWNTO 0);

COMPONENT altpll

GENERIC (

bandwidth_type : STRING;

clk0_divide_by : NATURAL;

clk0_duty_cycle : NATURAL;

clk0_multiply_by : NATURAL;

clk0_phase_shift : STRING;

compensate_clock : STRING;

inclk0_input_frequency : NATURAL;

intended_device_family : STRING;

lpm_hint : STRING;

lpm_type : STRING;

operation_mode : STRING;

pll_type : STRING;

port_activeclock : STRING;

port_areset : STRING;

port_clkbad0 : STRING;

port_clkbad1 : STRING;

port_clkloss : STRING;

port_clkswitch : STRING;

port_configupdate : STRING;

port_fbin : STRING;

port_inclk0 : STRING;

port_inclk1 : STRING;

port_locked : STRING;

port_pfdena : STRING;

port_phasecounterselect : STRING;

port_phasedone : STRING;

port_phasestep : STRING;

port_phaseupdown : STRING;

port_pllena : STRING;

port_scanaclr : STRING;

port_scanclk : STRING;

port_scanclkena : STRING;

port_scandata : STRING;

port_scandataout : STRING;

port_scandone : STRING;

port_scanread : STRING;

port_scanwrite : STRING;

port_clk0 : STRING;

port_clk1 : STRING;

port_clk2 : STRING;

port_clk3 : STRING;

port_clk4 : STRING;

port_clk5 : STRING;

port_clkena0 : STRING;

port_clkena1 : STRING;

port_clkena2 : STRING;

port_clkena3 : STRING;

port_clkena4 : STRING;

port_clkena5 : STRING;

port_extclk0 : STRING;

port_extclk1 : STRING;

port_extclk2 : STRING;

port_extclk3 : STRING;

self_reset_on_loss_lock : STRING;

width_clock : NATURAL

);

PORT (

clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);

inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);

locked : OUT STD_LOGIC

);

END COMPONENT;

BEGIN

sub_wire5_bv(0 DOWNTO 0) <= "0";

sub_wire5 <= To_stdlogicvector(sub_wire5_bv);

sub_wire1 <= sub_wire0(0);

c0 <= sub_wire1;

locked <= sub_wire2;

sub_wire3 <= inclk0;

sub_wire4 <= sub_wire5(0 DOWNTO 0) & sub_wire3;

altpll_component : altpll

GENERIC MAP (

bandwidth_type => "LOW",

clk0_divide_by => 27,

clk0_duty_cycle => 50,

clk0_multiply_by => 20,

clk0_phase_shift => "0",

compensate_clock => "CLK0",

inclk0_input_frequency => 37037,

intended_device_family => "Cyclone III",

lpm_hint => "CBX_MODULE_PREFIX=pll_pal_pre",

lpm_type => "altpll",

operation_mode => "NORMAL",

pll_type => "AUTO",

port_activeclock => "PORT_UNUSED",

port_areset => "PORT_UNUSED",

port_clkbad0 => "PORT_UNUSED",

port_clkbad1 => "PORT_UNUSED",

port_clkloss => "PORT_UNUSED",

port_clkswitch => "PORT_UNUSED",

port_configupdate => "PORT_UNUSED",

port_fbin => "PORT_UNUSED",

port_inclk0 => "PORT_USED",

port_inclk1 => "PORT_UNUSED",

port_locked => "PORT_USED",

port_pfdena => "PORT_UNUSED",

port_phasecounterselect => "PORT_UNUSED",

port_phasedone => "PORT_UNUSED",

port_phasestep => "PORT_UNUSED",

port_phaseupdown => "PORT_UNUSED",

port_pllena => "PORT_UNUSED",

port_scanaclr => "PORT_UNUSED",

port_scanclk => "PORT_UNUSED",

port_scanclkena => "PORT_UNUSED",

port_scandata => "PORT_UNUSED",

port_scandataout => "PORT_UNUSED",

port_scandone => "PORT_UNUSED",

port_scanread => "PORT_UNUSED",

port_scanwrite => "PORT_UNUSED",

port_clk0 => "PORT_USED",

port_clk1 => "PORT_UNUSED",

port_clk2 => "PORT_UNUSED",

port_clk3 => "PORT_UNUSED",

port_clk4 => "PORT_UNUSED",

port_clk5 => "PORT_UNUSED",

port_clkena0 => "PORT_UNUSED",

port_clkena1 => "PORT_UNUSED",

port_clkena2 => "PORT_UNUSED",

port_clkena3 => "PORT_UNUSED",

port_clkena4 => "PORT_UNUSED",

port_clkena5 => "PORT_UNUSED",

port_extclk0 => "PORT_UNUSED",

port_extclk1 => "PORT_UNUSED",

port_extclk2 => "PORT_UNUSED",

port_extclk3 => "PORT_UNUSED",

self_reset_on_loss_lock => "OFF",

width_clock => 5

)

PORT MAP (

inclk => sub_wire4,

clk => sub_wire0,

locked => sub_wire2

);

END SYN;

-- ============================================================

-- CNX file retrieval info

-- ============================================================

-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"

-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"

-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"

-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"

-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"

-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "0"

-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "1"

-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"

-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"

-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"

-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"

-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"

-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"

-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"

-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"

-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"

-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "27"

-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"

-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "20.000000"

-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"

-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"

-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"

-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"

-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"

-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"

-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"

-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"

-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"

-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"

-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"

-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"

-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"

-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"

-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"

-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"

-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"

-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"

-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"

-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"

-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"

-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"

-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "20"

-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"

-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000"

-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"

-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"

-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"

-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"

-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"

-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"

-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"

-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"

-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"

-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"

-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"

-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"

-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"

-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"

-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"

-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"

-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"

-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll_pal_pre.mif"

-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"

-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"

-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"

-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"

-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"

-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"

-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"

-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"

-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"

-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"

-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"

-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"

-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"

-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"

-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"

-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"

-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"

-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"

-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all

-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "LOW"

-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "27"

-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"

-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "20"

-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"

-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"

-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"

-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"

-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"

-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"

-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"

-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"

-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"

-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"

-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"

-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"

-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"

-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"

-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"

-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"

-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"

-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"

-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"

-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"

-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"

-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"

-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"

-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"

-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"

-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"

-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"

-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"

-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"

-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"

-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"

-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"

-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"

-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"

-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"

-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"

-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"

-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"

-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"

-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"

-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"

-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"

-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"

-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"

-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"

-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"

-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"

-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"

-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"

-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"

-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"

-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"

-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"

-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"

-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"

-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0

-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0

-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0

-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0

-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_pal_pre.vhd TRUE

-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_pal_pre.ppf TRUE

-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_pal_pre.inc FALSE

-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_pal_pre.cmp TRUE

-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_pal_pre.bsf FALSE

-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_pal_pre_inst.vhd FALSE

-- Retrieval info: LIB_FILE: altera_mf

-- Retrieval info: CBX_MODULE_PREFIX: ON

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

use ieee.numeric_std.all;

use ieee.std_logic_textio.all;

library std_developerskit ; -- used for to_string

-- use std_developerskit.std_iopak.all;

entity data_io_tb is

end;

architecture rtl of data_io_tb is

constant CLK_A_PERIOD : time := 1 us / (1.79*32);

signal CLK_A : std_logic;

signal reset_n : std_logic;

signal spi_clk : std_logic;

signal spi_ss_io : std_logic_vector(1 downto 0);

signal spi_miso : std_logic;

signal spi_mosi : std_logic;

signal request : std_logic;

signal write : std_logic;

signal ready : std_logic;

signal sector : std_logic_vector(23 downto 0);

signal addr : std_logic_vector(8 downto 0);

signal data_out : std_logic_vector(7 downto 0);

signal data_in : std_logic_vector(7 downto 0);

signal wr_en : std_logic;

signal spi_enable : std_logic;

signal spi_tx_data : std_logic_vector(7 downto 0);

signal spi_rx_data : std_logic_vector(7 downto 0);

signal spi_busy : std_logic;

signal spi_addr : integer;

begin

p_clk_gen_a : process

begin

clk_a <= '1';

wait for CLK_A_PERIOD/2;

clk_a <= '0';

wait for CLK_A_PERIOD - (CLK_A_PERIOD/2 );

end process;

reset_n <= '0', '1' after 1000ns;

spi_master1 : entity work.spi_master

generic map(slaves=>2,d_width=>8)

port map (clock=>clk_a,reset_n=>reset_n,enable=>spi_enable,cpol=>'0',cpha=>'0',cont=>'0',clk_div=>4,addr=>spi_addr,

tx_data=>spi_tx_data, miso=>spi_miso,sclk=>spi_clk,ss_n=>spi_ss_io,mosi=>spi_mosi,

rx_data=>spi_rx_data,busy=>spi_busy);

spi_fake : process

variable type_conv : std_logic_vector(8 downto 0);

begin

spi_enable <= '0';

spi_addr <= 0;

wait for 1500us;

spi_tx_data <= x"50";

spi_enable <= '1';

wait for CLK_A_PERIOD*2;

spi_tx_data <= x"FF";

spi_enable <= '0';

wait until spi_busy='0';

for i in 0 to 3 loop

spi_tx_data <= x"ff";

spi_enable <= '1';

wait for CLK_A_PERIOD*2;

spi_tx_data <= x"FF";

spi_enable <= '0';

wait until spi_busy='0';

end loop;

spi_addr <= 1;

spi_tx_data <= x"ff";

spi_enable <= '1';

wait for CLK_A_PERIOD*2;

spi_tx_data <= x"FF";

spi_enable <= '0';

wait until spi_busy='0';

spi_addr <= 0;

wait for 20us;

spi_tx_data <= x"51";

spi_enable <= '1';

wait for CLK_A_PERIOD*2;

spi_tx_data <= x"FF";

spi_enable <= '0';

wait until spi_busy='0';

for i in 0 to 511 loop

type_conv := std_logic_vector(to_unsigned(i,9));

spi_tx_data <= type_conv(7 downto 0);

spi_enable <= '1';

wait for CLK_A_PERIOD*4;

spi_tx_data <= x"FF";

spi_enable <= '0';

wait until spi_busy='0';

end loop;

spi_tx_data <= x"ff";

spi_enable <= '1';

wait for CLK_A_PERIOD*2;

spi_tx_data <= x"FF";

spi_enable <= '0';

wait until spi_busy='0';

-- NEXT

spi_addr <= 1;

spi_tx_data <= x"ff";

spi_enable <= '1';

wait for CLK_A_PERIOD*2;

spi_tx_data <= x"FF";

spi_enable <= '0';

wait until spi_busy='0';

spi_addr <= 0;

wait for 20us;

spi_tx_data <= x"50";

spi_enable <= '1';

wait for CLK_A_PERIOD*2;

spi_tx_data <= x"FF";

spi_enable <= '0';

wait until spi_busy='0';

for i in 0 to 3 loop

spi_tx_data <= x"ff";

spi_enable <= '1';

wait for CLK_A_PERIOD*2;

spi_tx_data <= x"FF";

spi_enable <= '0';

wait until spi_busy='0';

end loop;

spi_addr <= 1;

spi_tx_data <= x"ff";

spi_enable <= '1';

wait for CLK_A_PERIOD*2;

spi_tx_data <= x"FF";

spi_enable <= '0';

wait until spi_busy='0';

spi_addr <= 0;

wait for 20us;

spi_tx_data <= x"51";

spi_enable <= '1';

wait for CLK_A_PERIOD*2;

spi_tx_data <= x"FF";

spi_enable <= '0';

wait until spi_busy='0';

for i in 0 to 511 loop

type_conv := std_logic_vector(to_unsigned(511-i,9));

spi_tx_data <= type_conv(7 downto 0);

spi_enable <= '1';

wait for CLK_A_PERIOD*4;

spi_tx_data <= x"FF";

spi_enable <= '0';

wait until spi_busy='0';

end loop;

spi_tx_data <= x"ff";

spi_enable <= '1';

wait for CLK_A_PERIOD*2;

spi_tx_data <= x"FF";

spi_enable <= '0';

wait until spi_busy='0';

-- NEXT - WRITE...

spi_addr <= 1;

spi_tx_data <= x"ff";

spi_enable <= '1';

wait for CLK_A_PERIOD*2;

spi_tx_data <= x"FF";

spi_enable <= '0';

wait until spi_busy='0';

spi_addr <= 0;

wait for 20us;

spi_tx_data <= x"50";

spi_enable <= '1';

wait for CLK_A_PERIOD*2;

spi_tx_data <= x"FF";

spi_enable <= '0';

wait until spi_busy='0';

for i in 0 to 3 loop

spi_tx_data <= x"ff";

spi_enable <= '1';

wait for CLK_A_PERIOD*2;

spi_tx_data <= x"FF";

spi_enable <= '0';

wait until spi_busy='0';

end loop;

spi_addr <= 1;

spi_tx_data <= x"ff";

spi_enable <= '1';

wait for CLK_A_PERIOD*2;

spi_tx_data <= x"FF";

spi_enable <= '0';

wait until spi_busy='0';

spi_addr <= 0;

wait for 20us;

spi_tx_data <= x"52";

spi_enable <= '1';

wait for CLK_A_PERIOD*2;

spi_tx_data <= x"FF";

spi_enable <= '0';

wait until spi_busy='0';

for i in 0 to 511 loop

spi_tx_data <= x"FF";

spi_enable <= '1';

wait for CLK_A_PERIOD*4;

spi_tx_data <= x"FF";

spi_enable <= '0';

wait until spi_busy='0';

end loop;

spi_tx_data <= x"ff";

spi_enable <= '1';

wait for CLK_A_PERIOD*2;

spi_tx_data <= x"FF";

spi_enable <= '0';

wait until spi_busy='0';

wait for 100ms;

end process;

spi_request : process

begin

sector <= (others=>'0');

request <= '0';

write <= '0';

wait for 1500us;

sector <= x"123456";

request <= '1';

wait until ready = '1';

request <= '0';

wait for CLK_A_PERIOD*20;

wait until ready = '0';

sector <= x"654321";

request <= '1';

wait until ready = '1';

request <= '0';

wait for CLK_A_PERIOD*20;

wait until ready = '0';

sector <= x"111111";

write <= '1';

wait until ready = '1';

write <= '0';

wait for CLK_A_PERIOD*20;

wait until ready = '0';

wait for 100ms;

end process;

ram : entity work.generic_ram_infer

generic map

(

ADDRESS_WIDTH => 9,

SPACE => 512,

DATA_WIDTH => 8

)

PORT map

(

clock => spi_clk,

data => data_out,

address => addr,

we => wr_en,

q => data_in

);

data_io : entity work.data_io

PORT MAP

(

CLK => spi_clk,

RESET_n =>reset_n,

-- SPI connection - up to upstream to make miso 'Z' on ss_io going high

SPI_CLK => spi_clk,

SPI_SS_IO => spi_ss_io(0),

SPI_MISO => spi_miso,

SPI_MOSI => spi_mosi,

-- Sector access request

read_request => request,

write_request => write,

sector => sector,

ready => ready,

-- DMA to RAM

ADDR => addr,

DATA_OUT => data_out,

DATA_IN => data_in,

WR_EN => wr_en

);

end rtl;

<sld_project_info>

<project>

<hash md5_digest_80b="7d0f11bf891bc55d775e"/>

</project>

<file_info/>

<hub_info ir_width="8" node_count="1"/>

<node_info>

<node hpath="sld_signaltap:auto_signaltap_0" instance_id="0" mfg_id="110" node_id="0" sld_node_info="0x30006E00" version="6">

<parameters>

<parameter name="lpm_type" type="string" value="sld_signaltap"/>

<parameter name="sld_node_info" type="unknown" value="805334528"/>

<parameter name="SLD_IP_VERSION" type="dec" value="6"/>

<parameter name="SLD_IP_MINOR_VERSION" type="dec" value="0"/>

<parameter name="SLD_COMMON_IP_VERSION" type="dec" value="0"/>

<parameter name="sld_data_bits" type="unknown" value="119"/>

<parameter name="sld_trigger_bits" type="unknown" value="119"/>

<parameter name="SLD_NODE_CRC_BITS" type="dec" value="32"/>

<parameter name="sld_node_crc_hiword" type="unknown" value="37736"/>

<parameter name="sld_node_crc_loword" type="unknown" value="25945"/>

<parameter name="SLD_INCREMENTAL_ROUTING" type="dec" value="0"/>

<parameter name="sld_sample_depth" type="unknown" value="2048"/>

<parameter name="sld_segment_size" type="unknown" value="2048"/>

<parameter name="SLD_RAM_BLOCK_TYPE" type="string" value="AUTO"/>

<parameter name="sld_state_bits" type="unknown" value="11"/>

<parameter name="sld_buffer_full_stop" type="unknown" value="1"/>

<parameter name="SLD_MEM_ADDRESS_BITS" type="dec" value="7"/>

<parameter name="SLD_DATA_BIT_CNTR_BITS" type="dec" value="4"/>

<parameter name="sld_trigger_level" type="unknown" value="1"/>

<parameter name="sld_trigger_in_enabled" type="unknown" value="0"/>

<parameter name="sld_advanced_trigger_entity" type="unknown" value="basic,1,"/>

<parameter name="sld_trigger_level_pipeline" type="unknown" value="1"/>

<parameter name="sld_enable_advanced_trigger" type="unknown" value="0"/>

<parameter name="SLD_ADVANCED_TRIGGER_1" type="string" value="NONE"/>

<parameter name="SLD_ADVANCED_TRIGGER_2" type="string" value="NONE"/>

<parameter name="SLD_ADVANCED_TRIGGER_3" type="string" value="NONE"/>

<parameter name="SLD_ADVANCED_TRIGGER_4" type="string" value="NONE"/>

<parameter name="SLD_ADVANCED_TRIGGER_5" type="string" value="NONE"/>

<parameter name="SLD_ADVANCED_TRIGGER_6" type="string" value="NONE"/>

<parameter name="SLD_ADVANCED_TRIGGER_7" type="string" value="NONE"/>

<parameter name="SLD_ADVANCED_TRIGGER_8" type="string" value="NONE"/>

<parameter name="SLD_ADVANCED_TRIGGER_9" type="string" value="NONE"/>

<parameter name="SLD_ADVANCED_TRIGGER_10" type="string" value="NONE"/>

<parameter name="sld_inversion_mask_length" type="unknown" value="382"/>

<parameter name="sld_inversion_mask" type="unknown" value="0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"/>

<parameter name="sld_power_up_trigger" type="unknown" value="0"/>

<parameter name="SLD_STATE_FLOW_MGR_ENTITY" type="string" value="state_flow_mgr_entity.vhd"/>

<parameter name="sld_state_flow_use_generated" type="unknown" value="0"/>

<parameter name="sld_current_resource_width" type="unknown" value="1"/>

<parameter name="sld_attribute_mem_mode" type="unknown" value="OFF"/>

<parameter name="SLD_STORAGE_QUALIFIER_BITS" type="dec" value="1"/>

<parameter name="SLD_STORAGE_QUALIFIER_GAP_RECORD" type="dec" value="0"/>

<parameter name="SLD_STORAGE_QUALIFIER_MODE" type="string" value="OFF"/>

<parameter name="SLD_STORAGE_QUALIFIER_ENABLE_ADVANCED_CONDITION" type="dec" value="0"/>

<parameter name="sld_storage_qualifier_inversion_mask_length" type="unknown" value="0"/>

<parameter name="SLD_STORAGE_QUALIFIER_ADVANCED_CONDITION_ENTITY" type="string" value="basic"/>

<parameter name="SLD_STORAGE_QUALIFIER_PIPELINE" type="dec" value="0"/>

</parameters>

<inputs/>

<outputs/>

</node>

</node_info>

</sld_project_info>

# -------------------------------------------------------------------------- #

#

# Copyright (C) 1991-2012 Altera Corporation

# Your use of Altera Corporation's design tools, logic functions

# and other software and tools, and its AMPP partner logic

# functions, and any output files from any of the foregoing

# (including device programming or simulation files), and any

# associated documentation or information are expressly subject

# to the terms and conditions of the Altera Program License

# Subscription Agreement, Altera MegaCore Function License

# Agreement, or other applicable license agreement, including,

# without limitation, that your use is for the sole purpose of

# programming logic devices manufactured by Altera and sold by

# Altera or its authorized distributors. Please refer to the

# applicable agreement for further details.

#

# -------------------------------------------------------------------------- #

#

# Quartus II 64-Bit

# Version 12.1 Build 243 01/31/2013 Service Pack 1 SJ Web Edition

# Date created = 13:58:38 April 11, 2013

#

# -------------------------------------------------------------------------- #

QUARTUS_VERSION = "12.1"

DATE = "13:58:38 April 11, 2013"

# Revisions

PROJECT_REVISION = "atari800core"

# Copyright (C) 1991-2007 Altera Corporation

# Your use of Altera Corporation's design tools, logic functions

# and other software and tools, and its AMPP partner logic

# functions, and any output files from any of the foregoing

# (including device programming or simulation files), and any

# associated documentation or information are expressly subject

# to the terms and conditions of the Altera Program License

# Subscription Agreement, Altera MegaCore Function License

# Agreement, or other applicable license agreement, including,

# without limitation, that your use is for the sole purpose of

# programming logic devices manufactured by Altera and sold by

# Altera or its authorized distributors. Please refer to the

# applicable agreement for further details.

# The default values for assignments are stored in the file

# minimig_de1_assignment_defaults.qdf

# If this file doesn't exist, and for assignments not listed, see file

# assignment_defaults.qdf

# Altera recommends that you do not modify this file. This

# file is updated automatically by the Quartus II software

# and any changes you make may be lost or overwritten.

set_global_assignment -name FAMILY "Cyclone III"

set_global_assignment -name DEVICE EP3C25E144C8

set_global_assignment -name TOP_LEVEL_ENTITY atari800core_mist

set_global_assignment -name ORIGINAL_QUARTUS_VERSION 7.2

set_global_assignment -name PROJECT_CREATION_TIME_DATE "22:27:29 OCTOBER 30, 2007"

set_global_assignment -name LAST_QUARTUS_VERSION "12.1 SP1.33"

set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_palace

set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144

set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR"

set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"

set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"

set_global_assignment -name FITTER_EFFORT "AUTO FIT"

set_global_assignment -name STRATIX_CONFIGURATION_DEVICE EPCS4

set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"

set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "AS INPUT TRI-STATED"

set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL"

set_global_assignment -name GENERATE_RBF_FILE ON

set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON

set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"

set_location_assignment PIN_7 -to LED

set_location_assignment PIN_22 -to CLOCK_50[0]

set_location_assignment PIN_23 -to CLOCK_50[1]

set_location_assignment PIN_128 -to CLOCK_32[0]

set_location_assignment PIN_129 -to CLOCK_32[1]

set_location_assignment PIN_54 -to CLOCK_27[0]

set_location_assignment PIN_55 -to CLOCK_27[1]

set_location_assignment PIN_144 -to VGA_R[5]

set_location_assignment PIN_143 -to VGA_R[4]

set_location_assignment PIN_142 -to VGA_R[3]

set_location_assignment PIN_141 -to VGA_R[2]

set_location_assignment PIN_137 -to VGA_R[1]

set_location_assignment PIN_135 -to VGA_R[0]

set_location_assignment PIN_133 -to VGA_B[5]

set_location_assignment PIN_132 -to VGA_B[4]

set_location_assignment PIN_125 -to VGA_B[3]

set_location_assignment PIN_121 -to VGA_B[2]

set_location_assignment PIN_120 -to VGA_B[1]

set_location_assignment PIN_115 -to VGA_B[0]

set_location_assignment PIN_114 -to VGA_G[5]

set_location_assignment PIN_113 -to VGA_G[4]

set_location_assignment PIN_112 -to VGA_G[3]

set_location_assignment PIN_111 -to VGA_G[2]

set_location_assignment PIN_110 -to VGA_G[1]

set_location_assignment PIN_106 -to VGA_G[0]

set_location_assignment PIN_136 -to VGA_VS

set_location_assignment PIN_119 -to VGA_HS

set_location_assignment PIN_65 -to AUDIO_L

set_location_assignment PIN_80 -to AUDIO_R

set_location_assignment PIN_46 -to UART_TX

set_location_assignment PIN_31 -to UART_RX

set_location_assignment PIN_105 -to SPI_DO

set_location_assignment PIN_88 -to SPI_DI

set_location_assignment PIN_126 -to SPI_SCK

set_location_assignment PIN_127 -to SPI_SS2

set_location_assignment PIN_91 -to SPI_SS3

set_location_assignment PIN_90 -to SPI_SS4

set_location_assignment PIN_13 -to CONF_DATA0

set_location_assignment PIN_49 -to SDRAM_A[0]

set_location_assignment PIN_44 -to SDRAM_A[1]

set_location_assignment PIN_42 -to SDRAM_A[2]

set_location_assignment PIN_39 -to SDRAM_A[3]

set_location_assignment PIN_4 -to SDRAM_A[4]

set_location_assignment PIN_6 -to SDRAM_A[5]

set_location_assignment PIN_8 -to SDRAM_A[6]

set_location_assignment PIN_10 -to SDRAM_A[7]

set_location_assignment PIN_11 -to SDRAM_A[8]

set_location_assignment PIN_28 -to SDRAM_A[9]

set_location_assignment PIN_50 -to SDRAM_A[10]

set_location_assignment PIN_30 -to SDRAM_A[11]

set_location_assignment PIN_32 -to SDRAM_A[12]

set_location_assignment PIN_83 -to SDRAM_DQ[0]

set_location_assignment PIN_79 -to SDRAM_DQ[1]

set_location_assignment PIN_77 -to SDRAM_DQ[2]

set_location_assignment PIN_76 -to SDRAM_DQ[3]

set_location_assignment PIN_72 -to SDRAM_DQ[4]

set_location_assignment PIN_71 -to SDRAM_DQ[5]

set_location_assignment PIN_69 -to SDRAM_DQ[6]

set_location_assignment PIN_68 -to SDRAM_DQ[7]

set_location_assignment PIN_86 -to SDRAM_DQ[8]

set_location_assignment PIN_87 -to SDRAM_DQ[9]

set_location_assignment PIN_98 -to SDRAM_DQ[10]

set_location_assignment PIN_99 -to SDRAM_DQ[11]

set_location_assignment PIN_100 -to SDRAM_DQ[12]

set_location_assignment PIN_101 -to SDRAM_DQ[13]

set_location_assignment PIN_103 -to SDRAM_DQ[14]

set_location_assignment PIN_104 -to SDRAM_DQ[15]

set_location_assignment PIN_58 -to SDRAM_BA[0]

set_location_assignment PIN_51 -to SDRAM_BA[1]

set_location_assignment PIN_85 -to SDRAM_DQMH

set_location_assignment PIN_67 -to SDRAM_DQML

set_location_assignment PIN_60 -to SDRAM_nRAS

set_location_assignment PIN_64 -to SDRAM_nCAS

set_location_assignment PIN_66 -to SDRAM_nWE

set_location_assignment PIN_59 -to SDRAM_nCS

set_location_assignment PIN_33 -to SDRAM_CKE

set_location_assignment PIN_43 -to SDRAM_CLK

set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE BALANCED

set_global_assignment -name SMART_RECOMPILE ON

set_global_assignment -name ENABLE_SIGNALTAP ON

set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON

set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON

set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT NORMAL

set_global_assignment -name FMAX_REQUIREMENT "114 MHz"

set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING OFF

set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0

set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85

set_global_assignment -name USE_CONFIGURATION_DEVICE ON

set_global_assignment -name TPD_REQUIREMENT "2 ns"

set_global_assignment -name TSU_REQUIREMENT "2 ns"

set_global_assignment -name TCO_REQUIREMENT "2 ns"

set_global_assignment -name ALLOW_POWER_UP_DONT_CARE OFF

set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS OFF

set_global_assignment -name AUTO_RAM_TO_LCELL_CONVERSION OFF

set_global_assignment -name AUTO_RAM_RECOGNITION ON

set_global_assignment -name AUTO_ROM_RECOGNITION ON

set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON

set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"

set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"

set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top

set_global_assignment -name PARTITION_COLOR 2147039 -section_id Top

set_global_assignment -name MISC_FILE atari800core.dpf

set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top

set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING ON

set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA OFF

set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA OFF

set_global_assignment -name PROJECT_OUTPUT_DIRECTORY out

set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 4.0

set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 4.0

set_global_assignment -name CYCLONEII_M4K_COMPATIBILITY OFF

#set_parameter -name ENABLE_RUNTIME_MOD YES -to "Minimig1:minimig|amiga_boot:BOOTROM1|altsyncram:Ram0_rtl_10"

#set_parameter -name INSTANCE_NAME mig -to "Minimig1:minimig|amiga_boot:BOOTROM1|altsyncram:Ram0_rtl_10"

set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF

set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"

set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"

set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"

set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"

set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise

set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall

set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise

set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall

set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[0]

set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[1]

set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[2]

set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[3]

set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[4]

set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[5]

set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[6]

set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[7]

set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[8]

set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[9]

set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[10]

set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[11]

set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[12]

set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[13]

set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[14]

set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[15]

set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[0]

set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[1]

set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[2]

set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[3]

set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[4]

set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[5]

set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[6]

set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[7]

set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[8]

set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[9]

set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[10]

set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[11]

set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[12]

set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[0]

set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[1]

set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQMH

set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQML

set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nRAS

set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCAS

set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nWE

set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCS

set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[0]

set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[1]

set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[2]

set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[3]

set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[4]

set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[5]

set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[6]

set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[7]

set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[8]

set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[9]

set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[10]

set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[11]

set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[12]

set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[13]

set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[14]

set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[15]

set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[0]

set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[1]

set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[2]

set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[3]

set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[4]

set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[5]

set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[6]

set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[7]

set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[8]

set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[9]

set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[10]

set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[11]

set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[12]

set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[13]

set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[14]

set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[15]

set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[0]

set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[1]

set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[2]

set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[3]

set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[4]

set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[5]

set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[6]

set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[7]

set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[8]

set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[9]

set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[10]

set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[11]

set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[12]

set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[0]

set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[1]

set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[2]

set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[3]

set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[4]

set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[5]

set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[6]

set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[7]

set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[8]

set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[9]

set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[10]

set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[11]

set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[12]

set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[13]

set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[14]

set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[15]

set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_BA[0]

set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_BA[1]

set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQML

set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQMH

set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_nRAS

set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_nCAS

set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_nWE

set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_nCS

set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_CKE

set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_CLK

set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_R[5]

set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_R[4]

set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_R[3]

set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_R[2]

set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_R[1]

set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_R[0]

set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_G[5]

set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_G[4]

set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_G[3]

set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_G[2]

set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_G[1]

set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_G[0]

set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_B[5]

set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_B[4]

set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_B[3]

set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_B[2]

set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_B[1]

set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_B[0]

set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

set_global_assignment -name VHDL_FILE data_io.vhdl

set_global_assignment -name VHDL_FILE zpu_rom.vhdl

set_global_assignment -name SDC_FILE atari800core.sdc

set_global_assignment -name QIP_FILE mist_sector_buffer.qip

set_global_assignment -name VHDL_FILE atari800core_mist.vhd

set_global_assignment -name VERILOG_FILE user_io.v

set_global_assignment -name QIP_FILE pll_pal_pre.qip

set_global_assignment -name QIP_FILE pll_pal_post.qip

set_global_assignment -name QIP_FILE pll_ntsc.qip

create_clock -period 27MHz [get_ports CLOCK_27[0]]

derive_pll_clocks

create_generated_clock -name sdclk_pin -source [get_pins {clock|altpll_component|auto_generated|pll1|clk[2]}] [get_ports {SDRAM_CLK}]

derive_clock_uncertainty

set_input_delay -clock sdclk_pin -max 6.4 [get_ports SDRAM_DQ*]

set_input_delay -clock sdclk_pin -min 3.2 [get_ports SDRAM_DQ*]

set_output_delay -clock sdclk_pin -max 1.5 [get_ports SDRAM_*]

set_output_delay -clock sdclk_pin -min -0.8 [get_ports SDRAM_*]

set_multicycle_path -from [get_clocks {sdclk_pin}] -to [get_clocks {clock|altpll_component|auto_generated|pll1|clk[0]}] -setup -end 2

--------------------------------------------------------------------------- -- (c) 2013 mark watson

-- I am happy for anyone to use this for non-commercial use.

-- If my vhdl files are used commercially or otherwise sold,

-- please contact me for explicit permission at scrameta (gmail).

-- This applies for source and binary form and derived works.

---------------------------------------------------------------------------

LIBRARY ieee;

USE ieee.std_logic_1164.all;

use ieee.numeric_std.all;

LIBRARY work;

ENTITY atari800core_mist IS

GENERIC

(

TV : integer; -- 1 = PAL, 0=NTSC

VIDEO : integer; -- 1 = RGB, 2 = VGA

COMPOSITE_SYNC : integer; --0 = no, 1 = yes!

SCANDOUBLE : integer -- 1 = YES, 0=NO, (+ later scanlines etc)

);

PORT

(

CLOCK_27 : IN STD_LOGIC_VECTOR(1 downto 0);

VGA_VS : OUT STD_LOGIC;

VGA_HS : OUT STD_LOGIC;

VGA_B : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);

VGA_G : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);

VGA_R : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);

AUDIO_L : OUT std_logic;

AUDIO_R : OUT std_logic;

SDRAM_BA : OUT STD_LOGIC_VECTOR(1 downto 0);

SDRAM_nCS : OUT STD_LOGIC;

SDRAM_nRAS : OUT STD_LOGIC;

SDRAM_nCAS : OUT STD_LOGIC;

SDRAM_nWE : OUT STD_LOGIC;

SDRAM_DQMH : OUT STD_LOGIC;

SDRAM_DQML : OUT STD_LOGIC;

SDRAM_CLK : OUT STD_LOGIC;

SDRAM_CKE : OUT STD_LOGIC;

SDRAM_A : OUT STD_LOGIC_VECTOR(12 DOWNTO 0);

SDRAM_DQ : INOUT STD_LOGIC_VECTOR(15 DOWNTO 0);

LED : OUT std_logic;

UART_TX : OUT STD_LOGIC;

UART_RX : IN STD_LOGIC;

SPI_DO : INOUT STD_LOGIC;

SPI_DI : IN STD_LOGIC;

SPI_SCK : IN STD_LOGIC;

SPI_SS2 : IN STD_LOGIC;

SPI_SS3 : IN STD_LOGIC;

SPI_SS4 : IN STD_LOGIC;

CONF_DATA0 : IN STD_LOGIC -- AKA SPI_SS5

);

END atari800core_mist;

ARCHITECTURE vhdl OF atari800core_mist IS

component hq_dac

port (

reset :in std_logic;

clk :in std_logic;

clk_ena : in std_logic;

pcm_in : in std_logic_vector(19 downto 0);

dac_out : out std_logic

);

end component;

component user_io

PORT(

SPI_CLK : in std_logic;

SPI_SS_IO : in std_logic;

SPI_MISO : out std_logic;

SPI_MOSI : in std_logic;

CORE_TYPE : in std_logic_vector(7 downto 0);

JOY0 : out std_logic_vector(5 downto 0);

JOY1 : out std_logic_vector(5 downto 0);

BUTTONS : out std_logic_vector(1 downto 0);

SWITCHES : out std_logic_vector(1 downto 0);

CLK : in std_logic;

PS2_CLK : out std_logic;

PS2_DATA : out std_logic

);

end component;

signal AUDIO_L_PCM : std_logic_vector(15 downto 0);

signal AUDIO_R_PCM : std_logic_vector(15 downto 0);

signal VGA_VS_RAW : std_logic;

signal VGA_HS_RAW : std_logic;

signal RESET_n : std_logic;

signal PLL_LOCKED : std_logic;

signal CLK : std_logic;

signal CLK_SDRAM : std_logic;

signal CLK_PLL1 : std_logic; -- cascaded to get better pal clock

signal PLL1_LOCKED : std_logic;

SIGNAL PS2_CLK : std_logic;

SIGNAL PS2_DAT : std_logic;

SIGNAL CONSOL_OPTION_RAW : STD_LOGIC;

SIGNAL CONSOL_OPTION : STD_LOGIC;

SIGNAL CONSOL_SELECT_RAW : STD_LOGIC;

SIGNAL CONSOL_SELECT : STD_LOGIC;

SIGNAL CONSOL_START_RAW : STD_LOGIC;

SIGNAL CONSOL_START : STD_LOGIC;

SIGNAL FKEYS : std_logic_vector(11 downto 0);

signal capslock_pressed : std_logic;

signal capsheld_next : std_logic;

signal capsheld_reg : std_logic;

signal mist_sector_ready : std_logic;

signal mist_sector_ready_sync : std_logic;

signal mist_sector_request : std_logic;

signal mist_sector_request_sync : std_logic;

signal mist_sector_write : std_logic;

signal mist_sector_write_sync : std_logic;

signal mist_sector : std_logic_vector(25 downto 0);

signal mist_sector_sync : std_logic_vector(25 downto 0);

signal mist_addr : std_logic_vector(8 downto 0);

signal mist_do : std_logic_vector(7 downto 0);

signal mist_di : std_logic_vector(7 downto 0);

signal mist_wren : std_logic;

signal spi_miso_data : std_logic;

signal spi_miso_io : std_logic;

signal mist_buttons : std_logic_vector(1 downto 0);

signal mist_switches : std_logic_vector(1 downto 0);

signal JOY1 : STD_LOGIC_VECTOR(5 DOWNTO 0);

signal JOY2 : STD_LOGIC_VECTOR(5 DOWNTO 0);

signal JOY1_n : STD_LOGIC_VECTOR(4 DOWNTO 0);

signal JOY2_n : STD_LOGIC_VECTOR(4 DOWNTO 0);

signal joy_still : std_logic;

SIGNAL KEYBOARD_RESPONSE : STD_LOGIC_VECTOR(1 DOWNTO 0);

SIGNAL KEYBOARD_SCAN : STD_LOGIC_VECTOR(5 DOWNTO 0);

SIGNAL PAL : std_logic;

SIGNAL COMPOSITE_ON_HSYNC : std_logic;

SIGNAL VGA : std_logic;

signal SDRAM_REQUEST : std_logic;

signal SDRAM_REQUEST_COMPLETE : std_logic;

signal SDRAM_READ_ENABLE : STD_LOGIC;

signal SDRAM_WRITE_ENABLE : std_logic;

signal SDRAM_ADDR : STD_LOGIC_VECTOR(22 DOWNTO 0);

signal SDRAM_DO : STD_LOGIC_VECTOR(31 DOWNTO 0);

signal SDRAM_DI : STD_LOGIC_VECTOR(31 DOWNTO 0);

signal SDRAM_WIDTH_8bit_ACCESS : std_logic;

signal SDRAM_WIDTH_16bit_ACCESS : std_logic;

signal SDRAM_WIDTH_32bit_ACCESS : std_logic;

signal SDRAM_REFRESH : std_logic;

signal SDRAM_RESET_N : std_logic;

-- dma/virtual drive

signal DMA_ADDR_FETCH : std_logic_vector(23 downto 0);

signal DMA_WRITE_DATA : std_logic_vector(31 downto 0);

signal DMA_FETCH : std_logic;

signal DMA_32BIT_WRITE_ENABLE : std_logic;

signal DMA_16BIT_WRITE_ENABLE : std_logic;

signal DMA_8BIT_WRITE_ENABLE : std_logic;

signal DMA_READ_ENABLE : std_logic;

signal DMA_MEMORY_READY : std_logic;

signal DMA_MEMORY_DATA : std_logic_vector(31 downto 0);

signal ZPU_ADDR_ROM : std_logic_vector(15 downto 0);

signal ZPU_ROM_DATA : std_logic_vector(31 downto 0);

signal ZPU_OUT1 : std_logic_vector(31 downto 0);

signal ZPU_OUT2 : std_logic_vector(31 downto 0);

signal ZPU_OUT3 : std_logic_vector(31 downto 0);

signal ZPU_OUT4 : std_logic_vector(31 downto 0);

signal zpu_pokey_enable : std_logic;

signal zpu_sio_txd : std_logic;

signal zpu_sio_rxd : std_logic;

signal zpu_sio_command : std_logic;

-- system control from zpu

signal ram_select : std_logic_vector(2 downto 0);

signal rom_select : std_logic_vector(5 downto 0);

signal reset_atari : std_logic;

signal pause_atari : std_logic;

SIGNAL speed_6502 : std_logic_vector(5 downto 0);

-- mist sector

signal ZPU_ROM_DATA_MUX : std_logic_vector(31 downto 0);

signal ZPU_SECTOR_DATA : std_logic_vector(31 downto 0);

signal ZPU_ROM_DO : std_logic_vector(31 downto 0);

signal ZPU_ROM_WREN : std_logic;

-- ps2

signal SLOW_PS2_CLK : std_logic; -- around 16KHz

-- scandoubler

signal half_scandouble_enable_reg : std_logic;

signal half_scandouble_enable_next : std_logic;

signal VIDEO_B : std_logic_vector(7 downto 0);

BEGIN

pal <= '1' when tv=1 else '0';

vga <= '1' when video=2 else '0';

composite_on_hsync <= '1' when composite_sync=1 else '0';

-- mist spi io

mist_spi_interface : entity work.data_io

PORT map

(

CLK =>spi_sck,

RESET_n =>reset_n,

-- SPI connection - up to upstream to make miso 'Z' on ss_io going high

SPI_CLK =>spi_sck,

SPI_SS_IO => spi_ss2,

SPI_MISO => spi_miso_data,

SPI_MOSI => spi_di,

-- Sector access request

read_request => mist_sector_request_sync,

write_request => mist_sector_write_sync,

--request => mist_sector_request_sync,

sector => mist_sector_sync(25 downto 0),

ready => mist_sector_ready,

-- DMA to RAM

ADDR => mist_addr,

DATA_OUT => mist_do,

DATA_IN => mist_di,

WR_EN => mist_wren

);

-- TODO, review if these are all needed when ZPU connected again...

select_sync : entity work.synchronizer

PORT MAP ( CLK => clk, raw => mist_sector_ready, sync=>mist_sector_ready_sync);

select_sync2 : entity work.synchronizer

PORT MAP ( CLK => spi_sck, raw => mist_sector_request, sync=>mist_sector_request_sync);

select_sync3 : entity work.synchronizer

PORT MAP ( CLK => spi_sck, raw => mist_sector_write, sync=>mist_sector_write_sync);

sector_sync0 : entity work.synchronizer

PORT MAP ( CLK => spi_sck, raw => mist_sector(0), sync=>mist_sector_sync(0));

sector_sync1 : entity work.synchronizer

PORT MAP ( CLK => spi_sck, raw => mist_sector(1), sync=>mist_sector_sync(1));

sector_sync2 : entity work.synchronizer

PORT MAP ( CLK => spi_sck, raw => mist_sector(2), sync=>mist_sector_sync(2));

sector_sync3 : entity work.synchronizer

PORT MAP ( CLK => spi_sck, raw => mist_sector(3), sync=>mist_sector_sync(3));

sector_sync4 : entity work.synchronizer

PORT MAP ( CLK => spi_sck, raw => mist_sector(4), sync=>mist_sector_sync(4));

sector_sync5 : entity work.synchronizer

PORT MAP ( CLK => spi_sck, raw => mist_sector(5), sync=>mist_sector_sync(5));

sector_sync6 : entity work.synchronizer

PORT MAP ( CLK => spi_sck, raw => mist_sector(6), sync=>mist_sector_sync(6));

sector_sync7 : entity work.synchronizer

PORT MAP ( CLK => spi_sck, raw => mist_sector(7), sync=>mist_sector_sync(7));

sector_sync8 : entity work.synchronizer

PORT MAP ( CLK => spi_sck, raw => mist_sector(8), sync=>mist_sector_sync(8));

sector_sync9 : entity work.synchronizer

PORT MAP ( CLK => spi_sck, raw => mist_sector(9), sync=>mist_sector_sync(9));

sector_sync10 : entity work.synchronizer

PORT MAP ( CLK => spi_sck, raw => mist_sector(10), sync=>mist_sector_sync(10));

sector_sync11 : entity work.synchronizer

PORT MAP ( CLK => spi_sck, raw => mist_sector(11), sync=>mist_sector_sync(11));

sector_sync12 : entity work.synchronizer

PORT MAP ( CLK => spi_sck, raw => mist_sector(12), sync=>mist_sector_sync(12));

sector_sync13 : entity work.synchronizer

PORT MAP ( CLK => spi_sck, raw => mist_sector(13), sync=>mist_sector_sync(13));

sector_sync14 : entity work.synchronizer

PORT MAP ( CLK => spi_sck, raw => mist_sector(14), sync=>mist_sector_sync(14));

sector_sync15 : entity work.synchronizer

PORT MAP ( CLK => spi_sck, raw => mist_sector(15), sync=>mist_sector_sync(15));

sector_sync16 : entity work.synchronizer

PORT MAP ( CLK => spi_sck, raw => mist_sector(16), sync=>mist_sector_sync(16));

sector_sync17 : entity work.synchronizer

PORT MAP ( CLK => spi_sck, raw => mist_sector(17), sync=>mist_sector_sync(17));

sector_sync18 : entity work.synchronizer

PORT MAP ( CLK => spi_sck, raw => mist_sector(18), sync=>mist_sector_sync(18));

sector_sync19 : entity work.synchronizer

PORT MAP ( CLK => spi_sck, raw => mist_sector(19), sync=>mist_sector_sync(19));

sector_sync20 : entity work.synchronizer

PORT MAP ( CLK => spi_sck, raw => mist_sector(20), sync=>mist_sector_sync(20));

sector_sync21 : entity work.synchronizer

PORT MAP ( CLK => spi_sck, raw => mist_sector(21), sync=>mist_sector_sync(21));

sector_sync22 : entity work.synchronizer

PORT MAP ( CLK => spi_sck, raw => mist_sector(22), sync=>mist_sector_sync(22));

sector_sync23 : entity work.synchronizer

PORT MAP ( CLK => spi_sck, raw => mist_sector(23), sync=>mist_sector_sync(23));

sector_sync24 : entity work.synchronizer

PORT MAP ( CLK => spi_sck, raw => mist_sector(24), sync=>mist_sector_sync(24));

sector_sync25 : entity work.synchronizer

PORT MAP ( CLK => spi_sck, raw => mist_sector(25), sync=>mist_sector_sync(25));

spi_do <= spi_miso_io when CONF_DATA0 ='0' else spi_miso_data when spi_SS2='0' else 'Z';

mist_sector_buffer1 : entity work.mist_sector_buffer

PORT map

(

address_a => mist_addr,

address_b => zpu_addr_rom(8 downto 2),