repo2/mist/user_io.v @ 173
| 70 | markw | // MiST user_io
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module user_io(
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input SPI_CLK,
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input SPI_SS_IO,
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output reg SPI_MISO,
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input SPI_MOSI,
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input [7:0] CORE_TYPE,
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output [5:0] JOY0,
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output [5:0] JOY1,
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output [1:0] BUTTONS,
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output [1:0] SWITCHES,
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input clk,
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output ps2_clk,
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output reg ps2_data
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);
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reg [6:0] sbuf;
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reg [7:0] cmd;
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reg [4:0] cnt;
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reg [5:0] joystick0;
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reg [5:0] joystick1;
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reg [3:0] but_sw;
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assign JOY0 = joystick0;
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assign JOY1 = joystick1;
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assign BUTTONS = but_sw[1:0];
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assign SWITCHES = but_sw[3:2];
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// drive MISO only when transmitting core id
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always@(negedge SPI_CLK or posedge SPI_SS_IO) begin
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if(SPI_SS_IO == 1) begin
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SPI_MISO <= 1'bZ;
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end else begin
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if(cnt < 8) begin
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SPI_MISO <= CORE_TYPE[7-cnt];
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end else begin
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SPI_MISO <= 1'bZ;
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end
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end
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end
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// 8 byte fifo to store ps2 bytes
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localparam PS2_FIFO_BITS = 3;
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reg [7:0] ps2_fifo [(2**PS2_FIFO_BITS)-1:0];
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reg [PS2_FIFO_BITS-1:0] ps2_wptr;
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reg [PS2_FIFO_BITS-1:0] ps2_rptr;
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// ps2 transmitter state machine
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reg [3:0] ps2_tx_state;
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reg [7:0] ps2_tx_byte;
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reg ps2_parity;
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assign ps2_clk = clk || (ps2_tx_state == 0);
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// ps2 transmitter
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// Takes a byte from the FIFO and sends it in a ps2 compliant serial format.
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reg ps2_r_inc;
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always@(posedge clk) begin
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ps2_r_inc <= 1'b0;
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if(ps2_r_inc)
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ps2_rptr <= ps2_rptr + 1;
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// transmitter is idle?
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if(ps2_tx_state == 0) begin
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// data in fifo present?
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if(ps2_wptr != ps2_rptr) begin
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// load tx register from fifo
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ps2_tx_byte <= ps2_fifo[ps2_rptr];
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ps2_r_inc <= 1'b1;
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| 1 | markw | ||
| 70 | markw | // reset parity
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ps2_parity <= 1'b1;
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// start transmitter
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ps2_tx_state <= 4'd1;
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// put start bit on data line
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ps2_data <= 1'b0; // start bit is 0
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end
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end else begin
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// transmission of 8 data bits
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if((ps2_tx_state >= 1)&&(ps2_tx_state < 9)) begin
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ps2_data <= ps2_tx_byte[0]; // data bits
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ps2_tx_byte[6:0] <= ps2_tx_byte[7:1]; // shift down
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if(ps2_tx_byte[0])
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ps2_parity <= !ps2_parity;
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end
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// transmission of parity
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if(ps2_tx_state == 9)
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ps2_data <= ps2_parity;
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// transmission of stop bit
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if(ps2_tx_state == 10)
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ps2_data <= 1'b1; // stop bit is 1
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// advance state machine
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if(ps2_tx_state < 11)
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ps2_tx_state <= ps2_tx_state + 4'd1;
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else
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ps2_tx_state <= 4'd0;
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end
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end
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// SPI receiver
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//reg ps2_w_inc;
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always@(posedge SPI_CLK or posedge SPI_SS_IO) begin
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// ps2_w_inc <= 1'b0;
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// if(ps2_w_inc)
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// ps2_wptr <= ps2_wptr + 1;
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if(SPI_SS_IO == 1) begin
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cnt <= 1'b0;
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end else begin
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sbuf[6:0] <= { sbuf[5:0], SPI_MOSI };
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// counter counts 0-7, 8-15, 8-15 ...
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// 0-7 is command, 8-15 is payload
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if(cnt != 15) cnt <= cnt + 4'd1;
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else cnt <= 4'd8;
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// finished reading command byte
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if(cnt == 7)
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cmd <= { sbuf, SPI_MOSI};
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if(cnt == 15) begin
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if(cmd == 1)
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but_sw <= { sbuf[2:0], SPI_MOSI };
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if(cmd == 2)
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joystick0 <= { sbuf[4:0], SPI_MOSI };
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if(cmd == 3)
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joystick1 <= { sbuf[4:0], SPI_MOSI };
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if(cmd == 5) begin
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// store incoming keyboard bytes in
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ps2_fifo[ps2_wptr] <= { sbuf, SPI_MOSI };
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ps2_wptr <= ps2_wptr + 1;
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| 1 | markw | end
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| 70 | markw | ||
end
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end
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end
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endmodule
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