repo2/mist/data_io.vhdl @ 173
| 1 | markw | LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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LIBRARY work;
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ENTITY data_io IS
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PORT
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(
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CLK : in std_logic;
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RESET_n : in std_logic;
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-- SPI connection - up to upstream to make miso 'Z' on ss_io going high
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SPI_CLK : in std_logic;
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SPI_SS_IO : in std_logic;
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SPI_MISO: out std_logic;
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SPI_MOSI : in std_logic;
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| 70 | markw | -- Sector access read_request
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read_request : in std_logic;
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write_request : in std_logic;
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| 162 | markw | sector : in std_logic_vector(25 downto 0);
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| 1 | markw | ready : out std_logic;
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-- DMA to RAM
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ADDR: out std_logic_vector(8 downto 0);
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DATA_OUT : out std_logic_vector(7 downto 0);
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DATA_IN : in std_logic_vector(7 downto 0);
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WR_EN : out std_logic
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);
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end data_io;
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architecture vhdl of data_io is
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signal sbuf_next : std_logic_vector(6 downto 0);
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signal sbuf_reg : std_logic_vector(6 downto 0);
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signal cmd_next : std_logic_vector(7 downto 0);
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signal cmd_reg : std_logic_vector(7 downto 0);
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signal cnt_next : std_logic_vector(15 downto 0);
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signal cnt_reg : std_logic_vector(15 downto 0);
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| 70 | markw | ||
signal data_in_next : std_logic_vector(7 downto 0);
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signal data_in_reg : std_logic_vector(7 downto 0);
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| 1 | markw | ||
signal data_out_next : std_logic_vector(7 downto 0);
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signal data_out_reg : std_logic_vector(7 downto 0);
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signal addr_next : std_logic_vector(8 downto 0);
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signal addr_reg : std_logic_vector(8 downto 0);
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signal wren_next : std_logic;
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signal wren_reg : std_logic;
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signal ready_next : std_logic;
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signal ready_reg : std_logic;
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signal transmit_next : std_logic_vector(7 downto 0);
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signal transmit_reg : std_logic_vector(7 downto 0);
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| 162 | markw | signal sector_next : std_logic_vector(25 downto 0);
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signal sector_reg : std_logic_vector(25 downto 0);
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| 1 | markw | ||
| 70 | markw | signal read_request_next : std_logic;
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signal read_request_reg : std_logic;
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| 1 | markw | ||
| 70 | markw | signal write_request_next : std_logic;
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signal write_request_reg : std_logic;
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signal clk2 : std_logic;
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| 1 | markw | begin
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| 70 | markw | clk2 <= clk or spi_ss_io;
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process(clk2,reset_n,spi_ss_io)
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| 1 | markw | begin
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| 70 | markw | if (spi_ss_io = '1') then
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cnt_reg <= (others=>'0');
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cmd_reg <= (others=>'0');
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wren_reg <= '0';
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elsif (reset_n = '0') then
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| 1 | markw | cnt_reg <= (others=>'0');
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cmd_reg <= (others=>'0');
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sbuf_reg <= (others=>'0');
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addr_reg <= (others => '0');
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| 70 | markw | data_in_reg <= (others => '0');
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| 1 | markw | data_out_reg <= (others => '0');
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wren_reg <= '0';
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ready_reg <= '0';
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transmit_reg <= (others=>'0');
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| 70 | markw | read_request_reg <= '0';
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write_request_reg <= '0';
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| 1 | markw | sector_reg <=(others=>'0');
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| 70 | markw | elsif (clk2'event and clk2='1') then
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| 1 | markw | cnt_reg <= cnt_next;
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cmd_reg <= cmd_next;
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sbuf_reg <= sbuf_next;
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addr_reg <= addr_next;
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| 70 | markw | data_in_reg <= data_in_next;
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| 1 | markw | data_out_reg <= data_out_next;
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wren_reg <= wren_next;
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ready_reg <= ready_next;
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transmit_reg <= transmit_next;
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| 70 | markw | read_request_reg <= read_request_next;
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write_request_reg <= write_request_next;
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| 1 | markw | sector_reg <= sector_next;
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end if;
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end process;
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-- clk_sync : synchronizer
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-- PORT MAP ( CLK => clk, raw => spi_clk, sync=>spi_clk_next);
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--spi_clk_next <= spi_clk;
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-- input_sync : synchronizer
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-- PORT MAP ( CLK => clk, raw => spi_mosi, sync=>spi_mosi_next);
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-- select_sync : synchronizer
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-- PORT MAP ( CLK => clk, raw => spi_ss_io, sync=>spi_ss_next);
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| 70 | markw | ||
data_in_next <= data_in;
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| 1 | markw | ||
| 70 | markw | process(spi_ss_io,cnt_reg, sbuf_reg, transmit_reg, spi_mosi, addr_reg, cmd_reg, sector_reg, write_request_reg, read_request_reg, ready_reg,read_request,write_request,sector,data_in_reg)
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| 1 | markw | begin
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cnt_next <= cnt_reg;
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sbuf_next <= sbuf_reg;
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cmd_next <= cmd_reg;
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| 70 | markw | ready_next <= ready_reg and (read_request or write_request); -- stay ready until read_request cleared (received by other end)
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| 1 | markw | ||
transmit_next <= transmit_reg;
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wren_next <= '0';
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data_out_next <= (others=>'0');
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addr_next <= addr_reg;
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sector_next <= sector_reg;
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| 70 | markw | read_request_next <= read_request_reg;
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write_request_next <= write_request_reg;
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| 1 | markw | ||
--- It polls get_status 10 times a second
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--- it uses SPI_SS2 for this
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--- it sends command code 0x50
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--- reads 4 bytes afterwards
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--- it reports whenever the returned value is different then the one from previous get_status
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--- if the lowest byte of the status (the last transmitted of the four) is 0xa5:
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--- a sector is read from sd card with the sector no being the upper/first three bytes transmitted
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--- if the sector could be read
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--- SPI_SS2 is activated
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--- command byte 0x51 is sent
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--- all 512 sector bytes are sent
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--if (spi_clk_reg = '1' and spi_clk_next = '0') then
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transmit_next(7 downto 1) <= transmit_reg(6 downto 0);
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transmit_next(0) <= '0';
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cnt_next <= std_logic_vector(unsigned(cnt_reg) + 1);
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sbuf_next(6 downto 1) <= sbuf_reg(5 downto 0);
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sbuf_next(0) <= SPI_MOSI;
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| 70 | markw | ||
if (cnt_reg = X"0000") then
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addr_next <= (others=>'0');
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end if;
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| 1 | markw | ||
if (cnt_reg = X"0007") then
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cmd_next(7 downto 1) <= sbuf_reg;
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cmd_next(0) <= SPI_MOSI;
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sector_next <= sector;
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| 70 | markw | read_request_next <= read_request;
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write_request_next <= write_request;
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| 1 | markw | end if;
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--end if;
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case cmd_reg is
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when X"50" => --get status
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case cnt_reg is
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when X"0008" =>
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| 162 | markw | transmit_next <= sector_reg(25 downto 18);
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| 1 | markw | when X"0010" =>
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| 162 | markw | transmit_next <= sector_reg(17 downto 10);
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| 1 | markw | when X"0018" =>
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| 162 | markw | transmit_next <= sector_reg(9 downto 2);
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| 1 | markw | when X"0020" =>
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| 162 | markw | transmit_next <= sector_reg(1 downto 0)&"1010"&write_request_reg&read_request_reg; --read read_request
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| 1 | markw | when others =>
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-- nothing
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end case;
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when X"51" => --sector read from sd, write it...
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| 70 | markw | if (cnt_reg = X"0008") then
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addr_next <= (others=>'1');
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end if;
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| 1 | markw | if (cnt_reg(2 downto 0) = "111") then
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addr_next <= std_logic_vector(unsigned(addr_reg) + 1);
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data_out_next(7 downto 1) <= sbuf_reg;
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data_out_next(0) <= SPI_MOSI;
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| 70 | markw | wren_next <= read_request;
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| 1 | markw | ||
if (cnt_reg(12) = '1')then
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ready_next <= '1';
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end if;
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end if;
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| 70 | markw | when X"52" => -- read from write, write to sd
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if (cnt_reg(2 downto 0) = "000") then
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addr_next <= std_logic_vector(unsigned(addr_reg) + 1);
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transmit_next <= data_in_reg;
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if (cnt_reg(12) = '1')then
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ready_next <= '1';
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end if;
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end if;
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| 1 | markw | when others =>
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-- nop
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end case;
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end process;
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-- outputs
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| 70 | markw | addr <= addr_next;
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data_out <= data_out_next;
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wr_en <= wren_next;
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| 1 | markw | ||
ready <= ready_reg;
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spi_miso <= transmit_next(7);
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end vhdl;
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