repo2/aeon_lite/dac.vhd @ 173
| 149 | markw | library ieee;
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use ieee.std_logic_1164.all;
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entity dac is
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generic (
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msbi_g : integer := 15
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);
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port (
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clk_i : in std_logic;
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res_n_i : in std_logic;
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dac_i : in std_logic_vector(msbi_g downto 0);
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dac_o : out std_logic
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);
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end dac;
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library ieee;
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use ieee.numeric_std.all;
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architecture rtl of dac is
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signal DACout_q : std_logic;
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signal DeltaAdder_s,
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SigmaAdder_s,
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SigmaLatch_q,
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DeltaB_s : unsigned(msbi_g+2 downto 0);
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begin
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DeltaB_s(msbi_g+2 downto msbi_g+1) <= SigmaLatch_q(msbi_g+2) &
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SigmaLatch_q(msbi_g+2);
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DeltaB_s(msbi_g downto 0) <= (others => '0');
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DeltaAdder_s <= unsigned('0' & '0' & dac_i) + DeltaB_s;
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SigmaAdder_s <= DeltaAdder_s + SigmaLatch_q;
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seq: process (clk_i, res_n_i)
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begin
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if res_n_i = '0' then
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SigmaLatch_q <= to_unsigned(2**(msbi_g+1), SigmaLatch_q'length);
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DACout_q <= '0';
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elsif clk_i'event and clk_i = '1' then
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SigmaLatch_q <= SigmaAdder_s;
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DACout_q <= SigmaLatch_q(msbi_g+2);
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end if;
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end process seq;
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dac_o <= DACout_q;
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end rtl;
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