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Revision 167

Added by markw about 11 years ago

Match more closely to schematic - delay/inversion

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common/a8core/pokey_poly_17_9.vhdl
ARCHITECTURE vhdl OF pokey_poly_17_9 IS
signal shift_reg: std_logic_vector(16 downto 0);
signal shift_next: std_logic_vector(16 downto 0);
signal cycle_delay_reg : std_logic;
signal cycle_delay_next : std_logic;
signal feedback : std_logic;
BEGIN
......
begin
if (reset_n = '0') then
shift_reg <= "01010101010101010";
cycle_delay_reg <= '0';
elsif (clk'event and clk='1') then
shift_reg <= shift_next;
cycle_delay_reg <= cycle_delay_next;
end if;
end process;
-- next state (as pokey decap)
feedback <= shift_reg(13) xnor shift_reg(8);
process(enable,shift_reg,feedback,select_9_17,init)
process(enable,shift_reg,feedback,select_9_17,init,cycle_delay_reg)
begin
shift_next <= shift_reg;
cycle_delay_next <= cycle_delay_reg;
if (enable = '1') then
shift_next(15 downto 8) <= shift_reg(16 downto 9);
......
shift_next(6 downto 0) <= shift_reg(7 downto 1);
shift_next(16) <= ((feedback and select_9_17) or (shift_reg(0) and not(select_9_17))) and not(init);
cycle_delay_next <= shift_reg(9);
end if;
end process;
-- output
bit_out <= shift_reg(9);
bit_out <= cycle_delay_reg; -- from pokey schematics
RAND_OUT(7 downto 0) <= not(shift_reg(15 downto 8));
END vhdl;
common/a8core/pokey_poly_4.vhdl
end process;
-- output
bit_out <= not(shift_reg(0));
bit_out <= shift_reg(0);
END vhdl;

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