Revision 166
Added by markw about 11 years ago
common/a8core/pokey.vhdl | ||
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signal noise_4 : std_logic;
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signal noise_5 : std_logic;
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signal noise_large : std_logic;
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signal noise_4_next : std_logic_vector(2 downto 0);
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signal noise_4_reg : std_logic_vector(2 downto 0);
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signal noise_5_next : std_logic_vector(2 downto 0);
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signal noise_5_reg : std_logic_vector(2 downto 0);
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signal noise_large_next : std_logic_vector(2 downto 0);
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signal noise_large_reg : std_logic_vector(2 downto 0);
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signal rand_out : std_logic_vector(7 downto 0); -- snoop part of the shift reg
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signal initmode : std_logic;
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... | ... | |
pot_counter_reg <= (others=>'0');
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pot_reset_reg <= '1';
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noise_4_reg <= (others=>'0');
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noise_5_reg <= (others=>'0');
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noise_large_reg <= (others=>'0');
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elsif (clk'event and clk='1') then
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audf0_reg <= audf0_next;
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... | ... | |
pot_counter_reg <= pot_counter_next;
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pot_reset_reg <= pot_reset_next;
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noise_4_reg <= noise_4_next;
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noise_5_reg <= noise_5_next;
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noise_large_reg <= noise_large_next;
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end if;
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end process;
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... | ... | |
pokey_noise_filter0 : pokey_noise_filter
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port map(clk=>clk,noise_select=>audc0_reg(7 downto 5),pulse_in=>audf0_pulse,pulse_out=>audf0_pulse_noise,noise_4=>noise_4,noise_5=>noise_5,noise_large=>noise_large);
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pokey_noise_filter1 : pokey_noise_filter
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port map(clk=>clk,noise_select=>audc1_reg(7 downto 5),pulse_in=>audf1_pulse,pulse_out=>audf1_pulse_noise,noise_4=>noise_4,noise_5=>noise_5,noise_large=>noise_large);
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port map(clk=>clk,noise_select=>audc1_reg(7 downto 5),pulse_in=>audf1_pulse,pulse_out=>audf1_pulse_noise,noise_4=>noise_4_reg(0),noise_5=>noise_5_reg(0),noise_large=>noise_large_reg(0));
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pokey_noise_filter2 : pokey_noise_filter
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port map(clk=>clk,noise_select=>audc2_reg(7 downto 5),pulse_in=>audf2_pulse,pulse_out=>audf2_pulse_noise,noise_4=>noise_4,noise_5=>noise_5,noise_large=>noise_large);
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port map(clk=>clk,noise_select=>audc2_reg(7 downto 5),pulse_in=>audf2_pulse,pulse_out=>audf2_pulse_noise,noise_4=>noise_4_reg(1),noise_5=>noise_5_reg(1),noise_large=>noise_large_reg(1));
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pokey_noise_filter3 : pokey_noise_filter
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port map(clk=>clk,noise_select=>audc3_reg(7 downto 5),pulse_in=>audf3_pulse,pulse_out=>audf3_pulse_noise,noise_4=>noise_4,noise_5=>noise_5,noise_large=>noise_large);
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port map(clk=>clk,noise_select=>audc3_reg(7 downto 5),pulse_in=>audf3_pulse,pulse_out=>audf3_pulse_noise,noise_4=>noise_4_reg(2),noise_5=>noise_5_reg(2),noise_large=>noise_large_reg(2));
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-- Audio output stage
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-- (toggling now handled in the noise filter - the subtlety on when to toggle and when to sample is important)
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... | ... | |
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poly_4_lfsr : pokey_poly_4
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port map(clk=>clk,reset_n=>reset_n,init=>initmode,enable=>enable_179,bit_out=>noise_4);
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-- Delay between feeding noise between channels
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process(noise_large_reg, noise_5_reg, noise_4_reg, noise_large, noise_5, noise_4, enable_179)
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begin
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noise_large_next <= noise_large_reg;
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noise_5_next <= noise_5_reg;
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noise_4_next <= noise_4_reg;
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if (enable_179='1') then
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noise_large_next <= noise_large_reg(1 downto 0)&noise_large;
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noise_5_next <= noise_5_reg(1 downto 0)&noise_5;
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noise_4_next <= noise_4_reg(1 downto 0)&noise_4;
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end if;
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end process;
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--AUDIO_LEFT <= "000"&count_reg(15 downto 3);
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process(chan0_output_reg, chan1_output_reg, chan2_output_reg, chan3_output_reg, audc0_reg, audc1_reg, audc2_reg, audc3_reg, highpass0_reg, highpass1_reg)
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... | ... | |
if (skctl_reg(3) = '1') then
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sio_out_next <= twotone_reg;
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end if;
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-- force break
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if (skctl_reg(7) = '1') then
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sio_out_next <= '0';
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end if;
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serial_op_needed_interrupt <= '0';
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... | ... | |
serout_bitcount_next <= std_logic_vector(unsigned(serout_bitcount_reg)-1);
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end if;
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end if;
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-- force break
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if (skctl_reg(7) = '1') then
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serial_out_next <= '0';
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end if;
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-- register to load has been written too, update our state to reflect that it is full
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if (serout_holding_load = '1') then
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Also available in: Unified diff
noise delay between channels. Apply force break to two tone.