Revision 165
Added by markw almost 11 years ago
| mist/pll.qip | ||
|---|---|---|
|
set_global_assignment -name IP_TOOL_NAME "ALTPLL"
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set_global_assignment -name IP_TOOL_VERSION "13.0"
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set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll.vhd"]
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set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.bsf"]
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set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.cmp"]
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set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"]
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| mist/pll.bsf | ||
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/*
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WARNING: Do NOT edit the input and output ports in this file in a text
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editor if you plan to continue editing the block that represents it in
|
||
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the Block Editor! File corruption is VERY likely to occur.
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||
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*/
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/*
|
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|
Copyright (C) 1991-2013 Altera Corporation
|
||
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Your use of Altera Corporation's design tools, logic functions
|
||
|
and other software and tools, and its AMPP partner logic
|
||
|
functions, and any output files from any of the foregoing
|
||
|
(including device programming or simulation files), and any
|
||
|
associated documentation or information are expressly subject
|
||
|
to the terms and conditions of the Altera Program License
|
||
|
Subscription Agreement, Altera MegaCore Function License
|
||
|
Agreement, or other applicable license agreement, including,
|
||
|
without limitation, that your use is for the sole purpose of
|
||
|
programming logic devices manufactured by Altera and sold by
|
||
|
Altera or its authorized distributors. Please refer to the
|
||
|
applicable agreement for further details.
|
||
|
*/
|
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(header "symbol" (version "1.2"))
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(symbol
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(rect 0 0 224 168)
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(text "pll" (rect 106 0 120 11)(font "Arial" (font_size 10)))
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(text "inst" (rect 8 157 22 164)(font "Arial" ))
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(port
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(pt 0 64)
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(input)
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(text "inclk0" (rect 0 0 22 9)(font "Arial" (font_size 8)))
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(text "inclk0" (rect 4 55 21 63)(font "Arial" (font_size 8)))
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(line (pt 0 64)(pt 40 64))
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)
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(port
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(pt 224 64)
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(output)
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(text "c0" (rect 0 0 9 9)(font "Arial" (font_size 8)))
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(text "c0" (rect 212 55 218 63)(font "Arial" (font_size 8)))
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)
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(port
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(pt 224 80)
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(output)
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(text "c1" (rect 0 0 9 9)(font "Arial" (font_size 8)))
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(text "c1" (rect 212 71 218 79)(font "Arial" (font_size 8)))
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)
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(port
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(pt 224 96)
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(output)
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(text "c2" (rect 0 0 9 9)(font "Arial" (font_size 8)))
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(text "c2" (rect 212 87 219 95)(font "Arial" (font_size 8)))
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)
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(port
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(pt 224 112)
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(output)
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(text "c3" (rect 0 0 9 9)(font "Arial" (font_size 8)))
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(text "c3" (rect 212 103 218 111)(font "Arial" (font_size 8)))
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)
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(port
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(pt 224 128)
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(output)
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(text "locked" (rect 0 0 24 9)(font "Arial" (font_size 8)))
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(text "locked" (rect 199 119 219 127)(font "Arial" (font_size 8)))
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)
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(drawing
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(text "Cyclone III" (rect 181 161 394 328)(font "Arial" ))
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(text "inclk0 frequency: 27.000 MHz" (rect 50 71 191 148)(font "Arial" ))
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(text "Operation Mode: Normal" (rect 50 79 175 164)(font "Arial" ))
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(text "Clk " (rect 51 92 112 190)(font "Arial" ))
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(text "Ratio" (rect 74 92 163 190)(font "Arial" ))
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(text "Ph (dg)" (rect 102 92 226 190)(font "Arial" ))
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(text "DC (%)" (rect 129 92 279 190)(font "Arial" ))
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(text "c0" (rect 53 101 112 208)(font "Arial" ))
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(text "69/16" (rect 73 101 162 208)(font "Arial" ))
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(text "0.00" (rect 106 101 224 208)(font "Arial" ))
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(text "50.00" (rect 131 101 278 208)(font "Arial" ))
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(text "c1" (rect 53 110 112 226)(font "Arial" ))
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(text "69/32" (rect 73 110 163 226)(font "Arial" ))
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(text "0.00" (rect 106 110 224 226)(font "Arial" ))
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(text "50.00" (rect 131 110 278 226)(font "Arial" ))
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(text "c2" (rect 53 119 113 244)(font "Arial" ))
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(text "69/16" (rect 73 119 162 244)(font "Arial" ))
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(text "-100.60" (rect 101 119 224 244)(font "Arial" ))
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(text "50.00" (rect 131 119 278 244)(font "Arial" ))
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(text "c3" (rect 53 128 112 262)(font "Arial" ))
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(text "23/32768" (rect 67 128 162 262)(font "Arial" ))
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(text "0.00" (rect 106 128 224 262)(font "Arial" ))
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(text "50.00" (rect 131 128 278 262)(font "Arial" ))
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(line (pt 0 0)(pt 225 0))
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(line (pt 225 0)(pt 225 170))
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(line (pt 0 170)(pt 225 170))
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(line (pt 0 0)(pt 0 170))
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(line (pt 48 90)(pt 152 90))
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(line (pt 48 98)(pt 152 98))
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(line (pt 48 107)(pt 152 107))
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(line (pt 48 116)(pt 152 116))
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(line (pt 48 125)(pt 152 125))
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(line (pt 48 134)(pt 152 134))
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(line (pt 48 90)(pt 48 134))
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(line (pt 64 90)(pt 64 134)(line_width 3))
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(line (pt 98 90)(pt 98 134)(line_width 3))
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(line (pt 126 90)(pt 126 134)(line_width 3))
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(line (pt 151 90)(pt 151 134))
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(line (pt 40 48)(pt 183 48))
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(line (pt 183 48)(pt 183 152))
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(line (pt 40 152)(pt 183 152))
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(line (pt 40 48)(pt 40 152))
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(line (pt 223 64)(pt 183 64))
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(line (pt 223 80)(pt 183 80))
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(line (pt 223 96)(pt 183 96))
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(line (pt 223 112)(pt 183 112))
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(line (pt 223 128)(pt 183 128))
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)
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)
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| mist/pll.cmp | ||
|---|---|---|
|
--Copyright (C) 1991-2013 Altera Corporation
|
||
|
--Your use of Altera Corporation's design tools, logic functions
|
||
|
--and other software and tools, and its AMPP partner logic
|
||
|
--functions, and any output files from any of the foregoing
|
||
|
--(including device programming or simulation files), and any
|
||
|
--associated documentation or information are expressly subject
|
||
|
--to the terms and conditions of the Altera Program License
|
||
|
--Subscription Agreement, Altera MegaCore Function License
|
||
|
--Agreement, or other applicable license agreement, including,
|
||
|
--without limitation, that your use is for the sole purpose of
|
||
|
--programming logic devices manufactured by Altera and sold by
|
||
|
--Altera or its authorized distributors. Please refer to the
|
||
|
--applicable agreement for further details.
|
||
|
|
||
|
|
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component pll
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PORT
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(
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inclk0 : IN STD_LOGIC := '0';
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c0 : OUT STD_LOGIC ;
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c1 : OUT STD_LOGIC ;
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c2 : OUT STD_LOGIC ;
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c3 : OUT STD_LOGIC ;
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locked : OUT STD_LOGIC
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);
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end component;
|
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| mist/pll.vhd | ||
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-- megafunction wizard: %ALTPLL%
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-- GENERATION: STANDARD
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-- VERSION: WM1.0
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-- MODULE: altpll
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-- ============================================================
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-- File Name: pll.vhd
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-- Megafunction Name(s):
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-- altpll
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--
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-- Simulation Library Files(s):
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-- altera_mf
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-- ============================================================
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-- ************************************************************
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-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||
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--
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-- 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
|
||
|
-- ************************************************************
|
||
|
|
||
|
|
||
|
--Copyright (C) 1991-2013 Altera Corporation
|
||
|
--Your use of Altera Corporation's design tools, logic functions
|
||
|
--and other software and tools, and its AMPP partner logic
|
||
|
--functions, and any output files from any of the foregoing
|
||
|
--(including device programming or simulation files), and any
|
||
|
--associated documentation or information are expressly subject
|
||
|
--to the terms and conditions of the Altera Program License
|
||
|
--Subscription Agreement, Altera MegaCore Function License
|
||
|
--Agreement, or other applicable license agreement, including,
|
||
|
--without limitation, that your use is for the sole purpose of
|
||
|
--programming logic devices manufactured by Altera and sold by
|
||
|
--Altera or its authorized distributors. Please refer to the
|
||
|
--applicable agreement for further details.
|
||
|
|
||
|
|
||
|
LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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LIBRARY altera_mf;
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USE altera_mf.all;
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ENTITY pll IS
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PORT
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||
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(
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inclk0 : IN STD_LOGIC := '0';
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c0 : OUT STD_LOGIC ;
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c1 : OUT STD_LOGIC ;
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c2 : OUT STD_LOGIC ;
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c3 : OUT STD_LOGIC ;
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locked : OUT STD_LOGIC
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);
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END pll;
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ARCHITECTURE SYN OF pll IS
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SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0);
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SIGNAL sub_wire1 : STD_LOGIC ;
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SIGNAL sub_wire2 : STD_LOGIC ;
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SIGNAL sub_wire3 : STD_LOGIC ;
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SIGNAL sub_wire4 : STD_LOGIC ;
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SIGNAL sub_wire5 : STD_LOGIC ;
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SIGNAL sub_wire6 : STD_LOGIC ;
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SIGNAL sub_wire7 : STD_LOGIC_VECTOR (1 DOWNTO 0);
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SIGNAL sub_wire8_bv : BIT_VECTOR (0 DOWNTO 0);
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SIGNAL sub_wire8 : STD_LOGIC_VECTOR (0 DOWNTO 0);
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COMPONENT altpll
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GENERIC (
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bandwidth_type : STRING;
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clk0_divide_by : NATURAL;
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clk0_duty_cycle : NATURAL;
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clk0_multiply_by : NATURAL;
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clk0_phase_shift : STRING;
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clk1_divide_by : NATURAL;
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clk1_duty_cycle : NATURAL;
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clk1_multiply_by : NATURAL;
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clk1_phase_shift : STRING;
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clk2_divide_by : NATURAL;
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clk2_duty_cycle : NATURAL;
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clk2_multiply_by : NATURAL;
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clk2_phase_shift : STRING;
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clk3_divide_by : NATURAL;
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clk3_duty_cycle : NATURAL;
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clk3_multiply_by : NATURAL;
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clk3_phase_shift : STRING;
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compensate_clock : STRING;
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inclk0_input_frequency : NATURAL;
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intended_device_family : STRING;
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lpm_hint : STRING;
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lpm_type : STRING;
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operation_mode : STRING;
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pll_type : STRING;
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port_activeclock : STRING;
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port_areset : STRING;
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port_clkbad0 : STRING;
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port_clkbad1 : STRING;
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port_clkloss : STRING;
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port_clkswitch : STRING;
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port_configupdate : STRING;
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port_fbin : STRING;
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port_inclk0 : STRING;
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port_inclk1 : STRING;
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port_locked : STRING;
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port_pfdena : STRING;
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port_phasecounterselect : STRING;
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port_phasedone : STRING;
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port_phasestep : STRING;
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port_phaseupdown : STRING;
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port_pllena : STRING;
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port_scanaclr : STRING;
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port_scanclk : STRING;
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port_scanclkena : STRING;
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port_scandata : STRING;
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port_scandataout : STRING;
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port_scandone : STRING;
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port_scanread : STRING;
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port_scanwrite : STRING;
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port_clk0 : STRING;
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port_clk1 : STRING;
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port_clk2 : STRING;
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port_clk3 : STRING;
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port_clk4 : STRING;
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port_clk5 : STRING;
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port_clkena0 : STRING;
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port_clkena1 : STRING;
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port_clkena2 : STRING;
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port_clkena3 : STRING;
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port_clkena4 : STRING;
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port_clkena5 : STRING;
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port_extclk0 : STRING;
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port_extclk1 : STRING;
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port_extclk2 : STRING;
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port_extclk3 : STRING;
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self_reset_on_loss_lock : STRING;
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width_clock : NATURAL
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);
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PORT (
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clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
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inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
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locked : OUT STD_LOGIC
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||
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);
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END COMPONENT;
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BEGIN
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sub_wire8_bv(0 DOWNTO 0) <= "0";
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sub_wire8 <= To_stdlogicvector(sub_wire8_bv);
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sub_wire5 <= sub_wire0(2);
|
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sub_wire4 <= sub_wire0(0);
|
||
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sub_wire2 <= sub_wire0(3);
|
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sub_wire1 <= sub_wire0(1);
|
||
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c1 <= sub_wire1;
|
||
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c3 <= sub_wire2;
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||
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locked <= sub_wire3;
|
||
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c0 <= sub_wire4;
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c2 <= sub_wire5;
|
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sub_wire6 <= inclk0;
|
||
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sub_wire7 <= sub_wire8(0 DOWNTO 0) & sub_wire6;
|
||
|
|
||
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altpll_component : altpll
|
||
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GENERIC MAP (
|
||
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bandwidth_type => "AUTO",
|
||
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clk0_divide_by => 16,
|
||
|
clk0_duty_cycle => 50,
|
||
|
clk0_multiply_by => 69,
|
||
|
clk0_phase_shift => "0",
|
||
|
clk1_divide_by => 32,
|
||
|
clk1_duty_cycle => 50,
|
||
|
clk1_multiply_by => 69,
|
||
|
clk1_phase_shift => "0",
|
||
|
clk2_divide_by => 16,
|
||
|
clk2_duty_cycle => 50,
|
||
|
clk2_multiply_by => 69,
|
||
|
clk2_phase_shift => "-2400",
|
||
|
clk3_divide_by => 32768,
|
||
|
clk3_duty_cycle => 50,
|
||
|
clk3_multiply_by => 23,
|
||
|
clk3_phase_shift => "0",
|
||
|
compensate_clock => "CLK0",
|
||
|
inclk0_input_frequency => 37037,
|
||
|
intended_device_family => "Cyclone III",
|
||
|
lpm_hint => "CBX_MODULE_PREFIX=pll",
|
||
|
lpm_type => "altpll",
|
||
|
operation_mode => "NORMAL",
|
||
|
pll_type => "AUTO",
|
||
|
port_activeclock => "PORT_UNUSED",
|
||
|
port_areset => "PORT_UNUSED",
|
||
|
port_clkbad0 => "PORT_UNUSED",
|
||
|
port_clkbad1 => "PORT_UNUSED",
|
||
|
port_clkloss => "PORT_UNUSED",
|
||
|
port_clkswitch => "PORT_UNUSED",
|
||
|
port_configupdate => "PORT_UNUSED",
|
||
|
port_fbin => "PORT_UNUSED",
|
||
|
port_inclk0 => "PORT_USED",
|
||
|
port_inclk1 => "PORT_UNUSED",
|
||
|
port_locked => "PORT_USED",
|
||
|
port_pfdena => "PORT_UNUSED",
|
||
|
port_phasecounterselect => "PORT_UNUSED",
|
||
|
port_phasedone => "PORT_UNUSED",
|
||
|
port_phasestep => "PORT_UNUSED",
|
||
|
port_phaseupdown => "PORT_UNUSED",
|
||
|
port_pllena => "PORT_UNUSED",
|
||
|
port_scanaclr => "PORT_UNUSED",
|
||
|
port_scanclk => "PORT_UNUSED",
|
||
|
port_scanclkena => "PORT_UNUSED",
|
||
|
port_scandata => "PORT_UNUSED",
|
||
|
port_scandataout => "PORT_UNUSED",
|
||
|
port_scandone => "PORT_UNUSED",
|
||
|
port_scanread => "PORT_UNUSED",
|
||
|
port_scanwrite => "PORT_UNUSED",
|
||
|
port_clk0 => "PORT_USED",
|
||
|
port_clk1 => "PORT_USED",
|
||
|
port_clk2 => "PORT_USED",
|
||
|
port_clk3 => "PORT_USED",
|
||
|
port_clk4 => "PORT_UNUSED",
|
||
|
port_clk5 => "PORT_UNUSED",
|
||
|
port_clkena0 => "PORT_UNUSED",
|
||
|
port_clkena1 => "PORT_UNUSED",
|
||
|
port_clkena2 => "PORT_UNUSED",
|
||
|
port_clkena3 => "PORT_UNUSED",
|
||
|
port_clkena4 => "PORT_UNUSED",
|
||
|
port_clkena5 => "PORT_UNUSED",
|
||
|
port_extclk0 => "PORT_UNUSED",
|
||
|
port_extclk1 => "PORT_UNUSED",
|
||
|
port_extclk2 => "PORT_UNUSED",
|
||
|
port_extclk3 => "PORT_UNUSED",
|
||
|
self_reset_on_loss_lock => "OFF",
|
||
|
width_clock => 5
|
||
|
)
|
||
|
PORT MAP (
|
||
|
inclk => sub_wire7,
|
||
|
clk => sub_wire0,
|
||
|
locked => sub_wire3
|
||
|
);
|
||
|
|
||
|
|
||
|
|
||
|
END SYN;
|
||
|
|
||
|
-- ============================================================
|
||
|
-- CNX file retrieval info
|
||
|
-- ============================================================
|
||
|
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
|
||
|
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
|
||
|
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
|
||
|
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
|
||
|
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
|
||
|
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
|
||
|
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
|
||
|
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
|
||
|
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
|
||
|
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "1"
|
||
|
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
|
||
|
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
|
||
|
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
|
||
|
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
|
||
|
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
|
||
|
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
|
||
|
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "16"
|
||
|
-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "32"
|
||
|
-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "16"
|
||
|
-- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "32768"
|
||
|
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
|
||
|
-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
|
||
|
-- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
|
||
|
-- Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000"
|
||
|
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "116.437500"
|
||
|
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "58.218750"
|
||
|
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "116.437500"
|
||
|
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "0.018951"
|
||
|
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
|
||
|
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
|
||
|
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
|
||
|
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
|
||
|
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "1"
|
||
|
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
|
||
|
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
|
||
|
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"
|
||
|
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
|
||
|
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
|
||
|
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
|
||
|
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
|
||
|
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
|
||
|
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||
|
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
|
||
|
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
|
||
|
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
|
||
|
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
|
||
|
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
|
||
|
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
|
||
|
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
|
||
|
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps"
|
||
|
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "ps"
|
||
|
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
|
||
|
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
|
||
|
-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
|
||
|
-- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
|
||
|
-- Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0"
|
||
|
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "69"
|
||
|
-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "69"
|
||
|
-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "69"
|
||
|
-- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "23"
|
||
|
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
|
||
|
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "57.40000000"
|
||
|
-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "57.50000000"
|
||
|
-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "57.50000000"
|
||
|
-- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "100.00000000"
|
||
|
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
|
||
|
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
|
||
|
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
|
||
|
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "0"
|
||
|
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
|
||
|
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
|
||
|
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
|
||
|
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz"
|
||
|
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
|
||
|
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
|
||
|
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
|
||
|
-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
|
||
|
-- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "-2.40000000"
|
||
|
-- Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "0.00000000"
|
||
|
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
|
||
|
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
|
||
|
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ns"
|
||
|
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ns"
|
||
|
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "ps"
|
||
|
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
|
||
|
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
|
||
|
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
|
||
|
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
|
||
|
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
|
||
|
-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
|
||
|
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
|
||
|
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
|
||
|
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
|
||
|
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
|
||
|
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
|
||
|
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
|
||
|
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
|
||
|
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
|
||
|
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
|
||
|
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
|
||
|
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
|
||
|
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
|
||
|
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
|
||
|
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
|
||
|
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
|
||
|
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
|
||
|
-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
|
||
|
-- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
|
||
|
-- Retrieval info: PRIVATE: STICKY_CLK3 STRING "1"
|
||
|
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
|
||
|
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
|
||
|
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
||
|
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
|
||
|
-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
|
||
|
-- Retrieval info: PRIVATE: USE_CLK2 STRING "1"
|
||
|
-- Retrieval info: PRIVATE: USE_CLK3 STRING "1"
|
||
|
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
|
||
|
-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
|
||
|
-- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
|
||
|
-- Retrieval info: PRIVATE: USE_CLKENA3 STRING "0"
|
||
|
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
|
||
|
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
|
||
|
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
|
||
|
-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
|
||
|
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "16"
|
||
|
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
|
||
|
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "69"
|
||
|
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
|
||
|
-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "32"
|
||
|
-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
|
||
|
-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "69"
|
||
|
-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
|
||
|
-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "16"
|
||
|
-- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
|
||
|
-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "69"
|
||
|
-- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "-2400"
|
||
|
-- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "32768"
|
||
|
-- Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50"
|
||
|
-- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "23"
|
||
|
-- Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0"
|
||
|
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
|
||
|
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
|
||
|
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||
|
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
|
||
|
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
|
||
|
-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
|
||
|
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
|
||
|
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
|
||
|
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
|
||
|
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
|
||
|
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
|
||
|
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
|
||
|
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
|
||
|
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
|
||
|
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
|
||
|
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
|
||
|
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
|
||
|
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
|
||
|
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
|
||
|
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
|
||
|
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
|
||
|
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
|
||
|
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
|
||
|
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
|
||
|
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
|
||
|
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
|
||
|
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
|
||
|
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
|
||
|
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
|
||
|
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
|
||
|
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
|
||
|
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
|
||
|
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
|
||
|
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
|
||
|
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED"
|
||
|
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
|
||
|
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
|
||
|
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
|
||
|
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
|
||
|
-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
|
||
|
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
|
||
|
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
|
||
|
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
|
||
|
-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
|
||
|
-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
|
||
|
-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
|
||
|
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
|
||
|
-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
|
||
|
-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
|
||
|
-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
|
||
|
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
|
||
|
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
|
||
|
-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
|
||
|
-- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
|
||
|
-- Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3"
|
||
|
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
|
||
|
-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
|
||
|
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
|
||
|
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
|
||
|
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
|
||
|
-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
|
||
|
-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
|
||
|
-- Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3
|
||
|
-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
|
||
|
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE
|
||
|
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
|
||
|
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE
|
||
|
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp TRUE
|
||
|
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf TRUE
|
||
|
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.vhd FALSE
|
||
|
-- Retrieval info: LIB_FILE: altera_mf
|
||
|
-- Retrieval info: CBX_MODULE_PREFIX: ON
|
||
| mist/pll.ppf | ||
|---|---|---|
|
<?xml version="1.0" encoding="UTF-8" ?>
|
||
|
<!DOCTYPE pinplan>
|
||
|
<pinplan intended_family="Cyclone III" variation_name="pll" megafunction_name="ALTPLL" specifies="all_ports">
|
||
|
<global>
|
||
|
<pin name="inclk0" direction="input" scope="external" source="clock" />
|
||
|
<pin name="c0" direction="output" scope="external" source="clock" />
|
||
|
<pin name="c1" direction="output" scope="external" source="clock" />
|
||
|
<pin name="c2" direction="output" scope="external" source="clock" />
|
||
|
<pin name="c3" direction="output" scope="external" source="clock" />
|
||
|
<pin name="locked" direction="output" scope="external" />
|
||
|
|
||
|
</global>
|
||
|
</pinplan>
|
||
| mist/atari800core.qsf | ||
|---|---|---|
|
set_global_assignment -name QIP_FILE mist_sector_buffer.qip
|
||
|
set_global_assignment -name VHDL_FILE atari800core_mist.vhd
|
||
|
set_global_assignment -name VERILOG_FILE user_io.v
|
||
|
set_global_assignment -name QIP_FILE pll.qip
|
||
|
set_global_assignment -name QIP_FILE pll_pal.qip
|
||
|
set_global_assignment -name QIP_FILE pll_ntsc.qip
|
||
|
|
||
| mist/atari800core_mist.vhd | ||
|---|---|---|
|
dac_out => audio_r
|
||
|
);
|
||
|
|
||
|
mist_pll : entity work.pll
|
||
|
gen_ntsc_pll : if tv=0 generate
|
||
|
mist_pll : entity work.pll_ntsc
|
||
|
PORT MAP(inclk0 => CLOCK_27(0),
|
||
|
c0 => CLK_SDRAM,
|
||
|
c1 => CLK,
|
||
|
c2 => SDRAM_CLK,
|
||
|
c3 => SLOW_PS2_CLK,
|
||
|
locked => PLL_LOCKED);
|
||
|
end generate;
|
||
|
|
||
|
gen_pal_pll : if tv=1 generate
|
||
|
mist_pll : entity work.pll_pal
|
||
|
PORT MAP(inclk0 => CLOCK_27(0),
|
||
|
c0 => CLK_SDRAM,
|
||
|
c1 => CLK,
|
||
|
c2 => SDRAM_CLK,
|
||
|
c3 => SLOW_PS2_CLK,
|
||
|
locked => PLL_LOCKED);
|
||
|
end generate;
|
||
|
|
||
|
reset_n <= PLL_LOCKED;
|
||
|
|
||
|
atarixl_simple_sdram1 : entity work.atari800core_simple_sdram
|
||
| mist/pll_ntsc.cmp | ||
|---|---|---|
|
--Copyright (C) 1991-2013 Altera Corporation
|
||
|
--Your use of Altera Corporation's design tools, logic functions
|
||
|
--and other software and tools, and its AMPP partner logic
|
||
|
--functions, and any output files from any of the foregoing
|
||
|
--(including device programming or simulation files), and any
|
||
|
--associated documentation or information are expressly subject
|
||
|
--to the terms and conditions of the Altera Program License
|
||
|
--Subscription Agreement, Altera MegaCore Function License
|
||
|
--Agreement, or other applicable license agreement, including,
|
||
|
--without limitation, that your use is for the sole purpose of
|
||
|
--programming logic devices manufactured by Altera and sold by
|
||
|
--Altera or its authorized distributors. Please refer to the
|
||
|
--applicable agreement for further details.
|
||
|
|
||
|
|
||
|
component pll_ntsc
|
||
|
PORT
|
||
|
(
|
||
|
inclk0 : IN STD_LOGIC := '0';
|
||
|
c0 : OUT STD_LOGIC ;
|
||
|
c1 : OUT STD_LOGIC ;
|
||
|
c2 : OUT STD_LOGIC ;
|
||
|
c3 : OUT STD_LOGIC ;
|
||
|
locked : OUT STD_LOGIC
|
||
|
);
|
||
|
end component;
|
||
| mist/pll_ntsc.ppf | ||
|---|---|---|
|
<?xml version="1.0" encoding="UTF-8" ?>
|
||
|
<!DOCTYPE pinplan>
|
||
|
<pinplan intended_family="Cyclone III" variation_name="pll_ntsc" megafunction_name="ALTPLL" specifies="all_ports">
|
||
|
<global>
|
||
|
<pin name="inclk0" direction="input" scope="external" source="clock" />
|
||
|
<pin name="c0" direction="output" scope="external" source="clock" />
|
||
|
<pin name="c1" direction="output" scope="external" source="clock" />
|
||
|
<pin name="c2" direction="output" scope="external" source="clock" />
|
||
|
<pin name="c3" direction="output" scope="external" source="clock" />
|
||
|
<pin name="locked" direction="output" scope="external" />
|
||
|
|
||
|
</global>
|
||
|
</pinplan>
|
||
| mist/pll_ntsc.qip | ||
|---|---|---|
|
set_global_assignment -name IP_TOOL_NAME "ALTPLL"
|
||
|
set_global_assignment -name IP_TOOL_VERSION "13.0"
|
||
|
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll_ntsc.vhd"]
|
||
|
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_ntsc.cmp"]
|
||
|
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_ntsc.ppf"]
|
||
| mist/pll_ntsc.vhd | ||
|---|---|---|
|
-- megafunction wizard: %ALTPLL%
|
||
|
-- GENERATION: STANDARD
|
||
|
-- VERSION: WM1.0
|
||
|
-- MODULE: altpll
|
||
|
|
||
|
-- ============================================================
|
||
|
-- File Name: pll_ntsc.vhd
|
||
|
-- Megafunction Name(s):
|
||
|
-- altpll
|
||
|
--
|
||
|
-- Simulation Library Files(s):
|
||
|
-- altera_mf
|
||
|
-- ============================================================
|
||
|
-- ************************************************************
|
||
|
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||
|
--
|
||
|
-- 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
|
||
|
-- ************************************************************
|
||
|
|
||
|
|
||
|
--Copyright (C) 1991-2013 Altera Corporation
|
||
|
--Your use of Altera Corporation's design tools, logic functions
|
||
|
--and other software and tools, and its AMPP partner logic
|
||
|
--functions, and any output files from any of the foregoing
|
||
|
--(including device programming or simulation files), and any
|
||
|
--associated documentation or information are expressly subject
|
||
|
--to the terms and conditions of the Altera Program License
|
||
|
--Subscription Agreement, Altera MegaCore Function License
|
||
|
--Agreement, or other applicable license agreement, including,
|
||
|
--without limitation, that your use is for the sole purpose of
|
||
|
--programming logic devices manufactured by Altera and sold by
|
||
|
--Altera or its authorized distributors. Please refer to the
|
||
|
--applicable agreement for further details.
|
||
|
|
||
|
|
||
|
LIBRARY ieee;
|
||
|
USE ieee.std_logic_1164.all;
|
||
|
|
||
|
LIBRARY altera_mf;
|
||
|
USE altera_mf.all;
|
||
|
|
||
|
ENTITY pll_ntsc IS
|
||
|
PORT
|
||
|
(
|
||
|
inclk0 : IN STD_LOGIC := '0';
|
||
|
c0 : OUT STD_LOGIC ;
|
||
|
c1 : OUT STD_LOGIC ;
|
||
|
c2 : OUT STD_LOGIC ;
|
||
|
c3 : OUT STD_LOGIC ;
|
||
|
locked : OUT STD_LOGIC
|
||
|
);
|
||
|
END pll_ntsc;
|
||
|
|
||
|
|
||
|
ARCHITECTURE SYN OF pll_ntsc IS
|
||
|
|
||
|
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0);
|
||
|
SIGNAL sub_wire1 : STD_LOGIC ;
|
||
|
SIGNAL sub_wire2 : STD_LOGIC ;
|
||
|
SIGNAL sub_wire3 : STD_LOGIC ;
|
||
|
SIGNAL sub_wire4 : STD_LOGIC ;
|
||
|
SIGNAL sub_wire5 : STD_LOGIC ;
|
||
|
SIGNAL sub_wire6 : STD_LOGIC ;
|
||
|
SIGNAL sub_wire7 : STD_LOGIC_VECTOR (1 DOWNTO 0);
|
||
|
SIGNAL sub_wire8_bv : BIT_VECTOR (0 DOWNTO 0);
|
||
|
SIGNAL sub_wire8 : STD_LOGIC_VECTOR (0 DOWNTO 0);
|
||
|
|
||
|
|
||
|
|
||
|
COMPONENT altpll
|
||
|
GENERIC (
|
||
|
bandwidth_type : STRING;
|
||
|
clk0_divide_by : NATURAL;
|
||
|
clk0_duty_cycle : NATURAL;
|
||
|
clk0_multiply_by : NATURAL;
|
||
|
clk0_phase_shift : STRING;
|
||
|
clk1_divide_by : NATURAL;
|
||
|
clk1_duty_cycle : NATURAL;
|
||
|
clk1_multiply_by : NATURAL;
|
||
|
clk1_phase_shift : STRING;
|
||
|
clk2_divide_by : NATURAL;
|
||
|
clk2_duty_cycle : NATURAL;
|
||
|
clk2_multiply_by : NATURAL;
|
||
|
clk2_phase_shift : STRING;
|
||
|
clk3_divide_by : NATURAL;
|
||
|
clk3_duty_cycle : NATURAL;
|
||
|
clk3_multiply_by : NATURAL;
|
||
|
clk3_phase_shift : STRING;
|
||
|
compensate_clock : STRING;
|
||
|
inclk0_input_frequency : NATURAL;
|
||
|
intended_device_family : STRING;
|
||
|
lpm_hint : STRING;
|
||
|
lpm_type : STRING;
|
||
|
operation_mode : STRING;
|
||
|
pll_type : STRING;
|
||
|
port_activeclock : STRING;
|
||
|
port_areset : STRING;
|
||
|
port_clkbad0 : STRING;
|
||
|
port_clkbad1 : STRING;
|
||
|
port_clkloss : STRING;
|
||
|
port_clkswitch : STRING;
|
||
|
port_configupdate : STRING;
|
||
|
port_fbin : STRING;
|
||
|
port_inclk0 : STRING;
|
||
|
port_inclk1 : STRING;
|
||
|
port_locked : STRING;
|
||
|
port_pfdena : STRING;
|
||
|
port_phasecounterselect : STRING;
|
||
|
port_phasedone : STRING;
|
||
|
port_phasestep : STRING;
|
||
|
port_phaseupdown : STRING;
|
||
|
port_pllena : STRING;
|
||
|
port_scanaclr : STRING;
|
||
|
port_scanclk : STRING;
|
||
|
port_scanclkena : STRING;
|
||
|
port_scandata : STRING;
|
||
|
port_scandataout : STRING;
|
||
|
port_scandone : STRING;
|
||
|
port_scanread : STRING;
|
||
|
port_scanwrite : STRING;
|
||
|
port_clk0 : STRING;
|
||
|
port_clk1 : STRING;
|
||
|
port_clk2 : STRING;
|
||
|
port_clk3 : STRING;
|
||
|
port_clk4 : STRING;
|
||
|
port_clk5 : STRING;
|
||
|
port_clkena0 : STRING;
|
||
|
port_clkena1 : STRING;
|
||
|
port_clkena2 : STRING;
|
||
|
port_clkena3 : STRING;
|
||
|
port_clkena4 : STRING;
|
||
|
port_clkena5 : STRING;
|
||
|
port_extclk0 : STRING;
|
||
|
port_extclk1 : STRING;
|
||
|
port_extclk2 : STRING;
|
||
|
port_extclk3 : STRING;
|
||
|
self_reset_on_loss_lock : STRING;
|
||
|
width_clock : NATURAL
|
||
|
);
|
||
|
PORT (
|
||
|
clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
|
||
|
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
|
||
|
locked : OUT STD_LOGIC
|
||
|
);
|
||
|
END COMPONENT;
|
||
|
|
||
|
BEGIN
|
||
|
sub_wire8_bv(0 DOWNTO 0) <= "0";
|
||
|
sub_wire8 <= To_stdlogicvector(sub_wire8_bv);
|
||
|
sub_wire5 <= sub_wire0(2);
|
||
|
sub_wire4 <= sub_wire0(0);
|
||
|
sub_wire2 <= sub_wire0(3);
|
||
|
sub_wire1 <= sub_wire0(1);
|
||
|
c1 <= sub_wire1;
|
||
|
c3 <= sub_wire2;
|
||
|
locked <= sub_wire3;
|
||
|
c0 <= sub_wire4;
|
||
|
c2 <= sub_wire5;
|
||
|
sub_wire6 <= inclk0;
|
||
|
sub_wire7 <= sub_wire8(0 DOWNTO 0) & sub_wire6;
|
||
|
|
||
|
altpll_component : altpll
|
||
|
GENERIC MAP (
|
||
|
bandwidth_type => "AUTO",
|
||
|
clk0_divide_by => 33,
|
||
|
clk0_duty_cycle => 50,
|
||
|
clk0_multiply_by => 140,
|
||
|
clk0_phase_shift => "0",
|
||
|
clk1_divide_by => 33,
|
||
|
clk1_duty_cycle => 50,
|
||
|
clk1_multiply_by => 70,
|
||
|
clk1_phase_shift => "0",
|
||
|
clk2_divide_by => 33,
|
||
|
clk2_duty_cycle => 50,
|
||
|
clk2_multiply_by => 140,
|
||
|
clk2_phase_shift => "-2400",
|
||
|
clk3_divide_by => 270,
|
||
|
clk3_duty_cycle => 50,
|
||
|
clk3_multiply_by => 1,
|
||
|
clk3_phase_shift => "0",
|
||
|
compensate_clock => "CLK0",
|
||
|
inclk0_input_frequency => 37037,
|
||
|
intended_device_family => "Cyclone III",
|
||
|
lpm_hint => "CBX_MODULE_PREFIX=pll_ntsc",
|
||
|
lpm_type => "altpll",
|
||
|
operation_mode => "NORMAL",
|
||
|
pll_type => "AUTO",
|
||
|
port_activeclock => "PORT_UNUSED",
|
||
|
port_areset => "PORT_UNUSED",
|
||
|
port_clkbad0 => "PORT_UNUSED",
|
||
|
port_clkbad1 => "PORT_UNUSED",
|
||
|
port_clkloss => "PORT_UNUSED",
|
||
|
port_clkswitch => "PORT_UNUSED",
|
||
|
port_configupdate => "PORT_UNUSED",
|
||
|
port_fbin => "PORT_UNUSED",
|
||
|
port_inclk0 => "PORT_USED",
|
||
|
port_inclk1 => "PORT_UNUSED",
|
||
|
port_locked => "PORT_USED",
|
||
|
port_pfdena => "PORT_UNUSED",
|
||
|
port_phasecounterselect => "PORT_UNUSED",
|
||
|
port_phasedone => "PORT_UNUSED",
|
||
|
port_phasestep => "PORT_UNUSED",
|
||
|
port_phaseupdown => "PORT_UNUSED",
|
||
|
port_pllena => "PORT_UNUSED",
|
||
|
port_scanaclr => "PORT_UNUSED",
|
||
|
port_scanclk => "PORT_UNUSED",
|
||
|
port_scanclkena => "PORT_UNUSED",
|
||
|
port_scandata => "PORT_UNUSED",
|
||
|
port_scandataout => "PORT_UNUSED",
|
||
|
port_scandone => "PORT_UNUSED",
|
||
|
port_scanread => "PORT_UNUSED",
|
||
|
port_scanwrite => "PORT_UNUSED",
|
||
|
port_clk0 => "PORT_USED",
|
||
|
port_clk1 => "PORT_USED",
|
||
|
port_clk2 => "PORT_USED",
|
||
|
port_clk3 => "PORT_USED",
|
||
|
port_clk4 => "PORT_UNUSED",
|
||
|
port_clk5 => "PORT_UNUSED",
|
||
|
port_clkena0 => "PORT_UNUSED",
|
||
|
port_clkena1 => "PORT_UNUSED",
|
||
|
port_clkena2 => "PORT_UNUSED",
|
||
|
port_clkena3 => "PORT_UNUSED",
|
||
|
port_clkena4 => "PORT_UNUSED",
|
||
|
port_clkena5 => "PORT_UNUSED",
|
||
|
port_extclk0 => "PORT_UNUSED",
|
||
|
port_extclk1 => "PORT_UNUSED",
|
||
|
port_extclk2 => "PORT_UNUSED",
|
||
|
port_extclk3 => "PORT_UNUSED",
|
||
|
self_reset_on_loss_lock => "OFF",
|
||
|
width_clock => 5
|
||
|
)
|
||
|
PORT MAP (
|
||
|
inclk => sub_wire7,
|
||
|
clk => sub_wire0,
|
||
|
locked => sub_wire3
|
||
|
);
|
||
|
|
||
|
|
||
|
|
||
|
END SYN;
|
||
|
|
||
|
-- ============================================================
|
||
|
-- CNX file retrieval info
|
||
|
-- ============================================================
|
||
|
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
|
||
|
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
|
||
|
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
|
||
|
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
|
||
|
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
|
||
|
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
|
||
|
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
|
||
|
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
|
||
|
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
|
||
|
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "1"
|
||
|
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
|
||
|
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
|
||
|
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
|
||
|
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
|
||
|
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
|
||
|
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
|
||
|
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "33"
|
||
|
-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "33"
|
||
|
-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "33"
|
||
|
-- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "32768"
|
||
|
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
|
||
|
-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
|
||
|
-- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
|
||
|
-- Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000"
|
||
|
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "114.545456"
|
||
|
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "57.272728"
|
||
|
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "114.545456"
|
||
|
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "0.100000"
|
||
|
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
|
||
|
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
|
||
|
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
|
||
|
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
|
||
|
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "1"
|
||
|
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
|
||
|
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
|
||
|
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"
|
||
|
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
|
||
|
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
|
||
|
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
|
||
|
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
|
||
|
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
|
||
|
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||
|
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
|
||
|
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
|
||
|
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
|
||
|
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
|
||
|
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
|
||
|
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
|
||
|
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
|
||
|
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps"
|
||
|
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "ps"
|
||
|
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
|
||
|
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
|
||
|
-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
|
||
|
-- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
|
||
|
-- Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0"
|
||
|
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "140"
|
||
|
-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "70"
|
||
|
-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "140"
|
||
|
-- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "23"
|
||
|
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
|
||
|
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "57.40000000"
|
||
|
-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "57.50000000"
|
||
|
-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "57.50000000"
|
||
|
-- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "0.10000000"
|
||
|
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
|
||
|
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
|
||
|
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
|
||
|
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "1"
|
||
|
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
|
||
|
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
|
||
|
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
|
||
|
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz"
|
||
|
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
|
||
|
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
|
||
|
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
|
||
|
-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
|
||
|
-- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "-2.40000000"
|
||
|
-- Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "0.00000000"
|
||
|
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
|
||
|
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
|
||
|
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ns"
|
||
|
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ns"
|
||
|
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "ps"
|
||
|
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
|
||
|
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
|
||
|
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
|
||
|
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
|
||
|
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
|
||
|
-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
|
||
|
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
|
||
|
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
|
||
|
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
|
||
|
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
|
||
|
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
|
||
|
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
|
||
|
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
|
||
|
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
|
||
|
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
|
||
|
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
|
||
|
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
|
||
|
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
|
||
|
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
|
||
|
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
|
||
|
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
|
||
|
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
|
||
|
-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
|
||
|
-- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
|
||
|
-- Retrieval info: PRIVATE: STICKY_CLK3 STRING "1"
|
||
|
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
|
||
|
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
|
||
|
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
||
|
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
|
||
|
-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
|
||
|
-- Retrieval info: PRIVATE: USE_CLK2 STRING "1"
|
||
|
-- Retrieval info: PRIVATE: USE_CLK3 STRING "1"
|
||
|
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
|
||
|
-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
|
||
|
-- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
|
||
|
-- Retrieval info: PRIVATE: USE_CLKENA3 STRING "0"
|
||
|
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
|
||
|
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
|
||
|
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
|
||
|
-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
|
||
|
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "33"
|
||
|
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
|
||
|
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "140"
|
||
|
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
|
||
|
-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "33"
|
||
|
-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
|
||
|
-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "70"
|
||
|
-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
|
||
|
-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "33"
|
||
|
-- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
|
||
|
-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "140"
|
||
|
-- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "-2400"
|
||
|
-- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "270"
|
||
|
-- Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50"
|
||
|
-- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "1"
|
||
|
-- Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0"
|
||
|
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
|
||
|
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
|
||
|
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||
|
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
|
||
|
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
|
||
|
-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
|
||
|
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
|
||
|
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
|
||
|
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
|
||
|
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
|
||
|
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
|
||
|
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
|
||
|
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
|
||
|
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
|
||
|
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
|
||
|
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
|
||
|
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
|
||
|
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
|
||
|
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
|
||
|
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
|
||
|
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
|
||
|
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
|
||
|
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
|
||
|
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
|
||
|
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
|
||
|
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
|
||
|
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
|
||
|
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
|
||
|
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
|
||
|
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
|
||
|
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
|
||
|
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
|
||
|
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
|
||
|
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
|
||
|
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED"
|
||
|
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
|
||
|
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
|
||
|
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
|
||
|
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
|
||
|
-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
|
||
|
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
|
||
|
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
|
||
|
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
|
||
|
-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
|
||
|
-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
|
||
|
-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
|
||
|
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
|
||
|
-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
|
||
|
-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
|
||
|
-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
|
||
|
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
|
||
|
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
|
||
|
-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
|
||
|
-- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
|
||
|
-- Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3"
|
||
|
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
|
||
|
-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
|
||
|
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
|
||
|
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
|
||
|
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
|
||
|
-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
|
||
|
-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
|
||
|
-- Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3
|
||
|
-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
|
||
|
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_ntsc.vhd TRUE
|
||
|
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_ntsc.ppf TRUE
|
||
|
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_ntsc.inc FALSE
|
||
|
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_ntsc.cmp TRUE
|
||
|
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_ntsc.bsf FALSE
|
||
|
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_ntsc_inst.vhd FALSE
|
||
|
-- Retrieval info: LIB_FILE: altera_mf
|
||
|
-- Retrieval info: CBX_MODULE_PREFIX: ON
|
||
| mist/pll_pal.cmp | ||
|---|---|---|
|
--Copyright (C) 1991-2013 Altera Corporation
|
||
|
--Your use of Altera Corporation's design tools, logic functions
|
||
|
--and other software and tools, and its AMPP partner logic
|
||
|
--functions, and any output files from any of the foregoing
|
||
|
--(including device programming or simulation files), and any
|
||
|
--associated documentation or information are expressly subject
|
||
|
--to the terms and conditions of the Altera Program License
|
||
|
--Subscription Agreement, Altera MegaCore Function License
|
||
|
--Agreement, or other applicable license agreement, including,
|
||
|
--without limitation, that your use is for the sole purpose of
|
||
|
--programming logic devices manufactured by Altera and sold by
|
||
|
--Altera or its authorized distributors. Please refer to the
|
||
|
--applicable agreement for further details.
|
||
|
|
||
|
|
||
|
component pll_pal
|
||
|
PORT
|
||
|
(
|
||
|
inclk0 : IN STD_LOGIC := '0';
|
||
|
c0 : OUT STD_LOGIC ;
|
||
|
c1 : OUT STD_LOGIC ;
|
||
|
c2 : OUT STD_LOGIC ;
|
||
|
c3 : OUT STD_LOGIC ;
|
||
|
locked : OUT STD_LOGIC
|
||
|
);
|
||
|
end component;
|
||
| mist/pll_pal.ppf | ||
|---|---|---|
|
<?xml version="1.0" encoding="UTF-8" ?>
|
||
|
<!DOCTYPE pinplan>
|
||
|
<pinplan intended_family="Cyclone III" variation_name="pll_pal" megafunction_name="ALTPLL" specifies="all_ports">
|
||
|
<global>
|
||
|
<pin name="inclk0" direction="input" scope="external" source="clock" />
|
||
|
<pin name="c0" direction="output" scope="external" source="clock" />
|
||
|
<pin name="c1" direction="output" scope="external" source="clock" />
|
||
|
<pin name="c2" direction="output" scope="external" source="clock" />
|
||
|
<pin name="c3" direction="output" scope="external" source="clock" />
|
||
|
<pin name="locked" direction="output" scope="external" />
|
||
|
|
||
|
</global>
|
||
|
</pinplan>
|
||
| mist/pll_pal.qip | ||
|---|---|---|
|
set_global_assignment -name IP_TOOL_NAME "ALTPLL"
|
||
|
set_global_assignment -name IP_TOOL_VERSION "13.0"
|
||
|
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll_pal.vhd"]
|
||
|
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_pal.cmp"]
|
||
|
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_pal.ppf"]
|
||
| mist/pll_pal.vhd | ||
|---|---|---|
|
-- megafunction wizard: %ALTPLL%
|
||
|
-- GENERATION: STANDARD
|
||
|
-- VERSION: WM1.0
|
||
|
-- MODULE: altpll
|
||
|
|
||
|
-- ============================================================
|
||
|
-- File Name: pll_pal.vhd
|
||
|
-- Megafunction Name(s):
|
||
|
-- altpll
|
||
|
--
|
||
|
-- Simulation Library Files(s):
|
||
|
-- altera_mf
|
||
|
-- ============================================================
|
||
|
-- ************************************************************
|
||
|
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||
|
--
|
||
|
-- 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
|
||
|
-- ************************************************************
|
||
|
|
||
|
|
||
|
--Copyright (C) 1991-2013 Altera Corporation
|
||
|
--Your use of Altera Corporation's design tools, logic functions
|
||
|
--and other software and tools, and its AMPP partner logic
|
||
|
--functions, and any output files from any of the foregoing
|
||
|
--(including device programming or simulation files), and any
|
||
|
--associated documentation or information are expressly subject
|
||
|
--to the terms and conditions of the Altera Program License
|
||
|
--Subscription Agreement, Altera MegaCore Function License
|
||
|
--Agreement, or other applicable license agreement, including,
|
||
|
--without limitation, that your use is for the sole purpose of
|
||
|
--programming logic devices manufactured by Altera and sold by
|
||
|
--Altera or its authorized distributors. Please refer to the
|
||
|
--applicable agreement for further details.
|
||
|
|
||
|
|
||
|
LIBRARY ieee;
|
||
|
USE ieee.std_logic_1164.all;
|
||
|
|
||
|
LIBRARY altera_mf;
|
||
|
USE altera_mf.all;
|
||
|
|
||
|
ENTITY pll_pal IS
|
||
|
PORT
|
||
|
(
|
||
|
inclk0 : IN STD_LOGIC := '0';
|
||
|
c0 : OUT STD_LOGIC ;
|
||
|
c1 : OUT STD_LOGIC ;
|
||
|
c2 : OUT STD_LOGIC ;
|
||
|
c3 : OUT STD_LOGIC ;
|
||
|
locked : OUT STD_LOGIC
|
||
|
);
|
||
|
END pll_pal;
|
||
|
|
||
|
|
||
|
ARCHITECTURE SYN OF pll_pal IS
|
||
|
|
||
|
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0);
|
||
|
SIGNAL sub_wire1 : STD_LOGIC ;
|
||
|
SIGNAL sub_wire2 : STD_LOGIC ;
|
||
|
SIGNAL sub_wire3 : STD_LOGIC ;
|
||
|
SIGNAL sub_wire4 : STD_LOGIC ;
|
||
|
SIGNAL sub_wire5 : STD_LOGIC ;
|
||
|
SIGNAL sub_wire6 : STD_LOGIC ;
|
||
|
SIGNAL sub_wire7 : STD_LOGIC_VECTOR (1 DOWNTO 0);
|
||
|
SIGNAL sub_wire8_bv : BIT_VECTOR (0 DOWNTO 0);
|
||
|
SIGNAL sub_wire8 : STD_LOGIC_VECTOR (0 DOWNTO 0);
|
||
|
|
||
|
|
||
|
|
||
|
COMPONENT altpll
|
||
|
GENERIC (
|
||
|
bandwidth_type : STRING;
|
||
|
clk0_divide_by : NATURAL;
|
||
|
clk0_duty_cycle : NATURAL;
|
||
|
clk0_multiply_by : NATURAL;
|
||
|
clk0_phase_shift : STRING;
|
||
|
clk1_divide_by : NATURAL;
|
||
|
clk1_duty_cycle : NATURAL;
|
||
|
clk1_multiply_by : NATURAL;
|
||
|
clk1_phase_shift : STRING;
|
||
|
clk2_divide_by : NATURAL;
|
||
|
clk2_duty_cycle : NATURAL;
|
||
|
clk2_multiply_by : NATURAL;
|
||
|
clk2_phase_shift : STRING;
|
||
|
clk3_divide_by : NATURAL;
|
||
|
clk3_duty_cycle : NATURAL;
|
||
|
clk3_multiply_by : NATURAL;
|
||
|
clk3_phase_shift : STRING;
|
||
|
compensate_clock : STRING;
|
||
|
inclk0_input_frequency : NATURAL;
|
||
|
intended_device_family : STRING;
|
||
|
lpm_hint : STRING;
|
||
|
lpm_type : STRING;
|
||
|
operation_mode : STRING;
|
||
|
pll_type : STRING;
|
||
|
port_activeclock : STRING;
|
||
|
port_areset : STRING;
|
||
|
port_clkbad0 : STRING;
|
||
|
port_clkbad1 : STRING;
|
||
|
port_clkloss : STRING;
|
||
|
port_clkswitch : STRING;
|
||
|
port_configupdate : STRING;
|
||
|
port_fbin : STRING;
|
||
|
port_inclk0 : STRING;
|
||
|
port_inclk1 : STRING;
|
||
|
port_locked : STRING;
|
||
|
port_pfdena : STRING;
|
||
|
port_phasecounterselect : STRING;
|
||
|
port_phasedone : STRING;
|
||
|
port_phasestep : STRING;
|
||
|
port_phaseupdown : STRING;
|
||
|
port_pllena : STRING;
|
||
|
port_scanaclr : STRING;
|
||
|
port_scanclk : STRING;
|
||
|
port_scanclkena : STRING;
|
||
|
port_scandata : STRING;
|
||
|
port_scandataout : STRING;
|
||
|
port_scandone : STRING;
|
||
|
port_scanread : STRING;
|
||
|
port_scanwrite : STRING;
|
||
|
port_clk0 : STRING;
|
||
|
port_clk1 : STRING;
|
||
|
port_clk2 : STRING;
|
||
|
port_clk3 : STRING;
|
||
|
port_clk4 : STRING;
|
||
|
port_clk5 : STRING;
|
||
|
port_clkena0 : STRING;
|
||
|
port_clkena1 : STRING;
|
||
|
port_clkena2 : STRING;
|
||
|
port_clkena3 : STRING;
|
||
|
port_clkena4 : STRING;
|
||
|
port_clkena5 : STRING;
|
||
|
port_extclk0 : STRING;
|
||
|
port_extclk1 : STRING;
|
||
|
port_extclk2 : STRING;
|
||
|
port_extclk3 : STRING;
|
||
|
self_reset_on_loss_lock : STRING;
|
||
|
width_clock : NATURAL
|
||
|
);
|
||
|
PORT (
|
||
|
clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
|
||
|
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
|
||
|
locked : OUT STD_LOGIC
|
||
|
);
|
||
|
END COMPONENT;
|
||
|
|
||
|
BEGIN
|
||
|
sub_wire8_bv(0 DOWNTO 0) <= "0";
|
||
|
sub_wire8 <= To_stdlogicvector(sub_wire8_bv);
|
||
|
sub_wire5 <= sub_wire0(2);
|
||
|
sub_wire4 <= sub_wire0(0);
|
||
|
sub_wire2 <= sub_wire0(3);
|
||
|
sub_wire1 <= sub_wire0(1);
|
||
|
c1 <= sub_wire1;
|
||
|
c3 <= sub_wire2;
|
||
|
locked <= sub_wire3;
|
||
|
c0 <= sub_wire4;
|
||
|
c2 <= sub_wire5;
|
||
|
sub_wire6 <= inclk0;
|
||
|
sub_wire7 <= sub_wire8(0 DOWNTO 0) & sub_wire6;
|
||
|
|
||
|
altpll_component : altpll
|
||
|
GENERIC MAP (
|
||
|
bandwidth_type => "AUTO",
|
||
|
clk0_divide_by => 5,
|
||
|
clk0_duty_cycle => 50,
|
||
|
clk0_multiply_by => 21,
|
||
|
clk0_phase_shift => "0",
|
||
|
clk1_divide_by => 10,
|
||
|
clk1_duty_cycle => 50,
|
||
|
clk1_multiply_by => 21,
|
||
|
clk1_phase_shift => "0",
|
||
|
clk2_divide_by => 5,
|
||
|
clk2_duty_cycle => 50,
|
||
|
clk2_multiply_by => 21,
|
||
|
clk2_phase_shift => "-2400",
|
||
|
clk3_divide_by => 2700,
|
||
|
clk3_duty_cycle => 50,
|
||
|
clk3_multiply_by => 1,
|
||
|
clk3_phase_shift => "0",
|
||
|
compensate_clock => "CLK0",
|
||
|
inclk0_input_frequency => 37037,
|
||
|
intended_device_family => "Cyclone III",
|
||
|
lpm_hint => "CBX_MODULE_PREFIX=pll_pal",
|
||
|
lpm_type => "altpll",
|
||
|
operation_mode => "NORMAL",
|
||
|
pll_type => "AUTO",
|
||
|
port_activeclock => "PORT_UNUSED",
|
||
|
port_areset => "PORT_UNUSED",
|
||
|
port_clkbad0 => "PORT_UNUSED",
|
||
|
port_clkbad1 => "PORT_UNUSED",
|
||
|
port_clkloss => "PORT_UNUSED",
|
||
|
port_clkswitch => "PORT_UNUSED",
|
||
|
port_configupdate => "PORT_UNUSED",
|
||
|
port_fbin => "PORT_UNUSED",
|
||
|
port_inclk0 => "PORT_USED",
|
||
|
port_inclk1 => "PORT_UNUSED",
|
||
|
port_locked => "PORT_USED",
|
||
|
port_pfdena => "PORT_UNUSED",
|
||
|
port_phasecounterselect => "PORT_UNUSED",
|
||
|
port_phasedone => "PORT_UNUSED",
|
||
|
port_phasestep => "PORT_UNUSED",
|
||
|
port_phaseupdown => "PORT_UNUSED",
|
||
|
port_pllena => "PORT_UNUSED",
|
||
|
port_scanaclr => "PORT_UNUSED",
|
||
|
port_scanclk => "PORT_UNUSED",
|
||
|
port_scanclkena => "PORT_UNUSED",
|
||
|
port_scandata => "PORT_UNUSED",
|
||
|
port_scandataout => "PORT_UNUSED",
|
||
|
port_scandone => "PORT_UNUSED",
|
||
|
port_scanread => "PORT_UNUSED",
|
||
|
port_scanwrite => "PORT_UNUSED",
|
||
|
port_clk0 => "PORT_USED",
|
||
|
port_clk1 => "PORT_USED",
|
||
|
port_clk2 => "PORT_USED",
|
||
|
port_clk3 => "PORT_USED",
|
||
|
port_clk4 => "PORT_UNUSED",
|
||
|
port_clk5 => "PORT_UNUSED",
|
||
|
port_clkena0 => "PORT_UNUSED",
|
||
|
port_clkena1 => "PORT_UNUSED",
|
||
|
port_clkena2 => "PORT_UNUSED",
|
||
|
port_clkena3 => "PORT_UNUSED",
|
||
|
port_clkena4 => "PORT_UNUSED",
|
||
|
port_clkena5 => "PORT_UNUSED",
|
||
|
port_extclk0 => "PORT_UNUSED",
|
||
|
port_extclk1 => "PORT_UNUSED",
|
||
|
port_extclk2 => "PORT_UNUSED",
|
||
|
port_extclk3 => "PORT_UNUSED",
|
||
|
self_reset_on_loss_lock => "OFF",
|
||
|
width_clock => 5
|
||
|
)
|
||
|
PORT MAP (
|
||
|
inclk => sub_wire7,
|
||
|
clk => sub_wire0,
|
||
Also available in: Unified diff
Improved timings for PAL and NTSC